Struct W

pub struct W<U, REG> { /* private fields */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CR>>

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn cen1(&mut self) -> CEN1_W<'_>

Bit 14 - DAC Channel 1 calibration enable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable

pub fn cen2(&mut self) -> CEN2_W<'_>

Bit 30 - DAC Channel 2 calibration enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag

impl W<u32, Reg<u32, _CCR>>

pub fn otrim1(&mut self) -> OTRIM1_W<'_>

Bits 0:4 - DAC Channel 1 offset trimming value

pub fn otrim2(&mut self) -> OTRIM2_W<'_>

Bits 16:20 - DAC Channel 2 offset trimming value

impl W<u32, Reg<u32, _MCR>>

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 0:2 - DAC Channel 1 mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 16:18 - DAC Channel 2 mode

impl W<u32, Reg<u32, _SHSR1>>

pub fn tsample1(&mut self) -> TSAMPLE1_W<'_>

Bits 0:9 - DAC Channel 1 sample Time

impl W<u32, Reg<u32, _SHSR2>>

pub fn tsample2(&mut self) -> TSAMPLE2_W<'_>

Bits 0:9 - DAC Channel 2 sample Time

impl W<u32, Reg<u32, _SHHR>>

pub fn thold1(&mut self) -> THOLD1_W<'_>

Bits 0:9 - DAC Channel 1 hold Time

pub fn thold2(&mut self) -> THOLD2_W<'_>

Bits 16:25 - DAC Channel 2 hold time

impl W<u32, Reg<u32, _SHRR>>

pub fn trefresh1(&mut self) -> TREFRESH1_W<'_>

Bits 0:7 - DAC Channel 1 refresh Time

pub fn trefresh2(&mut self) -> TREFRESH2_W<'_>

Bits 16:23 - DAC Channel 2 refresh Time

impl W<u32, Reg<u32, _IFCR>>

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel x global interrupt clear (x = 1 ..7)

impl W<u32, Reg<u32, _CCR1>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR1>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR1>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR1>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR2>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR2>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR2>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR2>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR3>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR3>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR3>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR3>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR4>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR4>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR4>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR4>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR5>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR5>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR5>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR5>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR6>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR6>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR6>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR6>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR7>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR7>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR7>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR7>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CSELR>>

pub fn c7s(&mut self) -> C7S_W<'_>

Bits 24:27 - DMA channel 7 selection

pub fn c6s(&mut self) -> C6S_W<'_>

Bits 20:23 - DMA channel 6 selection

pub fn c5s(&mut self) -> C5S_W<'_>

Bits 16:19 - DMA channel 5 selection

pub fn c4s(&mut self) -> C4S_W<'_>

Bits 12:15 - DMA channel 4 selection

pub fn c3s(&mut self) -> C3S_W<'_>

Bits 8:11 - DMA channel 3 selection

pub fn c2s(&mut self) -> C2S_W<'_>

Bits 4:7 - DMA channel 2 selection

pub fn c1s(&mut self) -> C1S_W<'_>

Bits 0:3 - DMA channel 1 selection

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - General-purpose 8-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - RESET bit

impl W<u32, Reg<u32, _INIT>>

pub fn init(&mut self) -> INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn polynomialcoefficients(&mut self) -> POLYNOMIALCOEFFICIENTS_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u8, Reg<u8, _DR8>>

pub fn dr8(&mut self) -> DR8_W<'_>

Bits 0:7 - Data register bits

impl W<u16, Reg<u16, _DR16>>

pub fn dr16(&mut self) -> DR16_W<'_>

Bits 0:15 - Data register bits

impl W<u32, Reg<u32, _CR>>

pub fn bias(&mut self) -> BIAS_W<'_>

Bits 5:6 - Bias selector

pub fn duty(&mut self) -> DUTY_W<'_>

Bits 2:4 - Duty selection

pub fn vsel(&mut self) -> VSEL_W<'_>

Bit 1 - Voltage source selection

pub fn lcden(&mut self) -> LCDEN_W<'_>

Bit 0 - LCD controller enable

pub fn mux_seg(&mut self) -> MUX_SEG_W<'_>

Bit 7 - Mux segment enable

pub fn bufen(&mut self) -> BUFEN_W<'_>

Bit 8 - Voltage output buffer enable

impl W<u32, Reg<u32, _FCR>>

pub fn ps(&mut self) -> PS_W<'_>

Bits 22:25 - PS 16-bit prescaler

pub fn div(&mut self) -> DIV_W<'_>

Bits 18:21 - DIV clock divider

pub fn blink(&mut self) -> BLINK_W<'_>

Bits 16:17 - Blink mode selection

pub fn blinkf(&mut self) -> BLINKF_W<'_>

Bits 13:15 - Blink frequency selection

pub fn cc(&mut self) -> CC_W<'_>

Bits 10:12 - Contrast control

pub fn dead(&mut self) -> DEAD_W<'_>

Bits 7:9 - Dead time duration

pub fn pon(&mut self) -> PON_W<'_>

Bits 4:6 - Pulse ON duration

pub fn uddie(&mut self) -> UDDIE_W<'_>

Bit 3 - Update display done interrupt enable

pub fn sofie(&mut self) -> SOFIE_W<'_>

Bit 1 - Start of frame interrupt enable

pub fn hd(&mut self) -> HD_W<'_>

Bit 0 - High drive enable

impl W<u32, Reg<u32, _SR>>

pub fn udr(&mut self) -> UDR_W<'_>

Bit 2 - Update display request

impl W<u32, Reg<u32, _CLR>>

pub fn uddc(&mut self) -> UDDC_W<'_>

Bit 3 - Update display done clear

pub fn sofc(&mut self) -> SOFC_W<'_>

Bit 1 - Start of frame flag clear

impl W<u32, Reg<u32, _RAM_COM0>>

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM1>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM2>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM3>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM4>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM5>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM6>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM7>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _CR>>

pub fn ctph(&mut self) -> CTPH_W<'_>

Bits 28:31 - Charge transfer pulse high

pub fn ctpl(&mut self) -> CTPL_W<'_>

Bits 24:27 - Charge transfer pulse low

pub fn ssd(&mut self) -> SSD_W<'_>

Bits 17:23 - Spread spectrum deviation

pub fn sse(&mut self) -> SSE_W<'_>

Bit 16 - Spread spectrum enable

pub fn sspsc(&mut self) -> SSPSC_W<'_>

Bit 15 - Spread spectrum prescaler

pub fn pgpsc(&mut self) -> PGPSC_W<'_>

Bits 12:14 - pulse generator prescaler

pub fn mcv(&mut self) -> MCV_W<'_>

Bits 5:7 - Max count value

pub fn iodef(&mut self) -> IODEF_W<'_>

Bit 4 - I/O Default mode

pub fn syncpol(&mut self) -> SYNCPOL_W<'_>

Bit 3 - Synchronization pin polarity

pub fn am(&mut self) -> AM_W<'_>

Bit 2 - Acquisition mode

pub fn start(&mut self) -> START_W<'_>

Bit 1 - Start a new acquisition

pub fn tsce(&mut self) -> TSCE_W<'_>

Bit 0 - Touch sensing controller enable

impl W<u32, Reg<u32, _IER>>

pub fn mceie(&mut self) -> MCEIE_W<'_>

Bit 1 - Max count error interrupt enable

pub fn eoaie(&mut self) -> EOAIE_W<'_>

Bit 0 - End of acquisition interrupt enable

impl W<u32, Reg<u32, _ICR>>

pub fn mceic(&mut self) -> MCEIC_W<'_>

Bit 1 - Max count error interrupt clear

pub fn eoaic(&mut self) -> EOAIC_W<'_>

Bit 0 - End of acquisition interrupt clear

impl W<u32, Reg<u32, _ISR>>

pub fn mcef(&mut self) -> MCEF_W<'_>

Bit 1 - Max count error flag

pub fn eoaf(&mut self) -> EOAF_W<'_>

Bit 0 - End of acquisition flag

impl W<u32, Reg<u32, _IOHCR>>

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOASCR>>

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOSCR>>

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOCCR>>

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOGCSR>>

pub fn g8e(&mut self) -> G8E_W<'_>

Bit 7 - Analog I/O group x enable

pub fn g7e(&mut self) -> G7E_W<'_>

Bit 6 - Analog I/O group x enable

pub fn g6e(&mut self) -> G6E_W<'_>

Bit 5 - Analog I/O group x enable

pub fn g5e(&mut self) -> G5E_W<'_>

Bit 4 - Analog I/O group x enable

pub fn g4e(&mut self) -> G4E_W<'_>

Bit 3 - Analog I/O group x enable

pub fn g3e(&mut self) -> G3E_W<'_>

Bit 2 - Analog I/O group x enable

pub fn g2e(&mut self) -> G2E_W<'_>

Bit 1 - Analog I/O group x enable

pub fn g1e(&mut self) -> G1E_W<'_>

Bit 0 - Analog I/O group x enable

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value (write only, read 0x0000)

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _COMP1_CSR>>

pub fn comp1_en(&mut self) -> COMP1_EN_W<'_>

Bit 0 - Comparator 1 enable bit

pub fn comp1_pwrmode(&mut self) -> COMP1_PWRMODE_W<'_>

Bits 2:3 - Power Mode of the comparator 1

pub fn comp1_inmsel(&mut self) -> COMP1_INMSEL_W<'_>

Bits 4:6 - Comparator 1 Input Minus connection configuration bit

pub fn comp1_inpsel(&mut self) -> COMP1_INPSEL_W<'_>

Bits 7:8 - Comparator1 input plus selection bit

pub fn comp1_polarity(&mut self) -> COMP1_POLARITY_W<'_>

Bit 15 - Comparator 1 polarity selection bit

pub fn comp1_hyst(&mut self) -> COMP1_HYST_W<'_>

Bits 16:17 - Comparator 1 hysteresis selection bits

pub fn comp1_blanking(&mut self) -> COMP1_BLANKING_W<'_>

Bits 18:20 - Comparator 1 blanking source selection bits

pub fn comp1_brgen(&mut self) -> COMP1_BRGEN_W<'_>

Bit 22 - Scaler bridge enable

pub fn comp1_scalen(&mut self) -> COMP1_SCALEN_W<'_>

Bit 23 - Voltage scaler enable bit

pub fn comp1_inmesel(&mut self) -> COMP1_INMESEL_W<'_>

Bits 25:26 - comparator 1 input minus extended selection bits

pub fn comp1_lock(&mut self) -> COMP1_LOCK_W<'_>

Bit 31 - COMP1_CSR register lock bit

impl W<u32, Reg<u32, _COMP2_CSR>>

pub fn comp2_en(&mut self) -> COMP2_EN_W<'_>

Bit 0 - Comparator 2 enable bit

pub fn comp2_pwrmode(&mut self) -> COMP2_PWRMODE_W<'_>

Bits 2:3 - Power Mode of the comparator 2

pub fn comp2_inmsel(&mut self) -> COMP2_INMSEL_W<'_>

Bits 4:6 - Comparator 2 Input Minus connection configuration bit

pub fn comp2_inpsel(&mut self) -> COMP2_INPSEL_W<'_>

Bits 7:8 - Comparator 2 Input Plus connection configuration bit

pub fn comp2_winmode(&mut self) -> COMP2_WINMODE_W<'_>

Bit 9 - Windows mode selection bit

pub fn comp2_polarity(&mut self) -> COMP2_POLARITY_W<'_>

Bit 15 - Comparator 2 polarity selection bit

pub fn comp2_hyst(&mut self) -> COMP2_HYST_W<'_>

Bits 16:17 - Comparator 2 hysteresis selection bits

pub fn comp2_blanking(&mut self) -> COMP2_BLANKING_W<'_>

Bits 18:20 - Comparator 2 blanking source selection bits

pub fn comp2_brgen(&mut self) -> COMP2_BRGEN_W<'_>

Bit 22 - Scaler bridge enable

pub fn comp2_scalen(&mut self) -> COMP2_SCALEN_W<'_>

Bit 23 - Voltage scaler enable bit

pub fn comp2_inmesel(&mut self) -> COMP2_INMESEL_W<'_>

Bits 25:26 - comparator 2 input minus extended selection bits

pub fn comp2_lock(&mut self) -> COMP2_LOCK_W<'_>

Bit 31 - COMP2_CSR register lock bit

impl W<u32, Reg<u32, _CSSA>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 8:23 - code segment start address

impl W<u32, Reg<u32, _CSL>>

pub fn leng(&mut self) -> LENG_W<'_>

Bits 8:21 - code segment length

impl W<u32, Reg<u32, _NVDSSA>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 8:23 - Non-volatile data segment start address

impl W<u32, Reg<u32, _NVDSL>>

pub fn leng(&mut self) -> LENG_W<'_>

Bits 8:21 - Non-volatile data segment length

impl W<u32, Reg<u32, _VDSSA>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 6:15 - Volatile data segment start address

impl W<u32, Reg<u32, _VDSL>>

pub fn leng(&mut self) -> LENG_W<'_>

Bits 6:15 - Non-volatile data segment length

impl W<u32, Reg<u32, _CR>>

pub fn vde(&mut self) -> VDE_W<'_>

Bit 2 - Volatile data execution

pub fn vds(&mut self) -> VDS_W<'_>

Bit 1 - Volatile data shared

pub fn fpa(&mut self) -> FPA_W<'_>

Bit 0 - Firewall pre alarm

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1(&mut self) -> OA1_W<'_>

Bits 0:9 - Interface address

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn dcen(&mut self) -> DCEN_W<'_>

Bit 10 - Data cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn dcrst(&mut self) -> DCRST_W<'_>

Bit 12 - Data cache reset

pub fn run_pd(&mut self) -> RUN_PD_W<'_>

Bit 13 - Flash Power-down mode during Low-power run mode

pub fn sleep_pd(&mut self) -> SLEEP_PD_W<'_>

Bit 14 - Flash Power-down mode during Low-power sleep mode

impl W<u32, Reg<u32, _PDKEYR>>

pub fn pdkeyr(&mut self) -> PDKEYR_W<'_>

Bits 0:31 - RUN_PD in FLASH_ACR key

impl W<u32, Reg<u32, _KEYR>>

pub fn keyr(&mut self) -> KEYR_W<'_>

Bits 0:31 - KEYR

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 3 - Programming error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protected error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn sizerr(&mut self) -> SIZERR_W<'_>

Bit 6 - Size error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

pub fn miserr(&mut self) -> MISERR_W<'_>

Bit 8 - Fast programming data miss error

pub fn fasterr(&mut self) -> FASTERR_W<'_>

Bit 9 - Fast programming error

pub fn rderr(&mut self) -> RDERR_W<'_>

Bit 14 - PCROP read error

pub fn optverr(&mut self) -> OPTVERR_W<'_>

Bit 15 - Option validity error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn mer1(&mut self) -> MER1_W<'_>

Bit 2 - Bank 1 Mass erase

pub fn pnb(&mut self) -> PNB_W<'_>

Bits 3:10 - Page number

pub fn bker(&mut self) -> BKER_W<'_>

Bit 11 - Bank erase

pub fn mer2(&mut self) -> MER2_W<'_>

Bit 15 - Bank 2 Mass erase

pub fn start(&mut self) -> START_W<'_>

Bit 16 - Start

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 17 - Options modification start

pub fn fstpg(&mut self) -> FSTPG_W<'_>

Bit 18 - Fast programming

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn rderrie(&mut self) -> RDERRIE_W<'_>

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 27 - Force the option byte loading

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 30 - Options Lock

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - FLASH_CR Lock

impl W<u32, Reg<u32, _ECCR>>

pub fn eccie(&mut self) -> ECCIE_W<'_>

Bit 24 - ECC correction interrupt enable

pub fn eccc(&mut self) -> ECCC_W<'_>

Bit 30 - ECC correction

pub fn eccd(&mut self) -> ECCD_W<'_>

Bit 31 - ECC detection

impl W<u32, Reg<u32, _OPTR>>

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 0:7 - Read protection level

pub fn bor_lev(&mut self) -> BOR_LEV_W<'_>

Bits 8:10 - BOR reset Level

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 12 - nRST_STOP

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 13 - nRST_STDBY

pub fn idwg_sw(&mut self) -> IDWG_SW_W<'_>

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&mut self) -> IWDG_STOP_W<'_>

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W<'_>

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&mut self) -> WWDG_SW_W<'_>

Bit 19 - Window watchdog selection

pub fn bfb2(&mut self) -> BFB2_W<'_>

Bit 20 - Dual-bank boot

pub fn dualbank(&mut self) -> DUALBANK_W<'_>

Bit 21 - Dual-Bank on 512 KB or 256 KB Flash memory devices

pub fn n_boot1(&mut self) -> NBOOT1_W<'_>

Bit 23 - Boot configuration

pub fn sram2_pe(&mut self) -> SRAM2_PE_W<'_>

Bit 24 - SRAM2 parity check enable

pub fn sram2_rst(&mut self) -> SRAM2_RST_W<'_>

Bit 25 - SRAM2 Erase when system reset

pub fn n_swboot0(&mut self) -> NSWBOOT0_W<'_>

Bit 26 - Software BOOT0

pub fn n_boot0(&mut self) -> NBOOT0_W<'_>

Bit 27 - nBOOT0 option bit

impl W<u32, Reg<u32, _PCROP1SR>>

pub fn pcrop1_strt(&mut self) -> PCROP1_STRT_W<'_>

Bits 0:15 - Bank 1 PCROP area start offset

impl W<u32, Reg<u32, _PCROP1ER>>

pub fn pcrop1_end(&mut self) -> PCROP1_END_W<'_>

Bits 0:15 - Bank 1 PCROP area end offset

pub fn pcrop_rdp(&mut self) -> PCROP_RDP_W<'_>

Bit 31 - PCROP area preserved when RDP level decreased

impl W<u32, Reg<u32, _WRP1AR>>

pub fn wrp1a_strt(&mut self) -> WRP1A_STRT_W<'_>

Bits 0:7 - Bank 1 WRP first area tart offset

pub fn wrp1a_end(&mut self) -> WRP1A_END_W<'_>

Bits 16:23 - Bank 1 WRP first area A end offset

impl W<u32, Reg<u32, _WRP1BR>>

pub fn wrp1b_strt(&mut self) -> WRP1B_STRT_W<'_>

Bits 16:23 - Bank 1 WRP second area B end offset

pub fn wrp1b_end(&mut self) -> WRP1B_END_W<'_>

Bits 0:7 - Bank 1 WRP second area B start offset

impl W<u32, Reg<u32, _PCROP2SR>>

pub fn pcrop2_strt(&mut self) -> PCROP2_STRT_W<'_>

Bits 0:15 - Bank 2 PCROP area start offset

impl W<u32, Reg<u32, _PCROP2ER>>

pub fn pcrop2_end(&mut self) -> PCROP2_END_W<'_>

Bits 0:15 - Bank 2 PCROP area end offset

impl W<u32, Reg<u32, _WRP2AR>>

pub fn wrp2a_strt(&mut self) -> WRP2A_STRT_W<'_>

Bits 0:7 - Bank 2 WRP first area A start offset

pub fn wrp2a_end(&mut self) -> WRP2A_END_W<'_>

Bits 16:23 - Bank 2 WRP first area A end offset

impl W<u32, Reg<u32, _WRP2BR>>

pub fn wrp2b_strt(&mut self) -> WRP2B_STRT_W<'_>

Bits 0:7 - Bank 2 WRP second area B start offset

pub fn wrp2b_end(&mut self) -> WRP2B_END_W<'_>

Bits 16:23 - Bank 2 WRP second area B end offset

impl W<u32, Reg<u32, _CR>>

pub fn pllsai1on(&mut self) -> PLLSAI1ON_W<'_>

Bit 26 - SAI1 PLL enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - Main PLL enable

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE crystal oscillator bypass

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hsiasfs(&mut self) -> HSIASFS_W<'_>

Bit 11 - HSI automatic start from Stop

pub fn hsikeron(&mut self) -> HSIKERON_W<'_>

Bit 9 - HSI always enable for peripheral kernels

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 8 - HSI clock enable

pub fn msirange(&mut self) -> MSIRANGE_W<'_>

Bits 4:7 - MSI clock ranges

pub fn msirgsel(&mut self) -> MSIRGSEL_W<'_>

Bit 3 - MSI clock range selection

pub fn msipllen(&mut self) -> MSIPLLEN_W<'_>

Bit 2 - MSI clock PLL enable

pub fn msion(&mut self) -> MSION_W<'_>

Bit 0 - MSI clock enable

impl W<u32, Reg<u32, _ICSCR>>

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 24:28 - HSI clock trimming

pub fn msitrim(&mut self) -> MSITRIM_W<'_>

Bits 8:15 - MSI clock trimming

impl W<u32, Reg<u32, _CFGR>>

pub fn mcosel(&mut self) -> MCOSEL_W<'_>

Bits 24:26 - Microcontroller clock output

pub fn stopwuck(&mut self) -> STOPWUCK_W<'_>

Bit 15 - Wakeup from Stop and CSS backup clock selection

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 11:13 - APB high-speed prescaler (APB2)

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 8:10 - PB low-speed prescaler (APB1)

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock switch

impl W<u32, Reg<u32, _PLLCFGR>>

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 25:26 - Main PLL division factor for PLLCLK (system clock)

pub fn pllren(&mut self) -> PLLREN_W<'_>

Bit 24 - Main PLL PLLCLK output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)

pub fn pllqen(&mut self) -> PLLQEN_W<'_>

Bit 20 - Main PLL PLLUSB1CLK output enable

pub fn pllp(&mut self) -> PLLP_W<'_>

Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)

pub fn pllpen(&mut self) -> PLLPEN_W<'_>

Bit 16 - Main PLL PLLSAI3CLK output enable

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 8:14 - Main PLL multiplication factor for VCO

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 4:6 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source

pub fn pllpdiv(&mut self) -> PLLPDIV_W<'_>

Bits 27:31 - Main PLL division factor for PLLSAI2CLK

impl W<u32, Reg<u32, _PLLSAI1CFGR>>

pub fn pllsai1r(&mut self) -> PLLSAI1R_W<'_>

Bits 25:26 - PLLSAI1 division factor for PLLADC1CLK (ADC clock)

pub fn pllsai1ren(&mut self) -> PLLSAI1REN_W<'_>

Bit 24 - PLLSAI1 PLLADC1CLK output enable

pub fn pllsai1q(&mut self) -> PLLSAI1Q_W<'_>

Bits 21:22 - SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)

pub fn pllsai1qen(&mut self) -> PLLSAI1QEN_W<'_>

Bit 20 - SAI1PLL PLLUSB2CLK output enable

pub fn pllsai1p(&mut self) -> PLLSAI1P_W<'_>

Bit 17 - SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)

pub fn pllsai1pen(&mut self) -> PLLSAI1PEN_W<'_>

Bit 16 - SAI1PLL PLLSAI1CLK output enable

pub fn pllsai1n(&mut self) -> PLLSAI1N_W<'_>

Bits 8:14 - SAI1PLL multiplication factor for VCO

pub fn pllsai1pdiv(&mut self) -> PLLSAI1PDIV_W<'_>

Bits 27:31 - PLLSAI1 division factor for PLLSAI1CLK

impl W<u32, Reg<u32, _CIER>>

pub fn lsecssie(&mut self) -> LSECSSIE_W<'_>

Bit 9 - LSE clock security system interrupt enable

pub fn pllsai1rdyie(&mut self) -> PLLSAI1RDYIE_W<'_>

Bit 6 - PLLSAI1 ready interrupt enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 5 - PLL ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 4 - HSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 3 - HSI ready interrupt enable

pub fn msirdyie(&mut self) -> MSIRDYIE_W<'_>

Bit 2 - MSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 1 - LSE ready interrupt enable

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 0 - LSI ready interrupt enable

pub fn hsi48rdyie(&mut self) -> HSI48RDYIE_W<'_>

Bit 10 - HSI48 ready interrupt enable

impl W<u32, Reg<u32, _CICR>>

pub fn lsecssc(&mut self) -> LSECSSC_W<'_>

Bit 9 - LSE Clock security system interrupt clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 8 - Clock security system interrupt clear

pub fn pllsai1rdyc(&mut self) -> PLLSAI1RDYC_W<'_>

Bit 6 - PLLSAI1 ready interrupt clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 5 - PLL ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 4 - HSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 3 - HSI ready interrupt clear

pub fn msirdyc(&mut self) -> MSIRDYC_W<'_>

Bit 2 - MSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 1 - LSE ready interrupt clear

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 0 - LSI ready interrupt clear

pub fn hsi48rdyc(&mut self) -> HSI48RDYC_W<'_>

Bit 10 - HSI48 oscillator ready interrupt clear

impl W<u32, Reg<u32, _AHB1RSTR>>

pub fn tscrst(&mut self) -> TSCRST_W<'_>

Bit 16 - Touch Sensing Controller reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 11 - CRC reset

pub fn flashrst(&mut self) -> FLASHRST_W<'_>

Bit 8 - Flash memory interface reset

pub fn dma2rst(&mut self) -> DMA2RST_W<'_>

Bit 1 - DMA2 reset

pub fn dma1rst(&mut self) -> DMA1RST_W<'_>

Bit 0 - DMA1 reset

impl W<u32, Reg<u32, _AHB2RSTR>>

pub fn rngrst(&mut self) -> RNGRST_W<'_>

Bit 18 - Random number generator reset

pub fn aesrst(&mut self) -> AESRST_W<'_>

Bit 16 - AES hardware accelerator reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 13 - ADC reset

pub fn gpiohrst(&mut self) -> GPIOHRST_W<'_>

Bit 7 - IO port H reset

pub fn gpioerst(&mut self) -> GPIOERST_W<'_>

Bit 4 - IO port E reset

pub fn gpiodrst(&mut self) -> GPIODRST_W<'_>

Bit 3 - IO port D reset

pub fn gpiocrst(&mut self) -> GPIOCRST_W<'_>

Bit 2 - IO port C reset

pub fn gpiobrst(&mut self) -> GPIOBRST_W<'_>

Bit 1 - IO port B reset

pub fn gpioarst(&mut self) -> GPIOARST_W<'_>

Bit 0 - IO port A reset

impl W<u32, Reg<u32, _AHB3RSTR>>

pub fn qspirst(&mut self) -> QSPIRST_W<'_>

Bit 8 - Quad SPI memory interface reset

impl W<u32, Reg<u32, _APB1RSTR1>>

pub fn lptim1rst(&mut self) -> LPTIM1RST_W<'_>

Bit 31 - Low Power Timer 1 reset

pub fn opamprst(&mut self) -> OPAMPRST_W<'_>

Bit 30 - OPAMP interface reset

pub fn dac1rst(&mut self) -> DAC1RST_W<'_>

Bit 29 - DAC1 interface reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn can1rst(&mut self) -> CAN1RST_W<'_>

Bit 25 - CAN1 reset

pub fn i2c3rst(&mut self) -> I2C3RST_W<'_>

Bit 23 - I2C3 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART3 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI3 reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn lcdrst(&mut self) -> LCDRST_W<'_>

Bit 9 - LCD interface reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - TIM7 timer reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - TIM6 timer reset

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 timer reset

pub fn usart4rst(&mut self) -> USART4RST_W<'_>

Bit 19 - USART4 reset.

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn crsrst(&mut self) -> CRSRST_W<'_>

Bit 24 - CRS reset

pub fn usbfsrst(&mut self) -> USBFSRST_W<'_>

Bit 26 - USB FS reset

impl W<u32, Reg<u32, _APB1RSTR2>>

pub fn lptim2rst(&mut self) -> LPTIM2RST_W<'_>

Bit 5 - Low-power timer 2 reset

pub fn swpmi1rst(&mut self) -> SWPMI1RST_W<'_>

Bit 2 - Single wire protocol reset

pub fn lpuart1rst(&mut self) -> LPUART1RST_W<'_>

Bit 0 - Low-power UART 1 reset

pub fn i2c4rst(&mut self) -> I2C4RST_W<'_>

Bit 1 - I2C4 reset

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn sai1rst(&mut self) -> SAI1RST_W<'_>

Bit 21 - Serial audio interface 1 (SAI1) reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim15rst(&mut self) -> TIM15RST_W<'_>

Bit 16 - TIM15 timer reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI1 reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn sdmmcrst(&mut self) -> SDMMCRST_W<'_>

Bit 10 - SDMMC reset

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 0 - System configuration (SYSCFG) reset

pub fn dfsdmrst(&mut self) -> DFSDMRST_W<'_>

Bit 24 - DFSDM filter reset

impl W<u32, Reg<u32, _AHB1ENR>>

pub fn tscen(&mut self) -> TSCEN_W<'_>

Bit 16 - Touch Sensing Controller clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 12 - CRC clock enable

pub fn flashen(&mut self) -> FLASHEN_W<'_>

Bit 8 - Flash memory interface clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - DMA2 clock enable

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - DMA1 clock enable

impl W<u32, Reg<u32, _AHB2ENR>>

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 18 - Random Number Generator clock enable

pub fn aesen(&mut self) -> AESEN_W<'_>

Bit 16 - AES accelerator clock enable

pub fn adcen(&mut self) -> ADCEN_W<'_>

Bit 13 - ADC clock enable

pub fn gpiohen(&mut self) -> GPIOHEN_W<'_>

Bit 7 - IO port H clock enable

pub fn gpioeen(&mut self) -> GPIOEEN_W<'_>

Bit 4 - IO port E clock enable

pub fn gpioden(&mut self) -> GPIODEN_W<'_>

Bit 3 - IO port D clock enable

pub fn gpiocen(&mut self) -> GPIOCEN_W<'_>

Bit 2 - IO port C clock enable

pub fn gpioben(&mut self) -> GPIOBEN_W<'_>

Bit 1 - IO port B clock enable

pub fn gpioaen(&mut self) -> GPIOAEN_W<'_>

Bit 0 - IO port A clock enable

impl W<u32, Reg<u32, _AHB3ENR>>

pub fn qspien(&mut self) -> QSPIEN_W<'_>

Bit 8 - QSPIEN

impl W<u32, Reg<u32, _APB1ENR1>>

pub fn lptim1en(&mut self) -> LPTIM1EN_W<'_>

Bit 31 - Low power timer 1 clock enable

pub fn opampen(&mut self) -> OPAMPEN_W<'_>

Bit 30 - OPAMP interface clock enable

pub fn dac1en(&mut self) -> DAC1EN_W<'_>

Bit 29 - DAC1 interface clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn can1en(&mut self) -> CAN1EN_W<'_>

Bit 25 - CAN1 clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>

Bit 23 - I2C3 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 18 - USART1 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI3 clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI peripheral 2 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn lcden(&mut self) -> LCDEN_W<'_>

Bit 9 - LCD clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - TIM7 timer clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - TIM6 timer clock enable

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - TIM2 timer clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>

Bit 10 - RTC APB clock enable

pub fn crsen(&mut self) -> CRSEN_W<'_>

Bit 24 - CRS clock enable

pub fn usbf(&mut self) -> USBF_W<'_>

Bit 26 - USB FS clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 timer clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>

Bit 19 - UART4 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

impl W<u32, Reg<u32, _APB1ENR2>>

pub fn lptim2en(&mut self) -> LPTIM2EN_W<'_>

Bit 5 - LPTIM2EN

pub fn swpmi1en(&mut self) -> SWPMI1EN_W<'_>

Bit 2 - Single wire protocol clock enable

pub fn lpuart1en(&mut self) -> LPUART1EN_W<'_>

Bit 0 - Low power UART 1 clock enable

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>

Bit 24 - DFSDMEN enable

pub fn i2c4en(&mut self) -> I2C4EN_W<'_>

Bit 1 - I2C4 clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn sai1en(&mut self) -> SAI1EN_W<'_>

Bit 21 - SAI1 clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 timer clock enable

pub fn tim15en(&mut self) -> TIM15EN_W<'_>

Bit 16 - TIM15 timer clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 timer clock enable

pub fn sdmmcen(&mut self) -> SDMMCEN_W<'_>

Bit 10 - SDMMC clock enable

pub fn firewallen(&mut self) -> FIREWALLEN_W<'_>

Bit 7 - Firewall clock enable

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 0 - SYSCFG clock enable

impl W<u32, Reg<u32, _AHB1SMENR>>

pub fn tscsmen(&mut self) -> TSCSMEN_W<'_>

Bit 16 - Touch Sensing Controller clocks enable during Sleep and Stop modes

pub fn crcsmen(&mut self) -> CRCSMEN_W<'_>

Bit 12 - CRCSMEN

pub fn sram1smen(&mut self) -> SRAM1SMEN_W<'_>

Bit 9 - SRAM1 interface clocks enable during Sleep and Stop modes

pub fn flashsmen(&mut self) -> FLASHSMEN_W<'_>

Bit 8 - Flash memory interface clocks enable during Sleep and Stop modes

pub fn dma2smen(&mut self) -> DMA2SMEN_W<'_>

Bit 1 - DMA2 clocks enable during Sleep and Stop modes

pub fn dma1smen(&mut self) -> DMA1SMEN_W<'_>

Bit 0 - DMA1 clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _AHB2SMENR>>

pub fn rngsmen(&mut self) -> RNGSMEN_W<'_>

Bit 18 - Random Number Generator clocks enable during Sleep and Stop modes

pub fn aessmen(&mut self) -> AESSMEN_W<'_>

Bit 16 - AES accelerator clocks enable during Sleep and Stop modes

pub fn adcfssmen(&mut self) -> ADCFSSMEN_W<'_>

Bit 13 - ADC clocks enable during Sleep and Stop modes

pub fn sram2smen(&mut self) -> SRAM2SMEN_W<'_>

Bit 9 - SRAM2 interface clocks enable during Sleep and Stop modes

pub fn gpiohsmen(&mut self) -> GPIOHSMEN_W<'_>

Bit 7 - IO port H clocks enable during Sleep and Stop modes

pub fn gpioesmen(&mut self) -> GPIOESMEN_W<'_>

Bit 4 - IO port E clocks enable during Sleep and Stop modes

pub fn gpiodsmen(&mut self) -> GPIODSMEN_W<'_>

Bit 3 - IO port D clocks enable during Sleep and Stop modes

pub fn gpiocsmen(&mut self) -> GPIOCSMEN_W<'_>

Bit 2 - IO port C clocks enable during Sleep and Stop modes

pub fn gpiobsmen(&mut self) -> GPIOBSMEN_W<'_>

Bit 1 - IO port B clocks enable during Sleep and Stop modes

pub fn gpioasmen(&mut self) -> GPIOASMEN_W<'_>

Bit 0 - IO port A clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _AHB3SMENR>>

pub fn qspismen(&mut self) -> QSPISMEN_W<'_>

Bit 8 - QSPISMEN

impl W<u32, Reg<u32, _APB1SMENR1>>

pub fn lptim1smen(&mut self) -> LPTIM1SMEN_W<'_>

Bit 31 - Low power timer 1 clocks enable during Sleep and Stop modes

pub fn opampsmen(&mut self) -> OPAMPSMEN_W<'_>

Bit 30 - OPAMP interface clocks enable during Sleep and Stop modes

pub fn dac1smen(&mut self) -> DAC1SMEN_W<'_>

Bit 29 - DAC1 interface clocks enable during Sleep and Stop modes

pub fn pwrsmen(&mut self) -> PWRSMEN_W<'_>

Bit 28 - Power interface clocks enable during Sleep and Stop modes

pub fn can1smen(&mut self) -> CAN1SMEN_W<'_>

Bit 25 - CAN1 clocks enable during Sleep and Stop modes

pub fn i2c3smen(&mut self) -> I2C3SMEN_W<'_>

Bit 23 - I2C3 clocks enable during Sleep and Stop modes

pub fn i2c1smen(&mut self) -> I2C1SMEN_W<'_>

Bit 21 - I2C1 clocks enable during Sleep and Stop modes

pub fn usart2smen(&mut self) -> USART2SMEN_W<'_>

Bit 18 - USART2 clocks enable during Sleep and Stop modes

pub fn usart1smen(&mut self) -> USART1SMEN_W<'_>

Bit 17 - USART1 clocks enable during Sleep and Stop modes

pub fn sp3smen(&mut self) -> SP3SMEN_W<'_>

Bit 15 - SPI3 clocks enable during Sleep and Stop modes

pub fn spi2smen(&mut self) -> SPI2SMEN_W<'_>

Bit 14 - SPI2 clocks enable during Sleep and Stop modes

pub fn wwdgsmen(&mut self) -> WWDGSMEN_W<'_>

Bit 11 - Window watchdog clocks enable during Sleep and Stop modes

pub fn lcdsmen(&mut self) -> LCDSMEN_W<'_>

Bit 9 - LCD clocks enable during Sleep and Stop modes

pub fn tim7smen(&mut self) -> TIM7SMEN_W<'_>

Bit 5 - TIM7 timer clocks enable during Sleep and Stop modes

pub fn tim6smen(&mut self) -> TIM6SMEN_W<'_>

Bit 4 - TIM6 timer clocks enable during Sleep and Stop modes

pub fn tim2smen(&mut self) -> TIM2SMEN_W<'_>

Bit 0 - TIM2 timer clocks enable during Sleep and Stop modes

pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W<'_>

Bit 10 - RTC APB clock enable during Sleep and Stop modes

pub fn usbfssmen(&mut self) -> USBFSSMEN_W<'_>

Bit 26 - USB FS clock enable during Sleep and Stop modes

pub fn i2c2smen(&mut self) -> I2C2SMEN_W<'_>

Bit 22 - I2C2 clocks enable during Sleep and Stop modes

pub fn crssmen(&mut self) -> CRSSMEN_W<'_>

Bit 24 - CRS clock enable during Sleep and Stop modes

impl W<u32, Reg<u32, _APB1SMENR2>>

pub fn lptim2smen(&mut self) -> LPTIM2SMEN_W<'_>

Bit 5 - LPTIM2SMEN

pub fn swpmi1smen(&mut self) -> SWPMI1SMEN_W<'_>

Bit 2 - Single wire protocol clocks enable during Sleep and Stop modes

pub fn lpuart1smen(&mut self) -> LPUART1SMEN_W<'_>

Bit 0 - Low power UART 1 clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _APB2SMENR>>

pub fn sai1smen(&mut self) -> SAI1SMEN_W<'_>

Bit 21 - SAI1 clocks enable during Sleep and Stop modes

pub fn tim16smen(&mut self) -> TIM16SMEN_W<'_>

Bit 17 - TIM16 timer clocks enable during Sleep and Stop modes

pub fn tim15smen(&mut self) -> TIM15SMEN_W<'_>

Bit 16 - TIM15 timer clocks enable during Sleep and Stop modes

pub fn usart1smen(&mut self) -> USART1SMEN_W<'_>

Bit 14 - USART1clocks enable during Sleep and Stop modes

pub fn spi1smen(&mut self) -> SPI1SMEN_W<'_>

Bit 12 - SPI1 clocks enable during Sleep and Stop modes

pub fn tim1smen(&mut self) -> TIM1SMEN_W<'_>

Bit 11 - TIM1 timer clocks enable during Sleep and Stop modes

pub fn sdmmcsmen(&mut self) -> SDMMCSMEN_W<'_>

Bit 10 - SDMMC clocks enable during Sleep and Stop modes

pub fn syscfgsmen(&mut self) -> SYSCFGSMEN_W<'_>

Bit 0 - SYSCFG clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _CCIPR>>

pub fn swpmi1sel(&mut self) -> SWPMI1SEL_W<'_>

Bit 30 - SWPMI1 clock source selection

pub fn adcsel(&mut self) -> ADCSEL_W<'_>

Bits 28:29 - ADCs clock source selection

pub fn clk48sel(&mut self) -> CLK48SEL_W<'_>

Bits 26:27 - 48 MHz clock source selection

pub fn sai1sel(&mut self) -> SAI1SEL_W<'_>

Bits 22:23 - SAI1 clock source selection

pub fn lptim2sel(&mut self) -> LPTIM2SEL_W<'_>

Bits 20:21 - Low power timer 2 clock source selection

pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<'_>

Bits 18:19 - Low power timer 1 clock source selection

pub fn i2c3sel(&mut self) -> I2C3SEL_W<'_>

Bits 16:17 - I2C3 clock source selection

pub fn i2c1sel(&mut self) -> I2C1SEL_W<'_>

Bits 12:13 - I2C1 clock source selection

pub fn lpuart1sel(&mut self) -> LPUART1SEL_W<'_>

Bits 10:11 - LPUART1 clock source selection

pub fn usart2sel(&mut self) -> USART2SEL_W<'_>

Bits 2:3 - USART2 clock source selection

pub fn usart1sel(&mut self) -> USART1SEL_W<'_>

Bits 0:1 - USART1 clock source selection

pub fn usart4sel(&mut self) -> USART4SEL_W<'_>

Bits 6:7 - USART4 clock source selection

pub fn usart3sel(&mut self) -> USART3SEL_W<'_>

Bits 4:5 - USART3 clock source selection

pub fn i2c2sel(&mut self) -> I2C2SEL_W<'_>

Bits 14:15 - I2C2 clock source selection

impl W<u32, Reg<u32, _BDCR>>

pub fn lscosel(&mut self) -> LSCOSEL_W<'_>

Bit 25 - Low speed clock output selection

pub fn lscoen(&mut self) -> LSCOEN_W<'_>

Bit 24 - Low speed clock output enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn lsecsson(&mut self) -> LSECSSON_W<'_>

Bit 5 - LSECSSON

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - SE oscillator drive capability

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - LSE oscillator bypass

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - LSE oscillator enable

impl W<u32, Reg<u32, _CSR>>

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 23 - Remove reset flag

pub fn msisrange(&mut self) -> MSISRANGE_W<'_>

Bits 8:11 - SI range after Standby mode

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - LSI oscillator enable

impl W<u32, Reg<u32, _CRRCR>>

pub fn hsi48on(&mut self) -> HSI48ON_W<'_>

Bit 0 - HSI48 clock enable

impl W<u32, Reg<u32, _CR1>>

pub fn lpr(&mut self) -> LPR_W<'_>

Bit 14 - Low-power run

pub fn vos(&mut self) -> VOS_W<'_>

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn lpms(&mut self) -> LPMS_W<'_>

Bits 0:2 - Low-power mode selection

impl W<u32, Reg<u32, _CR2>>

pub fn usv(&mut self) -> USV_W<'_>

Bit 10 - VDDUSB USB supply valid

pub fn iosv(&mut self) -> IOSV_W<'_>

Bit 9 - VDDIO2 Independent I/Os supply valid

pub fn pvme4(&mut self) -> PVME4_W<'_>

Bit 7 - Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V

pub fn pvme3(&mut self) -> PVME3_W<'_>

Bit 6 - Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V

pub fn pvme2(&mut self) -> PVME2_W<'_>

Bit 5 - Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V

pub fn pvme1(&mut self) -> PVME1_W<'_>

Bit 4 - Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V

pub fn pls(&mut self) -> PLS_W<'_>

Bits 1:3 - Power voltage detector level selection

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 0 - Power voltage detector enable

impl W<u32, Reg<u32, _CR3>>

pub fn ewf(&mut self) -> EWF_W<'_>

Bit 15 - Enable internal wakeup line

pub fn apc(&mut self) -> APC_W<'_>

Bit 10 - Apply pull-up and pull-down configuration

pub fn rrs(&mut self) -> RRS_W<'_>

Bit 8 - SRAM2 retention in Standby mode

pub fn ewup5(&mut self) -> EWUP5_W<'_>

Bit 4 - Enable Wakeup pin WKUP5

pub fn ewup4(&mut self) -> EWUP4_W<'_>

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup3(&mut self) -> EWUP3_W<'_>

Bit 2 - Enable Wakeup pin WKUP3

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 0 - Enable Wakeup pin WKUP1

impl W<u32, Reg<u32, _CR4>>

pub fn vbrs(&mut self) -> VBRS_W<'_>

Bit 9 - VBAT battery charging resistor selection

pub fn vbe(&mut self) -> VBE_W<'_>

Bit 8 - VBAT battery charging enable

pub fn wp5(&mut self) -> WP5_W<'_>

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp4(&mut self) -> WP4_W<'_>

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp3(&mut self) -> WP3_W<'_>

Bit 2 - Wakeup pin WKUP3 polarity

pub fn wp2(&mut self) -> WP2_W<'_>

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp1(&mut self) -> WP1_W<'_>

Bit 0 - Wakeup pin WKUP1 polarity

impl W<u32, Reg<u32, _SCR>>

pub fn sbf(&mut self) -> SBF_W<'_>

Bit 8 - Clear standby flag

pub fn wuf5(&mut self) -> WUF5_W<'_>

Bit 4 - Clear wakeup flag 5

pub fn wuf4(&mut self) -> WUF4_W<'_>

Bit 3 - Clear wakeup flag 4

pub fn wuf3(&mut self) -> WUF3_W<'_>

Bit 2 - Clear wakeup flag 3

pub fn wuf2(&mut self) -> WUF2_W<'_>

Bit 1 - Clear wakeup flag 2

pub fn wuf1(&mut self) -> WUF1_W<'_>

Bit 0 - Clear wakeup flag 1

impl W<u32, Reg<u32, _PUCRA>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port A pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRA>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port A pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRB>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port B pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRB>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port B pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRC>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port C pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port C pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port C pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port C pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port C pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port C pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port C pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port C pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port C pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port C pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port C pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port C pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRC>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port C pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRD>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port D pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port D pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port D pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port D pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port D pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port D pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port D pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port D pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port D pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port D pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port D pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port D pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port D pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRD>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port D pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port D pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port D pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port D pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port D pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port D pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port D pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port D pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRE>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port E pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port E pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port E pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port E pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port E pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port E pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port E pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port E pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port E pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port E pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port E pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port E pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port E pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port E pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port E pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port E pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRE>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port E pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port E pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port E pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port E pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port E pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port E pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port E pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port E pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port E pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port E pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port E pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port E pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port E pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port E pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port E pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port E pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRF>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port F pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port F pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port F pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port F pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port F pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port F pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port F pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port F pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port F pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port F pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port F pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port F pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port F pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port F pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRF>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port F pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port F pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port F pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port F pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port F pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port F pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port F pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port F pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port F pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port F pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port F pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port F pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port F pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port F pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRG>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port G pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port G pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port G pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port G pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port G pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port G pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port G pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port G pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port G pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port G pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port G pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port G pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port G pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port G pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port G pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port G pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRG>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port G pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port G pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port G pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port G pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port G pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port G pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port G pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port G pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port G pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port G pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port G pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port G pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port G pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port G pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port G pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port G pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRH>>

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port H pull-up bit y (y=0..1)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port H pull-up bit y (y=0..1)

impl W<u32, Reg<u32, _PDCRH>>

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port H pull-down bit y (y=0..1)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port H pull-down bit y (y=0..1)

impl W<u32, Reg<u32, _MEMRMP>>

pub fn fb_mode(&mut self) -> FB_MODE_W<'_>

Bit 8 - Flash Bank mode selection

pub fn qfs(&mut self) -> QFS_W<'_>

Bit 3 - QUADSPI memory mapping swap

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:2 - Memory mapping selection

impl W<u32, Reg<u32, _CFGR1>>

pub fn fpu_ie(&mut self) -> FPU_IE_W<'_>

Bits 26:31 - Floating Point Unit interrupts enable bits

pub fn i2c3_fmp(&mut self) -> I2C3_FMP_W<'_>

Bit 22 - I2C3 Fast-mode Plus driving capability activation

pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>

Bit 21 - I2C2 Fast-mode Plus driving capability activation

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>

Bit 20 - I2C1 Fast-mode Plus driving capability activation

pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<'_>

Bit 19 - Fast-mode Plus (Fm+) driving capability activation on PB9

pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<'_>

Bit 18 - Fast-mode Plus (Fm+) driving capability activation on PB8

pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<'_>

Bit 17 - Fast-mode Plus (Fm+) driving capability activation on PB7

pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<'_>

Bit 16 - Fast-mode Plus (Fm+) driving capability activation on PB6

pub fn boosten(&mut self) -> BOOSTEN_W<'_>

Bit 8 - I/O analog switch voltage booster enable

pub fn fwdis(&mut self) -> FWDIS_W<'_>

Bit 0 - Firewall disable

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:14 - EXTI 3 configuration bits

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:10 - EXTI 2 configuration bits

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:6 - EXTI 1 configuration bits

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:2 - EXTI 0 configuration bits

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:14 - EXTI 7 configuration bits

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:10 - EXTI 6 configuration bits

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:6 - EXTI 5 configuration bits

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:2 - EXTI 4 configuration bits

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:14 - EXTI 11 configuration bits

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:10 - EXTI 10 configuration bits

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:6 - EXTI 9 configuration bits

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:2 - EXTI 8 configuration bits

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:14 - EXTI15 configuration bits

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:10 - EXTI14 configuration bits

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:6 - EXTI13 configuration bits

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:2 - EXTI12 configuration bits

impl W<u32, Reg<u32, _SCSR>>

pub fn sram2er(&mut self) -> SRAM2ER_W<'_>

Bit 0 - SRAM2 Erase

impl W<u32, Reg<u32, _CFGR2>>

pub fn spf(&mut self) -> SPF_W<'_>

Bit 8 - SRAM2 parity error flag

pub fn eccl(&mut self) -> ECCL_W<'_>

Bit 3 - ECC Lock

pub fn pvdl(&mut self) -> PVDL_W<'_>

Bit 2 - PVD lock enable bit

pub fn spl(&mut self) -> SPL_W<'_>

Bit 1 - SRAM2 parity lock bit

pub fn cll(&mut self) -> CLL_W<'_>

Bit 0 - OCKUP (Hardfault) output enable bit

impl W<u32, Reg<u32, _SWPR>>

pub fn p31wp(&mut self) -> P31WP_W<'_>

Bit 31 - SRAM2 page 31 write protection

pub fn p30wp(&mut self) -> P30WP_W<'_>

Bit 30 - P30WP

pub fn p29wp(&mut self) -> P29WP_W<'_>

Bit 29 - P29WP

pub fn p28wp(&mut self) -> P28WP_W<'_>

Bit 28 - P28WP

pub fn p27wp(&mut self) -> P27WP_W<'_>

Bit 27 - P27WP

pub fn p26wp(&mut self) -> P26WP_W<'_>

Bit 26 - P26WP

pub fn p25wp(&mut self) -> P25WP_W<'_>

Bit 25 - P25WP

pub fn p24wp(&mut self) -> P24WP_W<'_>

Bit 24 - P24WP

pub fn p23wp(&mut self) -> P23WP_W<'_>

Bit 23 - P23WP

pub fn p22wp(&mut self) -> P22WP_W<'_>

Bit 22 - P22WP

pub fn p21wp(&mut self) -> P21WP_W<'_>

Bit 21 - P21WP

pub fn p20wp(&mut self) -> P20WP_W<'_>

Bit 20 - P20WP

pub fn p19wp(&mut self) -> P19WP_W<'_>

Bit 19 - P19WP

pub fn p18wp(&mut self) -> P18WP_W<'_>

Bit 18 - P18WP

pub fn p17wp(&mut self) -> P17WP_W<'_>

Bit 17 - P17WP

pub fn p16wp(&mut self) -> P16WP_W<'_>

Bit 16 - P16WP

pub fn p15wp(&mut self) -> P15WP_W<'_>

Bit 15 - P15WP

pub fn p14wp(&mut self) -> P14WP_W<'_>

Bit 14 - P14WP

pub fn p13wp(&mut self) -> P13WP_W<'_>

Bit 13 - P13WP

pub fn p12wp(&mut self) -> P12WP_W<'_>

Bit 12 - P12WP

pub fn p11wp(&mut self) -> P11WP_W<'_>

Bit 11 - P11WP

pub fn p10wp(&mut self) -> P10WP_W<'_>

Bit 10 - P10WP

pub fn p9wp(&mut self) -> P9WP_W<'_>

Bit 9 - P9WP

pub fn p8wp(&mut self) -> P8WP_W<'_>

Bit 8 - P8WP

pub fn p7wp(&mut self) -> P7WP_W<'_>

Bit 7 - P7WP

pub fn p6wp(&mut self) -> P6WP_W<'_>

Bit 6 - P6WP

pub fn p5wp(&mut self) -> P5WP_W<'_>

Bit 5 - P5WP

pub fn p4wp(&mut self) -> P4WP_W<'_>

Bit 4 - P4WP

pub fn p3wp(&mut self) -> P3WP_W<'_>

Bit 3 - P3WP

pub fn p2wp(&mut self) -> P2WP_W<'_>

Bit 2 - P2WP

pub fn p1wp(&mut self) -> P1WP_W<'_>

Bit 1 - P1WP

pub fn p0wp(&mut self) -> P0WP_W<'_>

Bit 0 - P0WP

impl W<u32, Reg<u32, _SKR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - SRAM2 write protection key for software erase

impl W<u32, Reg<u32, _CR>>

pub fn ie(&mut self) -> IE_W<'_>

Bit 3 - Interrupt enable

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 2 - Random number generator enable

impl W<u32, Reg<u32, _SR>>

pub fn seis(&mut self) -> SEIS_W<'_>

Bit 6 - Seed error interrupt status

pub fn ceis(&mut self) -> CEIS_W<'_>

Bit 5 - Clock error interrupt status

impl W<u32, Reg<u32, _CR>>

pub fn dmaouten(&mut self) -> DMAOUTEN_W<'_>

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&mut self) -> DMAINEN_W<'_>

Bit 11 - Enable DMA management of data input phase

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn ccfie(&mut self) -> CCFIE_W<'_>

Bit 9 - CCF flag interrupt enable

pub fn errc(&mut self) -> ERRC_W<'_>

Bit 8 - Error clear

pub fn ccfc(&mut self) -> CCFC_W<'_>

Bit 7 - Computation Complete Flag Clear

pub fn chmod(&mut self) -> CHMOD_W<'_>

Bits 5:6 - AES chaining mode

pub fn mode(&mut self) -> MODE_W<'_>

Bits 3:4 - AES operating mode

pub fn datatype(&mut self) -> DATATYPE_W<'_>

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - AES enable

impl W<u32, Reg<u32, _DINR>>

pub fn aes_dinr(&mut self) -> AES_DINR_W<'_>

Bits 0:31 - Data Input Register

impl W<u32, Reg<u32, _KEYR0>>

pub fn aes_keyr0(&mut self) -> AES_KEYR0_W<'_>

Bits 0:31 - Data Output Register (LSB key [31:0])

impl W<u32, Reg<u32, _KEYR1>>

pub fn aes_keyr1(&mut self) -> AES_KEYR1_W<'_>

Bits 0:31 - AES key register (key [63:32])

impl W<u32, Reg<u32, _KEYR2>>

pub fn aes_keyr2(&mut self) -> AES_KEYR2_W<'_>

Bits 0:31 - AES key register (key [95:64])

impl W<u32, Reg<u32, _KEYR3>>

pub fn aes_keyr3(&mut self) -> AES_KEYR3_W<'_>

Bits 0:31 - AES key register (MSB key [127:96])

impl W<u32, Reg<u32, _IVR0>>

pub fn aes_ivr0(&mut self) -> AES_IVR0_W<'_>

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl W<u32, Reg<u32, _IVR1>>

pub fn aes_ivr1(&mut self) -> AES_IVR1_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl W<u32, Reg<u32, _IVR2>>

pub fn aes_ivr2(&mut self) -> AES_IVR2_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl W<u32, Reg<u32, _IVR3>>

pub fn aes_ivr3(&mut self) -> AES_IVR3_W<'_>

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl W<u32, Reg<u32, _ISR>>

pub fn jqovf(&mut self) -> JQOVF_W<'_>

Bit 10 - JQOVF

pub fn awd3(&mut self) -> AWD3_W<'_>

Bit 9 - AWD3

pub fn awd2(&mut self) -> AWD2_W<'_>

Bit 8 - AWD2

pub fn awd1(&mut self) -> AWD1_W<'_>

Bit 7 - AWD1

pub fn jeos(&mut self) -> JEOS_W<'_>

Bit 6 - JEOS

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 5 - JEOC

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 4 - OVR

pub fn eos(&mut self) -> EOS_W<'_>

Bit 3 - EOS

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 2 - EOC

pub fn eosmp(&mut self) -> EOSMP_W<'_>

Bit 1 - EOSMP

pub fn adrdy(&mut self) -> ADRDY_W<'_>

Bit 0 - ADRDY

impl W<u32, Reg<u32, _IER>>

pub fn jqovfie(&mut self) -> JQOVFIE_W<'_>

Bit 10 - JQOVFIE

pub fn awd3ie(&mut self) -> AWD3IE_W<'_>

Bit 9 - AWD3IE

pub fn awd2ie(&mut self) -> AWD2IE_W<'_>

Bit 8 - AWD2IE

pub fn awd1ie(&mut self) -> AWD1IE_W<'_>

Bit 7 - AWD1IE

pub fn jeosie(&mut self) -> JEOSIE_W<'_>

Bit 6 - JEOSIE

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 5 - JEOCIE

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 4 - OVRIE

pub fn eosie(&mut self) -> EOSIE_W<'_>

Bit 3 - EOSIE

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 2 - EOCIE

pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>

Bit 1 - EOSMPIE

pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>

Bit 0 - ADRDYIE

impl W<u32, Reg<u32, _CR>>

pub fn adcal(&mut self) -> ADCAL_W<'_>

Bit 31 - ADCAL

pub fn adcaldif(&mut self) -> ADCALDIF_W<'_>

Bit 30 - ADCALDIF

pub fn deeppwd(&mut self) -> DEEPPWD_W<'_>

Bit 29 - DEEPPWD

pub fn advregen(&mut self) -> ADVREGEN_W<'_>

Bit 28 - ADVREGEN

pub fn jadstp(&mut self) -> JADSTP_W<'_>

Bit 5 - JADSTP

pub fn adstp(&mut self) -> ADSTP_W<'_>

Bit 4 - ADSTP

pub fn jadstart(&mut self) -> JADSTART_W<'_>

Bit 3 - JADSTART

pub fn adstart(&mut self) -> ADSTART_W<'_>

Bit 2 - ADSTART

pub fn addis(&mut self) -> ADDIS_W<'_>

Bit 1 - ADDIS

pub fn aden(&mut self) -> ADEN_W<'_>

Bit 0 - ADEN

impl W<u32, Reg<u32, _CFGR>>

pub fn awdch1ch(&mut self) -> AWDCH1CH_W<'_>

Bits 26:30 - AWDCH1CH

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 25 - JAUTO

pub fn jawd1en(&mut self) -> JAWD1EN_W<'_>

Bit 24 - JAWD1EN

pub fn awd1en(&mut self) -> AWD1EN_W<'_>

Bit 23 - AWD1EN

pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>

Bit 22 - AWD1SGL

pub fn jqm(&mut self) -> JQM_W<'_>

Bit 21 - JQM

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 20 - JDISCEN

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 17:19 - DISCNUM

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 16 - DISCEN

pub fn autoff(&mut self) -> AUTOFF_W<'_>

Bit 15 - AUTOFF

pub fn autdly(&mut self) -> AUTDLY_W<'_>

Bit 14 - AUTDLY

pub fn cont(&mut self) -> CONT_W<'_>

Bit 13 - CONT

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>

Bit 12 - OVRMOD

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 10:11 - EXTEN

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 6:9 - EXTSEL

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 5 - ALIGN

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - RES

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 1 - DMACFG

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMAEN

impl W<u32, Reg<u32, _CFGR2>>

pub fn rovsm(&mut self) -> ROVSM_W<'_>

Bit 10 - EXTEN

pub fn tovs(&mut self) -> TOVS_W<'_>

Bit 9 - EXTSEL

pub fn ovss(&mut self) -> OVSS_W<'_>

Bits 5:8 - ALIGN

pub fn ovsr(&mut self) -> OVSR_W<'_>

Bits 2:4 - RES

pub fn jovse(&mut self) -> JOVSE_W<'_>

Bit 1 - DMACFG

pub fn rovse(&mut self) -> ROVSE_W<'_>

Bit 0 - DMAEN

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sampling time selection

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp18(&mut self) -> SMP18_W<'_>

Bits 24:26 - Channel 18 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sampling time selection

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sampling time selection

impl W<u32, Reg<u32, _TR1>>

pub fn ht1(&mut self) -> HT1_W<'_>

Bits 16:27 - HT1

pub fn lt1(&mut self) -> LT1_W<'_>

Bits 0:11 - LT1

impl W<u32, Reg<u32, _TR2>>

pub fn ht2(&mut self) -> HT2_W<'_>

Bits 16:23 - HT2

pub fn lt2(&mut self) -> LT2_W<'_>

Bits 0:7 - LT2

impl W<u32, Reg<u32, _TR3>>

pub fn ht3(&mut self) -> HT3_W<'_>

Bits 16:23 - HT3

pub fn lt3(&mut self) -> LT3_W<'_>

Bits 0:7 - LT3

impl W<u32, Reg<u32, _SQR1>>

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 24:28 - SQ4

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 18:22 - SQ3

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 12:16 - SQ2

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 6:10 - SQ1

pub fn l(&mut self) -> L_W<'_>

Bits 0:3 - Regular channel sequence length

impl W<u32, Reg<u32, _SQR2>>

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 24:28 - SQ9

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 18:22 - SQ8

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 12:16 - SQ7

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 6:10 - SQ6

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 0:4 - SQ5

impl W<u32, Reg<u32, _SQR3>>

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 24:28 - SQ14

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 18:22 - SQ13

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 12:16 - SQ12

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 6:10 - SQ11

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 0:4 - SQ10

impl W<u32, Reg<u32, _SQR4>>

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 6:10 - SQ16

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 0:4 - SQ15

impl W<u32, Reg<u32, _JSQR>>

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 26:30 - JSQ4

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 20:24 - JSQ3

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 14:18 - JSQ2

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 8:12 - JSQ1

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 6:7 - JEXTEN

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 2:5 - JEXTSEL

pub fn jl(&mut self) -> JL_W<'_>

Bits 0:1 - JL

impl W<u32, Reg<u32, _OFR1>>

pub fn offset1_en(&mut self) -> OFFSET1_EN_W<'_>

Bit 31 - OFFSET1_EN

pub fn offset1_ch(&mut self) -> OFFSET1_CH_W<'_>

Bits 26:30 - OFFSET1_CH

pub fn offset1(&mut self) -> OFFSET1_W<'_>

Bits 0:11 - OFFSET1

impl W<u32, Reg<u32, _OFR2>>

pub fn offset2_en(&mut self) -> OFFSET2_EN_W<'_>

Bit 31 - OFFSET2_EN

pub fn offset2_ch(&mut self) -> OFFSET2_CH_W<'_>

Bits 26:30 - OFFSET2_CH

pub fn offset2(&mut self) -> OFFSET2_W<'_>

Bits 0:11 - OFFSET2

impl W<u32, Reg<u32, _OFR3>>

pub fn offset3_en(&mut self) -> OFFSET3_EN_W<'_>

Bit 31 - OFFSET3_EN

pub fn offset3_ch(&mut self) -> OFFSET3_CH_W<'_>

Bits 26:30 - OFFSET3_CH

pub fn offset3(&mut self) -> OFFSET3_W<'_>

Bits 0:11 - OFFSET3

impl W<u32, Reg<u32, _OFR4>>

pub fn offset4_en(&mut self) -> OFFSET4_EN_W<'_>

Bit 31 - OFFSET4_EN

pub fn offset4_ch(&mut self) -> OFFSET4_CH_W<'_>

Bits 26:30 - OFFSET4_CH

pub fn offset4(&mut self) -> OFFSET4_W<'_>

Bits 0:11 - OFFSET4

impl W<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&mut self) -> AWD2CH_W<'_>

Bits 1:18 - AWD2CH

impl W<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&mut self) -> AWD3CH_W<'_>

Bits 1:18 - AWD3CH

impl W<u32, Reg<u32, _DIFSEL>>

pub fn difsel_1_15(&mut self) -> DIFSEL_1_15_W<'_>

Bits 1:15 - Differential mode for channels 15 to 1

impl W<u32, Reg<u32, _CALFACT>>

pub fn calfact_d(&mut self) -> CALFACT_D_W<'_>

Bits 16:22 - CALFACT_D

pub fn calfact_s(&mut self) -> CALFACT_S_W<'_>

Bits 0:6 - CALFACT_S

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _CR1>>

pub fn mckdiv(&mut self) -> MCKDIV_W<'_>

Bits 20:23 - Master clock divider

pub fn nodiv(&mut self) -> NODIV_W<'_>

Bit 19 - No divider

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 17 - DMA enable

pub fn saien(&mut self) -> SAIEN_W<'_>

Bit 16 - Audio block A enable

pub fn outdriv(&mut self) -> OUTDRIV_W<'_>

Bit 13 - Output drive

pub fn mono(&mut self) -> MONO_W<'_>

Bit 12 - Mono mode

pub fn syncen(&mut self) -> SYNCEN_W<'_>

Bits 10:11 - Synchronization enable

pub fn ckstr(&mut self) -> CKSTR_W<'_>

Bit 9 - Clock strobing edge

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 8 - Least significant bit first

pub fn ds(&mut self) -> DS_W<'_>

Bits 5:7 - Data size

pub fn prtcfg(&mut self) -> PRTCFG_W<'_>

Bits 2:3 - Protocol configuration

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Audio block mode

impl W<u32, Reg<u32, _CR2>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 14:15 - Companding mode

pub fn cpl(&mut self) -> CPL_W<'_>

Bit 13 - Complement bit

pub fn mutecn(&mut self) -> MUTECN_W<'_>

Bits 7:12 - Mute counter

pub fn muteval(&mut self) -> MUTEVAL_W<'_>

Bit 6 - Mute value

pub fn mute(&mut self) -> MUTE_W<'_>

Bit 5 - Mute

pub fn tris(&mut self) -> TRIS_W<'_>

Bit 4 - Tristate management on data line

pub fn fflush(&mut self) -> FFLUSH_W<'_>

Bit 3 - FIFO flush

pub fn fth(&mut self) -> FTH_W<'_>

Bits 0:2 - FIFO threshold

impl W<u32, Reg<u32, _FRCR>>

pub fn fsoff(&mut self) -> FSOFF_W<'_>

Bit 18 - Frame synchronization offset

pub fn fspol(&mut self) -> FSPOL_W<'_>

Bit 17 - Frame synchronization polarity

pub fn fsdef(&mut self) -> FSDEF_W<'_>

Bit 16 - Frame synchronization definition

pub fn fsall(&mut self) -> FSALL_W<'_>

Bits 8:14 - Frame synchronization active level length

pub fn frl(&mut self) -> FRL_W<'_>

Bits 0:7 - Frame length

impl W<u32, Reg<u32, _SLOTR>>

pub fn sloten(&mut self) -> SLOTEN_W<'_>

Bits 16:31 - Slot enable

pub fn nbslot(&mut self) -> NBSLOT_W<'_>

Bits 8:11 - Number of slots in an audio frame

pub fn slotsz(&mut self) -> SLOTSZ_W<'_>

Bits 6:7 - Slot size

pub fn fboff(&mut self) -> FBOFF_W<'_>

Bits 0:4 - First bit offset

impl W<u32, Reg<u32, _IM>>

pub fn lfsdetie(&mut self) -> LFSDETIE_W<'_>

Bit 6 - Late frame synchronization detection interrupt enable

pub fn afsdetie(&mut self) -> AFSDETIE_W<'_>

Bit 5 - Anticipated frame synchronization detection interrupt enable

pub fn cnrdyie(&mut self) -> CNRDYIE_W<'_>

Bit 4 - Codec not ready interrupt enable

pub fn freqie(&mut self) -> FREQIE_W<'_>

Bit 3 - FIFO request interrupt enable

pub fn wckcfgie(&mut self) -> WCKCFGIE_W<'_>

Bit 2 - Wrong clock configuration interrupt enable

pub fn mutedetie(&mut self) -> MUTEDETIE_W<'_>

Bit 1 - Mute detection interrupt enable

pub fn ovrudrie(&mut self) -> OVRUDRIE_W<'_>

Bit 0 - Overrun/underrun interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn flvl(&mut self) -> FLVL_W<'_>

Bits 16:18 - FIFO level threshold

pub fn lfsdet(&mut self) -> LFSDET_W<'_>

Bit 6 - Late frame synchronization detection

pub fn afsdet(&mut self) -> AFSDET_W<'_>

Bit 5 - Anticipated frame synchronization detection

pub fn cnrdy(&mut self) -> CNRDY_W<'_>

Bit 4 - Codec not ready

pub fn freq(&mut self) -> FREQ_W<'_>

Bit 3 - FIFO request

pub fn wckcfg(&mut self) -> WCKCFG_W<'_>

Bit 2 - Wrong clock configuration flag. This bit is read only

pub fn mutedet(&mut self) -> MUTEDET_W<'_>

Bit 1 - Mute detection

pub fn ovrudr(&mut self) -> OVRUDR_W<'_>

Bit 0 - Overrun / underrun

impl W<u32, Reg<u32, _CLRFR>>

pub fn clfsdet(&mut self) -> CLFSDET_W<'_>

Bit 6 - Clear late frame synchronization detection flag

pub fn cafsdet(&mut self) -> CAFSDET_W<'_>

Bit 5 - Clear anticipated frame synchronization detection flag

pub fn ccnrdy(&mut self) -> CCNRDY_W<'_>

Bit 4 - Clear codec not ready flag

pub fn cwckcfg(&mut self) -> CWCKCFG_W<'_>

Bit 2 - Clear wrong clock configuration flag

pub fn cmutedet(&mut self) -> CMUTEDET_W<'_>

Bit 1 - Mute detection flag

pub fn covrudr(&mut self) -> COVRUDR_W<'_>

Bit 0 - Clear overrun / underrun

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn etr_rmp(&mut self) -> ETR_RMP_W<'_>

Bits 0:2 - Timer2 ETR remap

pub fn ti4_rmp(&mut self) -> TI4_RMP_W<'_>

Bits 3:4 - Internal trigger

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn ti1_rmp(&mut self) -> TI1_RMP_W<'_>

Bits 0:1 - Input capture 1 remap

impl W<u32, Reg<u32, _OR2>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&mut self) -> BKDFBK1E_W<'_>

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn etr_adc1_rmp(&mut self) -> ETR_ADC1_RMP_W<'_>

Bits 0:1 - External trigger remap on ADC1 analog watchdog

pub fn etr_adc3_rmp(&mut self) -> ETR_ADC3_RMP_W<'_>

Bits 2:3 - External trigger remap on ADC3 analog watchdog

pub fn ti1_rmp(&mut self) -> TI1_RMP_W<'_>

Bit 4 - Input Capture 1 remap

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&mut self) -> OC6M_BIT3_W<'_>

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&mut self) -> OC5M_BIT3_W<'_>

Bits 16:18 - Output Compare 5 mode bit 3

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _OR2>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk0e(&mut self) -> BKDFBK0E_W<'_>

Bit 8 - BRK DFSDM_BREAK0 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _OR3>>

pub fn bk2ine(&mut self) -> BK2INE_W<'_>

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W<'_>

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W<'_>

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&mut self) -> BK2DFBK0E_W<'_>

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&mut self) -> BK2INP_W<'_>

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W<'_>

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W<'_>

Bit 11 - BRK2 COMP2 input polarity

impl W<u32, Reg<u32, _CR1>>

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _ICR>>

pub fn downcf(&mut self) -> DOWNCF_W<'_>

Bit 6 - Direction change to down Clear Flag

pub fn upcf(&mut self) -> UPCF_W<'_>

Bit 5 - Direction change to UP Clear Flag

pub fn arrokcf(&mut self) -> ARROKCF_W<'_>

Bit 4 - Autoreload register update OK Clear Flag

pub fn cmpokcf(&mut self) -> CMPOKCF_W<'_>

Bit 3 - Compare register update OK Clear Flag

pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<'_>

Bit 2 - External trigger valid edge Clear Flag

pub fn arrmcf(&mut self) -> ARRMCF_W<'_>

Bit 1 - Autoreload match Clear Flag

pub fn cmpmcf(&mut self) -> CMPMCF_W<'_>

Bit 0 - compare match Clear Flag

impl W<u32, Reg<u32, _IER>>

pub fn downie(&mut self) -> DOWNIE_W<'_>

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&mut self) -> UPIE_W<'_>

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&mut self) -> ARROKIE_W<'_>

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&mut self) -> CMPOKIE_W<'_>

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&mut self) -> EXTTRIGIE_W<'_>

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&mut self) -> ARRMIE_W<'_>

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&mut self) -> CMPMIE_W<'_>

Bit 0 - Compare match Interrupt Enable

impl W<u32, Reg<u32, _CFGR>>

pub fn enc(&mut self) -> ENC_W<'_>

Bit 24 - Encoder mode enable

pub fn countmode(&mut self) -> COUNTMODE_W<'_>

Bit 23 - counter mode enabled

pub fn preload(&mut self) -> PRELOAD_W<'_>

Bit 22 - Registers update mode

pub fn wavpol(&mut self) -> WAVPOL_W<'_>

Bit 21 - Waveform shape polarity

pub fn wave(&mut self) -> WAVE_W<'_>

Bit 20 - Waveform shape

pub fn timout(&mut self) -> TIMOUT_W<'_>

Bit 19 - Timeout enable

pub fn trigen(&mut self) -> TRIGEN_W<'_>

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>

Bits 13:15 - Trigger selector

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 9:11 - Clock prescaler

pub fn trgflt(&mut self) -> TRGFLT_W<'_>

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&mut self) -> CKFLT_W<'_>

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bits 1:2 - Clock Polarity

pub fn cksel(&mut self) -> CKSEL_W<'_>

Bit 0 - Clock selector

impl W<u32, Reg<u32, _CR>>

pub fn cntstrt(&mut self) -> CNTSTRT_W<'_>

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&mut self) -> SNGSTRT_W<'_>

Bit 1 - LPTIM start in single mode

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - LPTIM Enable

impl W<u32, Reg<u32, _CMP>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bits 0:15 - Compare value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto reload value

impl W<u32, Reg<u32, _CR1>>

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - Driver Enable de-assertion time

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - Driver Enable assertion time

impl W<u32, Reg<u32, _CR2>>

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn datainv(&mut self) -> DATAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn add(&mut self) -> ADD_W<'_>

Bits 24:31 - Address of the USART node

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

impl W<u32, Reg<u32, _CR3>>

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:15 - DIV_Mantissa

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _CR1>>

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - Driver Enable de-assertion time

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - Driver Enable assertion time

impl W<u32, Reg<u32, _CR2>>

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn datainv(&mut self) -> DATAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn add(&mut self) -> ADD_W<'_>

Bits 24:31 - Address of the USART node

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

impl W<u32, Reg<u32, _CR3>>

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

pub fn ucesm(&mut self) -> UCESM_W<'_>

Bit 23 - USART Clock Enable in Stop mode

pub fn tcbgtie(&mut self) -> TCBGTIE_W<'_>

Bit 24 - Transmission complete before guard time interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:11 - USARTDIV

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _CR1>>

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - Driver Enable assertion time

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - Driver Enable de-assertion time

impl W<u32, Reg<u32, _CR2>>

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn datainv(&mut self) -> DATAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn add(&mut self) -> ADD_W<'_>

Bits 24:31 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:19 - BRR

impl W<u32, Reg<u32, _RQR>>

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn crcl(&mut self) -> CRCL_W<'_>

Bit 11 - CRC length

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _POWER>>

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>

Bit 14 - HW Flow Control enable

pub fn negedge(&mut self) -> NEGEDGE_W<'_>

Bit 13 - SDIO_CK dephasing selection bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>

Bits 11:12 - Wide bus mode enable bit

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 10 - Clock divider bypass enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>

Bit 9 - Power saving configuration bit

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 8 - Clock enable bit

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 0:7 - Clock divide factor

impl W<u32, Reg<u32, _ARG>>

pub fn cmdarg(&mut self) -> CMDARG_W<'_>

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>

pub fn ce_atacmd(&mut self) -> CE_ATACMD_W<'_>

Bit 14 - CE-ATA command

pub fn n_ien(&mut self) -> NIEN_W<'_>

Bit 13 - not Interrupt Enable

pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W<'_>

Bit 12 - Enable CMD completion

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>

Bit 11 - SD I/O suspend command

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>

Bit 10 - Command path state machine (CPSM) Enable bit

pub fn waitpend(&mut self) -> WAITPEND_W<'_>

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)

pub fn waitint(&mut self) -> WAITINT_W<'_>

Bit 8 - CPSM waits for interrupt request

pub fn waitresp(&mut self) -> WAITRESP_W<'_>

Bits 6:7 - Wait for response bits

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>

Bits 0:5 - Command index

impl W<u32, Reg<u32, _DTIMER>>

pub fn datatime(&mut self) -> DATATIME_W<'_>

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>

pub fn datalength(&mut self) -> DATALENGTH_W<'_>

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SD I/O enable functions

pub fn rwmod(&mut self) -> RWMOD_W<'_>

Bit 10 - Read wait mode

pub fn rwstop(&mut self) -> RWSTOP_W<'_>

Bit 9 - Read wait stop

pub fn rwstart(&mut self) -> RWSTART_W<'_>

Bit 8 - Read wait start

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>

Bits 4:7 - Data block size

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 3 - DMA enable bit

pub fn dtmode(&mut self) -> DTMODE_W<'_>

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer

pub fn dtdir(&mut self) -> DTDIR_W<'_>

Bit 1 - Data transfer direction selection

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTEN

impl W<u32, Reg<u32, _ICR>>

pub fn ceataendc(&mut self) -> CEATAENDC_W<'_>

Bit 23 - CEATAEND flag clear bit

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>

Bit 22 - SDIOIT flag clear bit

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>

Bit 10 - DBCKEND flag clear bit

pub fn stbiterrc(&mut self) -> STBITERRC_W<'_>

Bit 9 - STBITERR flag clear bit

pub fn dataendc(&mut self) -> DATAENDC_W<'_>

Bit 8 - DATAEND flag clear bit

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>

Bit 7 - CMDSENT flag clear bit

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>

Bit 6 - CMDREND flag clear bit

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>

Bit 5 - RXOVERR flag clear bit

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>

Bit 4 - TXUNDERR flag clear bit

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>

Bit 3 - DTIMEOUT flag clear bit

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>

Bit 2 - CTIMEOUT flag clear bit

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>

Bit 1 - DCRCFAIL flag clear bit

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>

Bit 0 - CCRCFAIL flag clear bit

impl W<u32, Reg<u32, _MASK>>

pub fn ceataendie(&mut self) -> CEATAENDIE_W<'_>

Bit 23 - CE-ATA command completion signal received interrupt enable

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>

Bit 22 - SDIO mode interrupt received interrupt enable

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>

Bit 21 - Data available in Rx FIFO interrupt enable

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>

Bit 20 - Data available in Tx FIFO interrupt enable

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>

Bit 19 - Rx FIFO empty interrupt enable

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>

Bit 18 - Tx FIFO empty interrupt enable

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>

Bit 17 - Rx FIFO full interrupt enable

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>

Bit 16 - Tx FIFO full interrupt enable

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>

Bit 15 - Rx FIFO half full interrupt enable

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>

Bit 14 - Tx FIFO half empty interrupt enable

pub fn rxactie(&mut self) -> RXACTIE_W<'_>

Bit 13 - Data receive acting interrupt enable

pub fn txactie(&mut self) -> TXACTIE_W<'_>

Bit 12 - Data transmit acting interrupt enable

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>

Bit 11 - Command acting interrupt enable

pub fn dbckendie(&mut self) -> DBCKENDIE_W<'_>

Bit 10 - Data block end interrupt enable

pub fn stbiterrie(&mut self) -> STBITERRIE_W<'_>

Bit 9 - Start bit error interrupt enable

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>

Bit 8 - Data end interrupt enable

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>

Bit 7 - Command sent interrupt enable

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>

Bit 6 - Command response received interrupt enable

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>

Bit 5 - Rx FIFO overrun error interrupt enable

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>

Bit 4 - Tx FIFO underrun error interrupt enable

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>

Bit 3 - Data timeout interrupt enable

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>

Bit 2 - Command timeout interrupt enable

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>

Bit 1 - Data CRC fail interrupt enable

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>

Bit 0 - Command CRC fail interrupt enable

impl W<u32, Reg<u32, _FIFO>>

pub fn fifodata(&mut self) -> FIFODATA_W<'_>

Bits 0:31 - Receive and transmit FIFO data

impl W<u32, Reg<u32, _IMR1>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Interrupt Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Interrupt Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Interrupt Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Interrupt Mask on line 22

pub fn mr23(&mut self) -> MR23_W<'_>

Bit 23 - Interrupt Mask on line 23

pub fn mr24(&mut self) -> MR24_W<'_>

Bit 24 - Interrupt Mask on line 24

pub fn mr25(&mut self) -> MR25_W<'_>

Bit 25 - Interrupt Mask on line 25

pub fn mr26(&mut self) -> MR26_W<'_>

Bit 26 - Interrupt Mask on line 26

pub fn mr27(&mut self) -> MR27_W<'_>

Bit 27 - Interrupt Mask on line 27

pub fn mr28(&mut self) -> MR28_W<'_>

Bit 28 - Interrupt Mask on line 28

pub fn mr29(&mut self) -> MR29_W<'_>

Bit 29 - Interrupt Mask on line 29

pub fn mr30(&mut self) -> MR30_W<'_>

Bit 30 - Interrupt Mask on line 30

pub fn mr31(&mut self) -> MR31_W<'_>

Bit 31 - Interrupt Mask on line 31

impl W<u32, Reg<u32, _EMR1>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Event Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Event Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Event Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Event Mask on line 22

pub fn mr23(&mut self) -> MR23_W<'_>

Bit 23 - Event Mask on line 23

pub fn mr24(&mut self) -> MR24_W<'_>

Bit 24 - Event Mask on line 24

pub fn mr25(&mut self) -> MR25_W<'_>

Bit 25 - Event Mask on line 25

pub fn mr26(&mut self) -> MR26_W<'_>

Bit 26 - Event Mask on line 26

pub fn mr27(&mut self) -> MR27_W<'_>

Bit 27 - Event Mask on line 27

pub fn mr28(&mut self) -> MR28_W<'_>

Bit 28 - Event Mask on line 28

pub fn mr29(&mut self) -> MR29_W<'_>

Bit 29 - Event Mask on line 29

pub fn mr30(&mut self) -> MR30_W<'_>

Bit 30 - Event Mask on line 30

pub fn mr31(&mut self) -> MR31_W<'_>

Bit 31 - Event Mask on line 31

impl W<u32, Reg<u32, _RTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Rising trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Rising trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Rising trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Rising trigger event configuration of line 22

impl W<u32, Reg<u32, _FTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Falling trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Falling trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Falling trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Falling trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Falling trigger event configuration of line 22

impl W<u32, Reg<u32, _SWIER1>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

pub fn swier19(&mut self) -> SWIER19_W<'_>

Bit 19 - Software Interrupt on line 19

pub fn swier20(&mut self) -> SWIER20_W<'_>

Bit 20 - Software Interrupt on line 20

pub fn swier21(&mut self) -> SWIER21_W<'_>

Bit 21 - Software Interrupt on line 21

pub fn swier22(&mut self) -> SWIER22_W<'_>

Bit 22 - Software Interrupt on line 22

impl W<u32, Reg<u32, _PR1>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

pub fn pr19(&mut self) -> PR19_W<'_>

Bit 19 - Pending bit 19

pub fn pr20(&mut self) -> PR20_W<'_>

Bit 20 - Pending bit 20

pub fn pr21(&mut self) -> PR21_W<'_>

Bit 21 - Pending bit 21

pub fn pr22(&mut self) -> PR22_W<'_>

Bit 22 - Pending bit 22

impl W<u32, Reg<u32, _IMR2>>

pub fn mr32(&mut self) -> MR32_W<'_>

Bit 0 - Interrupt Mask on external/internal line 32

pub fn mr33(&mut self) -> MR33_W<'_>

Bit 1 - Interrupt Mask on external/internal line 33

pub fn mr34(&mut self) -> MR34_W<'_>

Bit 2 - Interrupt Mask on external/internal line 34

pub fn mr35(&mut self) -> MR35_W<'_>

Bit 3 - Interrupt Mask on external/internal line 35

pub fn mr36(&mut self) -> MR36_W<'_>

Bit 4 - Interrupt Mask on external/internal line 36

pub fn mr37(&mut self) -> MR37_W<'_>

Bit 5 - Interrupt Mask on external/internal line 37

pub fn mr38(&mut self) -> MR38_W<'_>

Bit 6 - Interrupt Mask on external/internal line 38

pub fn mr39(&mut self) -> MR39_W<'_>

Bit 7 - Interrupt Mask on external/internal line 39

impl W<u32, Reg<u32, _EMR2>>

pub fn mr32(&mut self) -> MR32_W<'_>

Bit 0 - Event mask on external/internal line 32

pub fn mr33(&mut self) -> MR33_W<'_>

Bit 1 - Event mask on external/internal line 33

pub fn mr34(&mut self) -> MR34_W<'_>

Bit 2 - Event mask on external/internal line 34

pub fn mr35(&mut self) -> MR35_W<'_>

Bit 3 - Event mask on external/internal line 35

pub fn mr36(&mut self) -> MR36_W<'_>

Bit 4 - Event mask on external/internal line 36

pub fn mr37(&mut self) -> MR37_W<'_>

Bit 5 - Event mask on external/internal line 37

pub fn mr38(&mut self) -> MR38_W<'_>

Bit 6 - Event mask on external/internal line 38

pub fn mr39(&mut self) -> MR39_W<'_>

Bit 7 - Event mask on external/internal line 39

impl W<u32, Reg<u32, _RTSR2>>

pub fn rt35(&mut self) -> RT35_W<'_>

Bit 3 - Rising trigger event configuration bit of line 35

pub fn rt36(&mut self) -> RT36_W<'_>

Bit 4 - Rising trigger event configuration bit of line 36

pub fn rt37(&mut self) -> RT37_W<'_>

Bit 5 - Rising trigger event configuration bit of line 37

pub fn rt38(&mut self) -> RT38_W<'_>

Bit 6 - Rising trigger event configuration bit of line 38

impl W<u32, Reg<u32, _FTSR2>>

pub fn ft35(&mut self) -> FT35_W<'_>

Bit 3 - Falling trigger event configuration bit of line 35

pub fn ft36(&mut self) -> FT36_W<'_>

Bit 4 - Falling trigger event configuration bit of line 36

pub fn ft37(&mut self) -> FT37_W<'_>

Bit 5 - Falling trigger event configuration bit of line 37

pub fn ft38(&mut self) -> FT38_W<'_>

Bit 6 - Falling trigger event configuration bit of line 38

impl W<u32, Reg<u32, _SWIER2>>

pub fn swi35(&mut self) -> SWI35_W<'_>

Bit 3 - Software interrupt on line 35

pub fn swi36(&mut self) -> SWI36_W<'_>

Bit 4 - Software interrupt on line 36

pub fn swi37(&mut self) -> SWI37_W<'_>

Bit 5 - Software interrupt on line 37

pub fn swi38(&mut self) -> SWI38_W<'_>

Bit 6 - Software interrupt on line 38

impl W<u32, Reg<u32, _PR2>>

pub fn pif35(&mut self) -> PIF35_W<'_>

Bit 3 - Pending interrupt flag on line 35

pub fn pif36(&mut self) -> PIF36_W<'_>

Bit 4 - Pending interrupt flag on line 36

pub fn pif37(&mut self) -> PIF37_W<'_>

Bit 5 - Pending interrupt flag on line 37

pub fn pif38(&mut self) -> PIF38_W<'_>

Bit 6 - Pending interrupt flag on line 38

impl W<u32, Reg<u32, _CSR>>

pub fn envr(&mut self) -> ENVR_W<'_>

Bit 0 - Voltage reference buffer enable

pub fn hiz(&mut self) -> HIZ_W<'_>

Bit 1 - High impedance mode

pub fn vrs(&mut self) -> VRS_W<'_>

Bit 2 - Voltage reference scale

impl W<u32, Reg<u32, _CCR>>

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 0:5 - Trimming code

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _FMR>>

pub fn finit(&mut self) -> FINIT_W<'_>

Bit 0 - Filter initialization mode

impl W<u32, Reg<u32, _FM1R>>

pub fn fbm0(&mut self) -> FBM0_W<'_>

Bit 0 - Filter mode

pub fn fbm1(&mut self) -> FBM1_W<'_>

Bit 1 - Filter mode

pub fn fbm2(&mut self) -> FBM2_W<'_>

Bit 2 - Filter mode

pub fn fbm3(&mut self) -> FBM3_W<'_>

Bit 3 - Filter mode

pub fn fbm4(&mut self) -> FBM4_W<'_>

Bit 4 - Filter mode

pub fn fbm5(&mut self) -> FBM5_W<'_>

Bit 5 - Filter mode

pub fn fbm6(&mut self) -> FBM6_W<'_>

Bit 6 - Filter mode

pub fn fbm7(&mut self) -> FBM7_W<'_>

Bit 7 - Filter mode

pub fn fbm8(&mut self) -> FBM8_W<'_>

Bit 8 - Filter mode

pub fn fbm9(&mut self) -> FBM9_W<'_>

Bit 9 - Filter mode

pub fn fbm10(&mut self) -> FBM10_W<'_>

Bit 10 - Filter mode

pub fn fbm11(&mut self) -> FBM11_W<'_>

Bit 11 - Filter mode

pub fn fbm12(&mut self) -> FBM12_W<'_>

Bit 12 - Filter mode

pub fn fbm13(&mut self) -> FBM13_W<'_>

Bit 13 - Filter mode

impl W<u32, Reg<u32, _FS1R>>

pub fn fsc0(&mut self) -> FSC0_W<'_>

Bit 0 - Filter scale configuration

pub fn fsc1(&mut self) -> FSC1_W<'_>

Bit 1 - Filter scale configuration

pub fn fsc2(&mut self) -> FSC2_W<'_>

Bit 2 - Filter scale configuration

pub fn fsc3(&mut self) -> FSC3_W<'_>

Bit 3 - Filter scale configuration

pub fn fsc4(&mut self) -> FSC4_W<'_>

Bit 4 - Filter scale configuration

pub fn fsc5(&mut self) -> FSC5_W<'_>

Bit 5 - Filter scale configuration

pub fn fsc6(&mut self) -> FSC6_W<'_>

Bit 6 - Filter scale configuration

pub fn fsc7(&mut self) -> FSC7_W<'_>

Bit 7 - Filter scale configuration

pub fn fsc8(&mut self) -> FSC8_W<'_>

Bit 8 - Filter scale configuration

pub fn fsc9(&mut self) -> FSC9_W<'_>

Bit 9 - Filter scale configuration

pub fn fsc10(&mut self) -> FSC10_W<'_>

Bit 10 - Filter scale configuration

pub fn fsc11(&mut self) -> FSC11_W<'_>

Bit 11 - Filter scale configuration

pub fn fsc12(&mut self) -> FSC12_W<'_>

Bit 12 - Filter scale configuration

pub fn fsc13(&mut self) -> FSC13_W<'_>

Bit 13 - Filter scale configuration

impl W<u32, Reg<u32, _FFA1R>>

pub fn ffa0(&mut self) -> FFA0_W<'_>

Bit 0 - Filter FIFO assignment for filter 0

pub fn ffa1(&mut self) -> FFA1_W<'_>

Bit 1 - Filter FIFO assignment for filter 1

pub fn ffa2(&mut self) -> FFA2_W<'_>

Bit 2 - Filter FIFO assignment for filter 2

pub fn ffa3(&mut self) -> FFA3_W<'_>

Bit 3 - Filter FIFO assignment for filter 3

pub fn ffa4(&mut self) -> FFA4_W<'_>

Bit 4 - Filter FIFO assignment for filter 4

pub fn ffa5(&mut self) -> FFA5_W<'_>

Bit 5 - Filter FIFO assignment for filter 5

pub fn ffa6(&mut self) -> FFA6_W<'_>

Bit 6 - Filter FIFO assignment for filter 6

pub fn ffa7(&mut self) -> FFA7_W<'_>

Bit 7 - Filter FIFO assignment for filter 7

pub fn ffa8(&mut self) -> FFA8_W<'_>

Bit 8 - Filter FIFO assignment for filter 8

pub fn ffa9(&mut self) -> FFA9_W<'_>

Bit 9 - Filter FIFO assignment for filter 9

pub fn ffa10(&mut self) -> FFA10_W<'_>

Bit 10 - Filter FIFO assignment for filter 10

pub fn ffa11(&mut self) -> FFA11_W<'_>

Bit 11 - Filter FIFO assignment for filter 11

pub fn ffa12(&mut self) -> FFA12_W<'_>

Bit 12 - Filter FIFO assignment for filter 12

pub fn ffa13(&mut self) -> FFA13_W<'_>

Bit 13 - Filter FIFO assignment for filter 13

impl W<u32, Reg<u32, _FA1R>>

pub fn fact0(&mut self) -> FACT0_W<'_>

Bit 0 - Filter active

pub fn fact1(&mut self) -> FACT1_W<'_>

Bit 1 - Filter active

pub fn fact2(&mut self) -> FACT2_W<'_>

Bit 2 - Filter active

pub fn fact3(&mut self) -> FACT3_W<'_>

Bit 3 - Filter active

pub fn fact4(&mut self) -> FACT4_W<'_>

Bit 4 - Filter active

pub fn fact5(&mut self) -> FACT5_W<'_>

Bit 5 - Filter active

pub fn fact6(&mut self) -> FACT6_W<'_>

Bit 6 - Filter active

pub fn fact7(&mut self) -> FACT7_W<'_>

Bit 7 - Filter active

pub fn fact8(&mut self) -> FACT8_W<'_>

Bit 8 - Filter active

pub fn fact9(&mut self) -> FACT9_W<'_>

Bit 9 - Filter active

pub fn fact10(&mut self) -> FACT10_W<'_>

Bit 10 - Filter active

pub fn fact11(&mut self) -> FACT11_W<'_>

Bit 11 - Filter active

pub fn fact12(&mut self) -> FACT12_W<'_>

Bit 12 - Filter active

pub fn fact13(&mut self) -> FACT13_W<'_>

Bit 13 - Filter active

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - Wakeup clock selection

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - Time-stamp event active edge

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - Bypass the shadow registers

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - Hour format

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - Alarm A enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - Alarm B enable

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - Wakeup timer enable

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - Time stamp enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - Alarm A interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - Alarm B interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - Wakeup timer interrupt enable

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - Time-stamp interrupt enable

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - Add 1 hour (summer time change)

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - Subtract 1 hour (winter time change)

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - Backup

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - Calibration output selection

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - Output polarity

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - Output selection

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - Calibration output enable

pub fn itse(&mut self) -> ITSE_W<'_>

Bit 24 - timestamp on internal event enable

impl W<u32, Reg<u32, _ISR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

pub fn alraf(&mut self) -> ALRAF_W<'_>

Bit 8 - Alarm A flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>

Bit 9 - Alarm B flag

pub fn wutf(&mut self) -> WUTF_W<'_>

Bit 10 - Wakeup timer flag

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 11 - Time-stamp flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>

Bit 12 - Time-stamp overflow flag

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>

Bit 13 - Tamper detection flag

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>

Bit 14 - RTC_TAMP2 detection flag

pub fn tamp3f(&mut self) -> TAMP3F_W<'_>

Bit 15 - RTC_TAMP3 detection flag

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAMPCR>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - Tamper 1 detection enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 1 - Active level for tamper 1

pub fn tampie(&mut self) -> TAMPIE_W<'_>

Bit 2 - Tamper interrupt enable

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 3 - Tamper 2 detection enable

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 4 - Active level for tamper 2

pub fn tamp3e(&mut self) -> TAMP3E_W<'_>

Bit 5 - Tamper 3 detection enable

pub fn tamp3trg(&mut self) -> TAMP3TRG_W<'_>

Bit 6 - Active level for tamper 3

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 7 - Activate timestamp on tamper detection event

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 8:10 - Tamper sampling frequency

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 11:12 - Tamper filter count

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 13:14 - Tamper precharge duration

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 15 - TAMPER pull-up disable

pub fn tamp1ie(&mut self) -> TAMP1IE_W<'_>

Bit 16 - Tamper 1 interrupt enable

pub fn tamp1noerase(&mut self) -> TAMP1NOERASE_W<'_>

Bit 17 - Tamper 1 no erase

pub fn tamp1mf(&mut self) -> TAMP1MF_W<'_>

Bit 18 - Tamper 1 mask flag

pub fn tamp2ie(&mut self) -> TAMP2IE_W<'_>

Bit 19 - Tamper 2 interrupt enable

pub fn tamp2noerase(&mut self) -> TAMP2NOERASE_W<'_>

Bit 20 - Tamper 2 no erase

pub fn tamp2mf(&mut self) -> TAMP2MF_W<'_>

Bit 21 - Tamper 2 mask flag

pub fn tamp3ie(&mut self) -> TAMP3IE_W<'_>

Bit 22 - Tamper 3 interrupt enable

pub fn tamp3noerase(&mut self) -> TAMP3NOERASE_W<'_>

Bit 23 - Tamper 3 no erase

pub fn tamp3mf(&mut self) -> TAMP3MF_W<'_>

Bit 24 - Tamper 3 mask flag

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _OR>>

pub fn rtc_alarm_type(&mut self) -> RTC_ALARM_TYPE_W<'_>

Bit 0 - RTC_ALARM on PC13 output type

pub fn rtc_out_rmp(&mut self) -> RTC_OUT_RMP_W<'_>

Bit 1 - RTC_OUT remap

impl W<u32, Reg<u32, _BKPR>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CR>>

pub fn rxdma(&mut self) -> RXDMA_W<'_>

Bit 0 - Reception DMA enable

pub fn txdma(&mut self) -> TXDMA_W<'_>

Bit 1 - Transmission DMA enable

pub fn rxmode(&mut self) -> RXMODE_W<'_>

Bit 2 - Reception buffering mode

pub fn txmode(&mut self) -> TXMODE_W<'_>

Bit 3 - Transmission buffering mode

pub fn lpbk(&mut self) -> LPBK_W<'_>

Bit 4 - Loopback mode enable

pub fn swpme(&mut self) -> SWPME_W<'_>

Bit 5 - Single wire protocol master interface enable

pub fn deact(&mut self) -> DEACT_W<'_>

Bit 10 - Single wire protocol master interface deactivate

impl W<u32, Reg<u32, _BRR>>

pub fn br(&mut self) -> BR_W<'_>

Bits 0:5 - Bitrate prescaler

impl W<u32, Reg<u32, _ICR>>

pub fn crxbff(&mut self) -> CRXBFF_W<'_>

Bit 0 - Clear receive buffer full flag

pub fn ctxbef(&mut self) -> CTXBEF_W<'_>

Bit 1 - Clear transmit buffer empty flag

pub fn crxberf(&mut self) -> CRXBERF_W<'_>

Bit 2 - Clear receive CRC error flag

pub fn crxovrf(&mut self) -> CRXOVRF_W<'_>

Bit 3 - Clear receive overrun error flag

pub fn ctxunrf(&mut self) -> CTXUNRF_W<'_>

Bit 4 - Clear transmit underrun error flag

pub fn ctcf(&mut self) -> CTCF_W<'_>

Bit 7 - Clear transfer complete flag

pub fn csrf(&mut self) -> CSRF_W<'_>

Bit 8 - Clear slave resume flag

impl W<u32, Reg<u32, _IER>>

pub fn rxbfie(&mut self) -> RXBFIE_W<'_>

Bit 0 - Receive buffer full interrupt enable

pub fn txbeie(&mut self) -> TXBEIE_W<'_>

Bit 1 - Transmit buffer empty interrupt enable

pub fn rxberie(&mut self) -> RXBERIE_W<'_>

Bit 2 - Receive CRC error interrupt enable

pub fn rxovrie(&mut self) -> RXOVRIE_W<'_>

Bit 3 - Receive overrun error interrupt enable

pub fn txunrie(&mut self) -> TXUNRIE_W<'_>

Bit 4 - Transmit underrun error interrupt enable

pub fn rie(&mut self) -> RIE_W<'_>

Bit 5 - Receive interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Transmit interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 7 - Transmit complete interrupt enable

pub fn srie(&mut self) -> SRIE_W<'_>

Bit 8 - Slave resume interrupt enable

impl W<u32, Reg<u32, _TDR>>

pub fn td(&mut self) -> TD_W<'_>

Bits 0:31 - Transmit data

impl W<u32, Reg<u32, _OPAMP1_CSR>>

pub fn opaen(&mut self) -> OPAEN_W<'_>

Bit 0 - Operational amplifier Enable

pub fn opalpm(&mut self) -> OPALPM_W<'_>

Bit 1 - Operational amplifier Low Power Mode

pub fn opamode(&mut self) -> OPAMODE_W<'_>

Bits 2:3 - Operational amplifier PGA mode

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 4:5 - Operational amplifier Programmable amplifier gain value

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 8:9 - Inverting input selection

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bit 10 - Non inverted input selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 12 - Calibration mode enabled

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bit 13 - Calibration selection

pub fn usertrim(&mut self) -> USERTRIM_W<'_>

Bit 14 - allows to switch from AOP offset trimmed values to AOP offset

pub fn calout(&mut self) -> CALOUT_W<'_>

Bit 15 - Operational amplifier calibration output

pub fn opa_range(&mut self) -> OPA_RANGE_W<'_>

Bit 31 - Operational amplifier power supply range for stability

impl W<u32, Reg<u32, _OPAMP1_OTR>>

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 0:4 - Trim for NMOS differential pairs

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 8:12 - Trim for PMOS differential pairs

impl W<u32, Reg<u32, _OPAMP1_LPOTR>>

pub fn trimlpoffsetn(&mut self) -> TRIMLPOFFSETN_W<'_>

Bits 0:4 - Trim for NMOS differential pairs

pub fn trimlpoffsetp(&mut self) -> TRIMLPOFFSETP_W<'_>

Bits 8:12 - Trim for PMOS differential pairs

impl W<u32, Reg<u32, _OPAMP2_CSR>>

pub fn opaen(&mut self) -> OPAEN_W<'_>

Bit 0 - Operational amplifier Enable

pub fn opalpm(&mut self) -> OPALPM_W<'_>

Bit 1 - Operational amplifier Low Power Mode

pub fn opamode(&mut self) -> OPAMODE_W<'_>

Bits 2:3 - Operational amplifier PGA mode

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 4:5 - Operational amplifier Programmable amplifier gain value

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 8:9 - Inverting input selection

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bit 10 - Non inverted input selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 12 - Calibration mode enabled

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bit 13 - Calibration selection

pub fn usertrim(&mut self) -> USERTRIM_W<'_>

Bit 14 - allows to switch from AOP offset trimmed values to AOP offset

pub fn calout(&mut self) -> CALOUT_W<'_>

Bit 15 - Operational amplifier calibration output

impl W<u32, Reg<u32, _OPAMP2_OTR>>

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 0:4 - Trim for NMOS differential pairs

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 8:12 - Trim for PMOS differential pairs

impl W<u32, Reg<u32, _OPAMP2_LPOTR>>

pub fn trimlpoffsetn(&mut self) -> TRIMLPOFFSETN_W<'_>

Bits 0:4 - Trim for NMOS differential pairs

pub fn trimlpoffsetp(&mut self) -> TRIMLPOFFSETP_W<'_>

Bits 8:12 - Trim for PMOS differential pairs

impl W<u32, Reg<u32, _CR>>

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 8:13 - HSI48 oscillator smooth trimming

pub fn swsync(&mut self) -> SWSYNC_W<'_>

Bit 7 - Generate software SYNC event

pub fn autotrimen(&mut self) -> AUTOTRIMEN_W<'_>

Bit 6 - Automatic trimming enable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 5 - Frequency error counter enable

pub fn esyncie(&mut self) -> ESYNCIE_W<'_>

Bit 3 - Expected SYNC interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 2 - Synchronization or trimming error interrupt enable

pub fn syncwarnie(&mut self) -> SYNCWARNIE_W<'_>

Bit 1 - SYNC warning interrupt enable

pub fn syncokie(&mut self) -> SYNCOKIE_W<'_>

Bit 0 - SYNC event OK interrupt enable

impl W<u32, Reg<u32, _CFGR>>

pub fn syncpol(&mut self) -> SYNCPOL_W<'_>

Bit 31 - SYNC polarity selection

pub fn syncsrc(&mut self) -> SYNCSRC_W<'_>

Bits 28:29 - SYNC signal source selection

pub fn syncdiv(&mut self) -> SYNCDIV_W<'_>

Bits 24:26 - SYNC divider

pub fn felim(&mut self) -> FELIM_W<'_>

Bits 16:23 - Frequency error limit

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:15 - Counter reload value

impl W<u32, Reg<u32, _ICR>>

pub fn esyncc(&mut self) -> ESYNCC_W<'_>

Bit 3 - Expected SYNC clear flag

pub fn errc(&mut self) -> ERRC_W<'_>

Bit 2 - Error clear flag

pub fn syncwarnc(&mut self) -> SYNCWARNC_W<'_>

Bit 1 - SYNC warning clear flag

pub fn syncokc(&mut self) -> SYNCOKC_W<'_>

Bit 0 - SYNC event OK clear flag

impl W<u32, Reg<u32, _EP0R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP1R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP2R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP3R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP4R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP5R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP6R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP7R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _CNTR>>

pub fn fres(&mut self) -> FRES_W<'_>

Bit 0 - Force USB Reset

pub fn pdwn(&mut self) -> PDWN_W<'_>

Bit 1 - Power down

pub fn lpmode(&mut self) -> LPMODE_W<'_>

Bit 2 - Low-power mode

pub fn fsusp(&mut self) -> FSUSP_W<'_>

Bit 3 - Force suspend

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 4 - Resume request

pub fn l1resume(&mut self) -> L1RESUME_W<'_>

Bit 5 - LPM L1 Resume request

pub fn l1reqm(&mut self) -> L1REQM_W<'_>

Bit 7 - LPM L1 state request interrupt mask

pub fn esofm(&mut self) -> ESOFM_W<'_>

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 9 - Start of frame interrupt mask

pub fn resetm(&mut self) -> RESETM_W<'_>

Bit 10 - USB reset interrupt mask

pub fn suspm(&mut self) -> SUSPM_W<'_>

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&mut self) -> WKUPM_W<'_>

Bit 12 - Wakeup interrupt mask

pub fn errm(&mut self) -> ERRM_W<'_>

Bit 13 - Error interrupt mask

pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&mut self) -> CTRM_W<'_>

Bit 15 - Correct transfer interrupt mask

impl W<u32, Reg<u32, _ISTR>>

pub fn l1req(&mut self) -> L1REQ_W<'_>

Bit 7 - LPM L1 state request

pub fn esof(&mut self) -> ESOF_W<'_>

Bit 8 - Expected start frame

pub fn sof(&mut self) -> SOF_W<'_>

Bit 9 - start of frame

pub fn reset(&mut self) -> RESET_W<'_>

Bit 10 - reset request

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 11 - Suspend mode request

pub fn wkup(&mut self) -> WKUP_W<'_>

Bit 12 - Wakeup

pub fn err(&mut self) -> ERR_W<'_>

Bit 13 - Error

pub fn pmaovr(&mut self) -> PMAOVR_W<'_>

Bit 14 - Packet memory area over / underrun

impl W<u32, Reg<u32, _DADDR>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:6 - Device address

pub fn ef(&mut self) -> EF_W<'_>

Bit 7 - Enable function

impl W<u32, Reg<u32, _BTABLE>>

pub fn btable(&mut self) -> BTABLE_W<'_>

Bits 3:15 - Buffer table

impl W<u32, Reg<u32, _LPMCSR>>

pub fn lpmen(&mut self) -> LPMEN_W<'_>

Bit 0 - LPM support enable

pub fn lpmack(&mut self) -> LPMACK_W<'_>

Bit 1 - LPM Token acknowledge enable

impl W<u32, Reg<u32, _BCDR>>

pub fn bcden(&mut self) -> BCDEN_W<'_>

Bit 0 - Battery charging detector

pub fn dcden(&mut self) -> DCDEN_W<'_>

Bit 1 - Data contact detection

pub fn pden(&mut self) -> PDEN_W<'_>

Bit 2 - Primary detection

pub fn sden(&mut self) -> SDEN_W<'_>

Bit 3 - Secondary detection

pub fn dppu(&mut self) -> DPPU_W<'_>

Bit 15 - DP pull-up control

impl W<u32, Reg<u32, _CFGR1>>

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>

Bit 31 - DFSDMEN

pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<'_>

Bit 30 - CKOUTSRC

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>

Bits 16:23 - CKOUTDIV

pub fn datpack(&mut self) -> DATPACK_W<'_>

Bits 14:15 - DATPACK

pub fn datmpx(&mut self) -> DATMPX_W<'_>

Bits 12:13 - DATMPX

pub fn chinsel(&mut self) -> CHINSEL_W<'_>

Bit 8 - CHINSEL

pub fn chen(&mut self) -> CHEN_W<'_>

Bit 7 - CHEN

pub fn ckaben(&mut self) -> CKABEN_W<'_>

Bit 6 - CKABEN

pub fn scden(&mut self) -> SCDEN_W<'_>

Bit 5 - SCDEN

pub fn spicksel(&mut self) -> SPICKSEL_W<'_>

Bits 2:3 - SPICKSEL

pub fn sitp(&mut self) -> SITP_W<'_>

Bits 0:1 - SITP

impl W<u32, Reg<u32, _CFGR2>>

pub fn offset(&mut self) -> OFFSET_W<'_>

Bits 8:31 - OFFSET

pub fn dtrbs(&mut self) -> DTRBS_W<'_>

Bits 3:7 - DTRBS

impl W<u32, Reg<u32, _AWSCDR>>

pub fn awford(&mut self) -> AWFORD_W<'_>

Bits 22:23 - AWFORD

pub fn awfosr(&mut self) -> AWFOSR_W<'_>

Bits 16:20 - AWFOSR

pub fn bkscd(&mut self) -> BKSCD_W<'_>

Bits 12:15 - BKSCD

pub fn scdt(&mut self) -> SCDT_W<'_>

Bits 0:7 - SCDT

impl W<u32, Reg<u32, _WDATR>>

pub fn wdata(&mut self) -> WDATA_W<'_>

Bits 0:15 - WDATA

impl W<u32, Reg<u32, _DATINR>>

pub fn indat1(&mut self) -> INDAT1_W<'_>

Bits 16:31 - INDAT1

pub fn indat0(&mut self) -> INDAT0_W<'_>

Bits 0:15 - INDAT0

impl W<u32, Reg<u32, _CR2>>

pub fn awfsel(&mut self) -> AWFSEL_W<'_>

Bit 30 - Analog watchdog fast mode select

pub fn fast(&mut self) -> FAST_W<'_>

Bit 29 - Fast conversion mode selection for regular conversions

pub fn rch(&mut self) -> RCH_W<'_>

Bits 24:26 - Regular channel selection

pub fn rdmaen(&mut self) -> RDMAEN_W<'_>

Bit 21 - DMA channel enabled to read data for the regular conversion

pub fn rsync(&mut self) -> RSYNC_W<'_>

Bit 19 - Launch regular conversion synchronously with DFSDM0

pub fn rcont(&mut self) -> RCONT_W<'_>

Bit 18 - Continuous mode selection for regular conversions

pub fn rswstart(&mut self) -> RSWSTART_W<'_>

Bit 17 - Software start of a conversion on the regular channel

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 8:10 - Trigger signal selection for launching injected conversions

pub fn jdmaen(&mut self) -> JDMAEN_W<'_>

Bit 5 - DMA channel enabled to read data for the injected channel group

pub fn jscan(&mut self) -> JSCAN_W<'_>

Bit 4 - Scanning conversion mode for injected conversions

pub fn jsync(&mut self) -> JSYNC_W<'_>

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 1 - Start a conversion of the injected group of channels

pub fn dfen(&mut self) -> DFEN_W<'_>

Bit 0 - DFSDM enable

impl W<u32, Reg<u32, _ICR>>

pub fn clrscdf(&mut self) -> CLRSCDF_W<'_>

Bits 24:31 - Clear the short-circuit detector flag

pub fn clrckabf(&mut self) -> CLRCKABF_W<'_>

Bits 16:23 - Clear the clock absence flag

pub fn clrrovrf(&mut self) -> CLRROVRF_W<'_>

Bit 3 - Clear the regular conversion overrun flag

pub fn clrjovrf(&mut self) -> CLRJOVRF_W<'_>

Bit 2 - Clear the injected conversion overrun flag

impl W<u32, Reg<u32, _JCHGR>>

pub fn jchg(&mut self) -> JCHG_W<'_>

Bits 0:7 - Injected channel group selection

impl W<u32, Reg<u32, _FCR>>

pub fn ford(&mut self) -> FORD_W<'_>

Bits 29:31 - Sinc filter order

pub fn fosr(&mut self) -> FOSR_W<'_>

Bits 16:25 - Sinc filter oversampling ratio (decimation rate)

pub fn iosr(&mut self) -> IOSR_W<'_>

Bits 0:7 - Integrator oversampling ratio (averaging length)

impl W<u32, Reg<u32, _AWHTR>>

pub fn awht(&mut self) -> AWHT_W<'_>

Bits 8:31 - Analog watchdog high threshold

pub fn bkawh(&mut self) -> BKAWH_W<'_>

Bits 0:3 - Break signal assignment to analog watchdog high threshold event

impl W<u32, Reg<u32, _AWLTR>>

pub fn awlt(&mut self) -> AWLT_W<'_>

Bits 8:31 - Analog watchdog low threshold

pub fn bkawl(&mut self) -> BKAWL_W<'_>

Bits 0:3 - Break signal assignment to analog watchdog low threshold event

impl W<u32, Reg<u32, _AWCFR>>

pub fn clrawhtf(&mut self) -> CLRAWHTF_W<'_>

Bits 8:15 - Clear the analog watchdog high threshold flag

pub fn clrawltf(&mut self) -> CLRAWLTF_W<'_>

Bits 0:7 - Clear the analog watchdog low threshold flag

impl W<u32, Reg<u32, _DFSDM0_CR2>>

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 16:23 - Analog watchdog channel selection

pub fn exch(&mut self) -> EXCH_W<'_>

Bits 8:15 - Extremes detector channel selection

pub fn ckabie(&mut self) -> CKABIE_W<'_>

Bit 6 - Clock absence interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>

Bit 5 - Short-circuit detector interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 4 - Analog watchdog interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>

Bit 3 - Regular data overrun interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>

Bit 2 - Injected data overrun interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>

Bit 1 - Regular end of conversion interrupt enable

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 0 - Injected end of conversion interrupt enable

impl W<u32, Reg<u32, _DFSDM1_CR2>>

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 16:23 - Analog watchdog channel selection

pub fn exch(&mut self) -> EXCH_W<'_>

Bits 8:15 - Extremes detector channel selection

pub fn ckabie(&mut self) -> CKABIE_W<'_>

Bit 6 - Clock absence interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>

Bit 5 - Short-circuit detector interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 4 - Analog watchdog interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>

Bit 3 - Regular data overrun interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>

Bit 2 - Injected data overrun interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>

Bit 1 - Regular end of conversion interrupt enable

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 0 - Injected end of conversion interrupt enable

impl W<u32, Reg<u32, _DFSDM2_CR2>>

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 16:23 - Analog watchdog channel selection

pub fn exch(&mut self) -> EXCH_W<'_>

Bits 8:15 - Extremes detector channel selection

pub fn ckabie(&mut self) -> CKABIE_W<'_>

Bit 6 - Clock absence interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>

Bit 5 - Short-circuit detector interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 4 - Analog watchdog interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>

Bit 3 - Regular data overrun interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>

Bit 2 - Injected data overrun interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>

Bit 1 - Regular end of conversion interrupt enable

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 0 - Injected end of conversion interrupt enable

impl W<u32, Reg<u32, _DFSDM3_CR2>>

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 16:23 - Analog watchdog channel selection

pub fn exch(&mut self) -> EXCH_W<'_>

Bits 8:15 - Extremes detector channel selection

pub fn ckabie(&mut self) -> CKABIE_W<'_>

Bit 6 - Clock absence interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>

Bit 5 - Short-circuit detector interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 4 - Analog watchdog interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>

Bit 3 - Regular data overrun interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>

Bit 2 - Injected data overrun interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>

Bit 1 - Regular end of conversion interrupt enable

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 0 - Injected end of conversion interrupt enable

impl W<u32, Reg<u32, _CR>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 24:31 - Clock prescaler

pub fn pmm(&mut self) -> PMM_W<'_>

Bit 23 - Polling match mode

pub fn apms(&mut self) -> APMS_W<'_>

Bit 22 - Automatic poll mode stop

pub fn toie(&mut self) -> TOIE_W<'_>

Bit 20 - TimeOut interrupt enable

pub fn smie(&mut self) -> SMIE_W<'_>

Bit 19 - Status match interrupt enable

pub fn ftie(&mut self) -> FTIE_W<'_>

Bit 18 - FIFO threshold interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 17 - Transfer complete interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 16 - Transfer error interrupt enable

pub fn fthres(&mut self) -> FTHRES_W<'_>

Bits 8:12 - IFO threshold level

pub fn fsel(&mut self) -> FSEL_W<'_>

Bit 7 - FLASH memory selection

pub fn dfm(&mut self) -> DFM_W<'_>

Bit 6 - Dual-flash mode

pub fn sshift(&mut self) -> SSHIFT_W<'_>

Bit 4 - Sample shift

pub fn tcen(&mut self) -> TCEN_W<'_>

Bit 3 - Timeout counter enable

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 2 - DMA enable

pub fn abort(&mut self) -> ABORT_W<'_>

Bit 1 - Abort request

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

impl W<u32, Reg<u32, _DCR>>

pub fn fsize(&mut self) -> FSIZE_W<'_>

Bits 16:20 - FLASH memory size

pub fn csht(&mut self) -> CSHT_W<'_>

Bits 8:10 - Chip select high time

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bit 0 - Mode 0 / mode 3

impl W<u32, Reg<u32, _FCR>>

pub fn ctof(&mut self) -> CTOF_W<'_>

Bit 4 - Clear timeout flag

pub fn csmf(&mut self) -> CSMF_W<'_>

Bit 3 - Clear status match flag

pub fn ctcf(&mut self) -> CTCF_W<'_>

Bit 1 - Clear transfer complete flag

pub fn ctef(&mut self) -> CTEF_W<'_>

Bit 0 - Clear transfer error flag

impl W<u32, Reg<u32, _DLR>>

pub fn dl(&mut self) -> DL_W<'_>

Bits 0:31 - Data length

impl W<u32, Reg<u32, _CCR>>

pub fn ddrm(&mut self) -> DDRM_W<'_>

Bit 31 - Double data rate mode

pub fn dhhc(&mut self) -> DHHC_W<'_>

Bit 30 - DDR hold half cycle

pub fn sioo(&mut self) -> SIOO_W<'_>

Bit 28 - Send instruction only once mode

pub fn fmode(&mut self) -> FMODE_W<'_>

Bits 26:27 - Functional mode

pub fn dmode(&mut self) -> DMODE_W<'_>

Bits 24:25 - Data mode

pub fn dcyc(&mut self) -> DCYC_W<'_>

Bits 18:22 - Number of dummy cycles

pub fn absize(&mut self) -> ABSIZE_W<'_>

Bits 16:17 - Alternate bytes size

pub fn abmode(&mut self) -> ABMODE_W<'_>

Bits 14:15 - Alternate bytes mode

pub fn adsize(&mut self) -> ADSIZE_W<'_>

Bits 12:13 - Address size

pub fn admode(&mut self) -> ADMODE_W<'_>

Bits 10:11 - Address mode

pub fn imode(&mut self) -> IMODE_W<'_>

Bits 8:9 - Instruction mode

pub fn instruction(&mut self) -> INSTRUCTION_W<'_>

Bits 0:7 - Instruction

impl W<u32, Reg<u32, _AR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:31 - Address

impl W<u32, Reg<u32, _ABR>>

pub fn alternate(&mut self) -> ALTERNATE_W<'_>

Bits 0:31 - ALTERNATE

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _PSMKR>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 0:31 - Status mask

impl W<u32, Reg<u32, _PSMAR>>

pub fn match_(&mut self) -> MATCH_W<'_>

Bits 0:31 - Status match

impl W<u32, Reg<u32, _PIR>>

pub fn interval(&mut self) -> INTERVAL_W<'_>

Bits 0:15 - Polling interval

impl W<u32, Reg<u32, _LPTR>>

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bits 0:15 - Timeout period

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - Debug Sleep mode

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby mode

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - Trace pin assignment control

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - Trace pin assignment control

impl W<u32, Reg<u32, _APB1FZR1>>

pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W<'_>

Bit 0 - TIM2 counter stopped when core is halted

pub fn dbg_tim6_stop(&mut self) -> DBG_TIM6_STOP_W<'_>

Bit 4 - TIM6 counter stopped when core is halted

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 5 - TIM7 counter stopped when core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - RTC counter stopped when core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - Window watchdog counter stopped when core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - Independent watchdog counter stopped when core is halted

pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W<'_>

Bit 21 - I2C1 SMBUS timeout counter stopped when core is halted

pub fn dbg_i2c2_stop(&mut self) -> DBG_I2C2_STOP_W<'_>

Bit 22 - I2C2 SMBUS timeout counter stopped when core is halted

pub fn dbg_i2c3_stop(&mut self) -> DBG_I2C3_STOP_W<'_>

Bit 23 - I2C3 SMBUS timeout counter stopped when core is halted

pub fn dbg_can_stop(&mut self) -> DBG_CAN_STOP_W<'_>

Bit 25 - bxCAN stopped when core is halted

pub fn dbg_lptim1_stop(&mut self) -> DBG_LPTIM1_STOP_W<'_>

Bit 31 - LPTIM1 counter stopped when core is halted

impl W<u32, Reg<u32, _APB1FZR2>>

pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W<'_>

Bit 5 - LPTIM2 counter stopped when core is halted

impl W<u32, Reg<u32, _APB2FZR>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>

Bit 16 - TIM15 counter stopped when core is halted

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 17 - TIM16 counter stopped when core is halted

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn etr_rmp(&mut self) -> ETR_RMP_W<'_>

Bits 0:2 - Timer2 ETR remap

pub fn ti4_rmp(&mut self) -> TI4_RMP_W<'_>

Bits 3:4 - Internal trigger

impl W<u32, Reg<u32, _CCR>>

pub fn ch18sel(&mut self) -> CH18SEL_W<'_>

Bit 24 - CH18 selection (Vbat)

pub fn ch17sel(&mut self) -> CH17SEL_W<'_>

Bit 23 - CH17 selection (temperature)

pub fn vrefen(&mut self) -> VREFEN_W<'_>

Bit 22 - Vrefint enable

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 18:21 - ADC prescaler

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bits 16:17 - ADC clock mode

pub fn mdma(&mut self) -> MDMA_W<'_>

Bits 14:15 - Direct memory access mode for dual ADC mode

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 13 - DMA configuration (for dual ADC mode)

pub fn delay(&mut self) -> DELAY_W<'_>

Bits 8:11 - Delay between 2 sampling phases

pub fn dual(&mut self) -> DUAL_W<'_>

Bits 0:4 - Dual ADC mode selection

impl W<u32, Reg<u32, _CR>>

pub fn en1(&mut self) -> EN1_W<'_>

Bit 0 - DAC channel1 enable

pub fn ten1(&mut self) -> TEN1_W<'_>

Bit 2 - DAC channel1 trigger enable

pub fn tsel1(&mut self) -> TSEL1_W<'_>

Bits 3:5 - DAC channel1 trigger selection

pub fn wave1(&mut self) -> WAVE1_W<'_>

Bits 6:7 - DAC channel1 noise/triangle wave generation enable

pub fn mamp1(&mut self) -> MAMP1_W<'_>

Bits 8:11 - DAC channel1 mask/amplitude selector

pub fn dmaen1(&mut self) -> DMAEN1_W<'_>

Bit 12 - DAC channel1 DMA enable

pub fn dmaudrie1(&mut self) -> DMAUDRIE1_W<'_>

Bit 13 - DAC channel1 DMA Underrun Interrupt enable

pub fn cen1(&mut self) -> CEN1_W<'_>

Bit 14 - DAC Channel 1 calibration enable

pub fn en2(&mut self) -> EN2_W<'_>

Bit 16 - DAC channel2 enable

pub fn ten2(&mut self) -> TEN2_W<'_>

Bit 18 - DAC channel2 trigger enable

pub fn tsel2(&mut self) -> TSEL2_W<'_>

Bits 19:21 - DAC channel2 trigger selection

pub fn wave2(&mut self) -> WAVE2_W<'_>

Bits 22:23 - DAC channel2 noise/triangle wave generation enable

pub fn mamp2(&mut self) -> MAMP2_W<'_>

Bits 24:27 - DAC channel2 mask/amplitude selector

pub fn dmaen2(&mut self) -> DMAEN2_W<'_>

Bit 28 - DAC channel2 DMA enable

pub fn dmaudrie2(&mut self) -> DMAUDRIE2_W<'_>

Bit 29 - DAC channel2 DMA underrun interrupt enable

pub fn cen2(&mut self) -> CEN2_W<'_>

Bit 30 - DAC Channel 2 calibration enable

impl W<u32, Reg<u32, _SWTRIGR>>

pub fn swtrig1(&mut self) -> SWTRIG1_W<'_>

Bit 0 - DAC channel1 software trigger

pub fn swtrig2(&mut self) -> SWTRIG2_W<'_>

Bit 1 - DAC channel2 software trigger

impl W<u32, Reg<u32, _DHR12R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R1>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:11 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12L2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 4:15 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8R2>>

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 0:7 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _DHR12RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:11 - DAC channel1 12-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 16:27 - DAC channel2 12-bit right-aligned data

impl W<u32, Reg<u32, _DHR12LD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 4:15 - DAC channel1 12-bit left-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 20:31 - DAC channel2 12-bit left-aligned data

impl W<u32, Reg<u32, _DHR8RD>>

pub fn dacc1dhr(&mut self) -> DACC1DHR_W<'_>

Bits 0:7 - DAC channel1 8-bit right-aligned data

pub fn dacc2dhr(&mut self) -> DACC2DHR_W<'_>

Bits 8:15 - DAC channel2 8-bit right-aligned data

impl W<u32, Reg<u32, _SR>>

pub fn dmaudr1(&mut self) -> DMAUDR1_W<'_>

Bit 13 - DAC channel1 DMA underrun flag

pub fn dmaudr2(&mut self) -> DMAUDR2_W<'_>

Bit 29 - DAC channel2 DMA underrun flag

impl W<u32, Reg<u32, _CCR>>

pub fn otrim1(&mut self) -> OTRIM1_W<'_>

Bits 0:4 - DAC Channel 1 offset trimming value

pub fn otrim2(&mut self) -> OTRIM2_W<'_>

Bits 16:20 - DAC Channel 2 offset trimming value

impl W<u32, Reg<u32, _MCR>>

pub fn mode1(&mut self) -> MODE1_W<'_>

Bits 0:2 - DAC Channel 1 mode

pub fn mode2(&mut self) -> MODE2_W<'_>

Bits 16:18 - DAC Channel 2 mode

impl W<u32, Reg<u32, _SHSR1>>

pub fn tsample1(&mut self) -> TSAMPLE1_W<'_>

Bits 0:9 - DAC Channel 1 sample Time

impl W<u32, Reg<u32, _SHSR2>>

pub fn tsample2(&mut self) -> TSAMPLE2_W<'_>

Bits 0:9 - DAC Channel 2 sample Time

impl W<u32, Reg<u32, _SHHR>>

pub fn thold1(&mut self) -> THOLD1_W<'_>

Bits 0:9 - DAC Channel 1 hold Time

pub fn thold2(&mut self) -> THOLD2_W<'_>

Bits 16:25 - DAC Channel 2 hold time

impl W<u32, Reg<u32, _SHRR>>

pub fn trefresh1(&mut self) -> TREFRESH1_W<'_>

Bits 0:7 - DAC Channel 1 refresh Time

pub fn trefresh2(&mut self) -> TREFRESH2_W<'_>

Bits 16:23 - DAC Channel 2 refresh Time

impl W<u32, Reg<u32, _IFCR>>

pub fn cteif7(&mut self) -> CTEIF7_W<'_>

Bit 27 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif7(&mut self) -> CHTIF7_W<'_>

Bit 26 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif7(&mut self) -> CTCIF7_W<'_>

Bit 25 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif7(&mut self) -> CGIF7_W<'_>

Bit 24 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif6(&mut self) -> CTEIF6_W<'_>

Bit 23 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif6(&mut self) -> CHTIF6_W<'_>

Bit 22 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif6(&mut self) -> CTCIF6_W<'_>

Bit 21 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif6(&mut self) -> CGIF6_W<'_>

Bit 20 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif5(&mut self) -> CTEIF5_W<'_>

Bit 19 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif5(&mut self) -> CHTIF5_W<'_>

Bit 18 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif5(&mut self) -> CTCIF5_W<'_>

Bit 17 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif5(&mut self) -> CGIF5_W<'_>

Bit 16 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif4(&mut self) -> CTEIF4_W<'_>

Bit 15 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif4(&mut self) -> CHTIF4_W<'_>

Bit 14 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif4(&mut self) -> CTCIF4_W<'_>

Bit 13 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif4(&mut self) -> CGIF4_W<'_>

Bit 12 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif3(&mut self) -> CTEIF3_W<'_>

Bit 11 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif3(&mut self) -> CHTIF3_W<'_>

Bit 10 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif3(&mut self) -> CTCIF3_W<'_>

Bit 9 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif3(&mut self) -> CGIF3_W<'_>

Bit 8 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif2(&mut self) -> CTEIF2_W<'_>

Bit 7 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif2(&mut self) -> CHTIF2_W<'_>

Bit 6 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif2(&mut self) -> CTCIF2_W<'_>

Bit 5 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif2(&mut self) -> CGIF2_W<'_>

Bit 4 - Channel x global interrupt clear (x = 1 ..7)

pub fn cteif1(&mut self) -> CTEIF1_W<'_>

Bit 3 - Channel x transfer error clear (x = 1 ..7)

pub fn chtif1(&mut self) -> CHTIF1_W<'_>

Bit 2 - Channel x half transfer clear (x = 1 ..7)

pub fn ctcif1(&mut self) -> CTCIF1_W<'_>

Bit 1 - Channel x transfer complete clear (x = 1 ..7)

pub fn cgif1(&mut self) -> CGIF1_W<'_>

Bit 0 - Channel x global interrupt clear (x = 1 ..7)

impl W<u32, Reg<u32, _CCR1>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR1>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR1>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR1>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR2>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR2>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR2>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR2>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR3>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR3>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR3>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR3>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR4>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR4>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR4>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR4>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR5>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR5>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR5>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR5>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR6>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR6>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR6>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR6>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CCR7>>

pub fn mem2mem(&mut self) -> MEM2MEM_W<'_>

Bit 14 - Memory to memory mode

pub fn pl(&mut self) -> PL_W<'_>

Bits 12:13 - Channel priority level

pub fn msize(&mut self) -> MSIZE_W<'_>

Bits 10:11 - Memory size

pub fn psize(&mut self) -> PSIZE_W<'_>

Bits 8:9 - Peripheral size

pub fn minc(&mut self) -> MINC_W<'_>

Bit 7 - Memory increment mode

pub fn pinc(&mut self) -> PINC_W<'_>

Bit 6 - Peripheral increment mode

pub fn circ(&mut self) -> CIRC_W<'_>

Bit 5 - Circular mode

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Data transfer direction

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 3 - Transfer error interrupt enable

pub fn htie(&mut self) -> HTIE_W<'_>

Bit 2 - Half transfer interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 1 - Transfer complete interrupt enable

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Channel enable

impl W<u32, Reg<u32, _CNDTR7>>

pub fn ndt(&mut self) -> NDT_W<'_>

Bits 0:15 - Number of data to transfer

impl W<u32, Reg<u32, _CPAR7>>

pub fn pa(&mut self) -> PA_W<'_>

Bits 0:31 - Peripheral address

impl W<u32, Reg<u32, _CMAR7>>

pub fn ma(&mut self) -> MA_W<'_>

Bits 0:31 - Memory address

impl W<u32, Reg<u32, _CSELR>>

pub fn c7s(&mut self) -> C7S_W<'_>

Bits 24:27 - DMA channel 7 selection

pub fn c6s(&mut self) -> C6S_W<'_>

Bits 20:23 - DMA channel 6 selection

pub fn c5s(&mut self) -> C5S_W<'_>

Bits 16:19 - DMA channel 5 selection

pub fn c4s(&mut self) -> C4S_W<'_>

Bits 12:15 - DMA channel 4 selection

pub fn c3s(&mut self) -> C3S_W<'_>

Bits 8:11 - DMA channel 3 selection

pub fn c2s(&mut self) -> C2S_W<'_>

Bits 4:7 - DMA channel 2 selection

pub fn c1s(&mut self) -> C1S_W<'_>

Bits 0:3 - DMA channel 1 selection

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:31 - Data register bits

impl W<u32, Reg<u32, _IDR>>

pub fn idr(&mut self) -> IDR_W<'_>

Bits 0:7 - General-purpose 8-bit data register bits

impl W<u32, Reg<u32, _CR>>

pub fn rev_out(&mut self) -> REV_OUT_W<'_>

Bit 7 - Reverse output data

pub fn rev_in(&mut self) -> REV_IN_W<'_>

Bits 5:6 - Reverse input data

pub fn polysize(&mut self) -> POLYSIZE_W<'_>

Bits 3:4 - Polynomial size

pub fn reset(&mut self) -> RESET_W<'_>

Bit 0 - RESET bit

impl W<u32, Reg<u32, _INIT>>

pub fn init(&mut self) -> INIT_W<'_>

Bits 0:31 - Programmable initial CRC value

impl W<u32, Reg<u32, _POL>>

pub fn polynomialcoefficients(&mut self) -> POLYNOMIALCOEFFICIENTS_W<'_>

Bits 0:31 - Programmable polynomial

impl W<u8, Reg<u8, _DR8>>

pub fn dr8(&mut self) -> DR8_W<'_>

Bits 0:7 - Data register bits

impl W<u16, Reg<u16, _DR16>>

pub fn dr16(&mut self) -> DR16_W<'_>

Bits 0:15 - Data register bits

impl W<u32, Reg<u32, _CR>>

pub fn bias(&mut self) -> BIAS_W<'_>

Bits 5:6 - Bias selector

pub fn duty(&mut self) -> DUTY_W<'_>

Bits 2:4 - Duty selection

pub fn vsel(&mut self) -> VSEL_W<'_>

Bit 1 - Voltage source selection

pub fn lcden(&mut self) -> LCDEN_W<'_>

Bit 0 - LCD controller enable

pub fn mux_seg(&mut self) -> MUX_SEG_W<'_>

Bit 7 - Mux segment enable

pub fn bufen(&mut self) -> BUFEN_W<'_>

Bit 8 - Voltage output buffer enable

impl W<u32, Reg<u32, _FCR>>

pub fn ps(&mut self) -> PS_W<'_>

Bits 22:25 - PS 16-bit prescaler

pub fn div(&mut self) -> DIV_W<'_>

Bits 18:21 - DIV clock divider

pub fn blink(&mut self) -> BLINK_W<'_>

Bits 16:17 - Blink mode selection

pub fn blinkf(&mut self) -> BLINKF_W<'_>

Bits 13:15 - Blink frequency selection

pub fn cc(&mut self) -> CC_W<'_>

Bits 10:12 - Contrast control

pub fn dead(&mut self) -> DEAD_W<'_>

Bits 7:9 - Dead time duration

pub fn pon(&mut self) -> PON_W<'_>

Bits 4:6 - Pulse ON duration

pub fn uddie(&mut self) -> UDDIE_W<'_>

Bit 3 - Update display done interrupt enable

pub fn sofie(&mut self) -> SOFIE_W<'_>

Bit 1 - Start of frame interrupt enable

pub fn hd(&mut self) -> HD_W<'_>

Bit 0 - High drive enable

impl W<u32, Reg<u32, _SR>>

pub fn udr(&mut self) -> UDR_W<'_>

Bit 2 - Update display request

impl W<u32, Reg<u32, _CLR>>

pub fn uddc(&mut self) -> UDDC_W<'_>

Bit 3 - Update display done clear

pub fn sofc(&mut self) -> SOFC_W<'_>

Bit 1 - Start of frame flag clear

impl W<u32, Reg<u32, _RAM_COM0>>

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM1>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM2>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM3>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM4>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM5>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM6>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _RAM_COM7>>

pub fn s31(&mut self) -> S31_W<'_>

Bit 31 - S31

pub fn s30(&mut self) -> S30_W<'_>

Bit 30 - S30

pub fn s29(&mut self) -> S29_W<'_>

Bit 29 - S29

pub fn s28(&mut self) -> S28_W<'_>

Bit 28 - S28

pub fn s27(&mut self) -> S27_W<'_>

Bit 27 - S27

pub fn s26(&mut self) -> S26_W<'_>

Bit 26 - S26

pub fn s25(&mut self) -> S25_W<'_>

Bit 25 - S25

pub fn s24(&mut self) -> S24_W<'_>

Bit 24 - S24

pub fn s23(&mut self) -> S23_W<'_>

Bit 23 - S23

pub fn s22(&mut self) -> S22_W<'_>

Bit 22 - S22

pub fn s21(&mut self) -> S21_W<'_>

Bit 21 - S21

pub fn s20(&mut self) -> S20_W<'_>

Bit 20 - S20

pub fn s19(&mut self) -> S19_W<'_>

Bit 19 - S19

pub fn s18(&mut self) -> S18_W<'_>

Bit 18 - S18

pub fn s17(&mut self) -> S17_W<'_>

Bit 17 - S17

pub fn s16(&mut self) -> S16_W<'_>

Bit 16 - S16

pub fn s15(&mut self) -> S15_W<'_>

Bit 15 - S15

pub fn s14(&mut self) -> S14_W<'_>

Bit 14 - S14

pub fn s13(&mut self) -> S13_W<'_>

Bit 13 - S13

pub fn s12(&mut self) -> S12_W<'_>

Bit 12 - S12

pub fn s11(&mut self) -> S11_W<'_>

Bit 11 - S11

pub fn s10(&mut self) -> S10_W<'_>

Bit 10 - S10

pub fn s09(&mut self) -> S09_W<'_>

Bit 9 - S09

pub fn s08(&mut self) -> S08_W<'_>

Bit 8 - S08

pub fn s07(&mut self) -> S07_W<'_>

Bit 7 - S07

pub fn s06(&mut self) -> S06_W<'_>

Bit 6 - S06

pub fn s05(&mut self) -> S05_W<'_>

Bit 5 - S05

pub fn s04(&mut self) -> S04_W<'_>

Bit 4 - S04

pub fn s03(&mut self) -> S03_W<'_>

Bit 3 - S03

pub fn s02(&mut self) -> S02_W<'_>

Bit 2 - S02

pub fn s01(&mut self) -> S01_W<'_>

Bit 1 - S01

pub fn s00(&mut self) -> S00_W<'_>

Bit 0 - S00

impl W<u32, Reg<u32, _CR>>

pub fn ctph(&mut self) -> CTPH_W<'_>

Bits 28:31 - Charge transfer pulse high

pub fn ctpl(&mut self) -> CTPL_W<'_>

Bits 24:27 - Charge transfer pulse low

pub fn ssd(&mut self) -> SSD_W<'_>

Bits 17:23 - Spread spectrum deviation

pub fn sse(&mut self) -> SSE_W<'_>

Bit 16 - Spread spectrum enable

pub fn sspsc(&mut self) -> SSPSC_W<'_>

Bit 15 - Spread spectrum prescaler

pub fn pgpsc(&mut self) -> PGPSC_W<'_>

Bits 12:14 - pulse generator prescaler

pub fn mcv(&mut self) -> MCV_W<'_>

Bits 5:7 - Max count value

pub fn iodef(&mut self) -> IODEF_W<'_>

Bit 4 - I/O Default mode

pub fn syncpol(&mut self) -> SYNCPOL_W<'_>

Bit 3 - Synchronization pin polarity

pub fn am(&mut self) -> AM_W<'_>

Bit 2 - Acquisition mode

pub fn start(&mut self) -> START_W<'_>

Bit 1 - Start a new acquisition

pub fn tsce(&mut self) -> TSCE_W<'_>

Bit 0 - Touch sensing controller enable

impl W<u32, Reg<u32, _IER>>

pub fn mceie(&mut self) -> MCEIE_W<'_>

Bit 1 - Max count error interrupt enable

pub fn eoaie(&mut self) -> EOAIE_W<'_>

Bit 0 - End of acquisition interrupt enable

impl W<u32, Reg<u32, _ICR>>

pub fn mceic(&mut self) -> MCEIC_W<'_>

Bit 1 - Max count error interrupt clear

pub fn eoaic(&mut self) -> EOAIC_W<'_>

Bit 0 - End of acquisition interrupt clear

impl W<u32, Reg<u32, _ISR>>

pub fn mcef(&mut self) -> MCEF_W<'_>

Bit 1 - Max count error flag

pub fn eoaf(&mut self) -> EOAF_W<'_>

Bit 0 - End of acquisition flag

impl W<u32, Reg<u32, _IOHCR>>

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOASCR>>

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOSCR>>

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOCCR>>

pub fn g8_io4(&mut self) -> G8_IO4_W<'_>

Bit 31 - G8_IO4

pub fn g8_io3(&mut self) -> G8_IO3_W<'_>

Bit 30 - G8_IO3

pub fn g8_io2(&mut self) -> G8_IO2_W<'_>

Bit 29 - G8_IO2

pub fn g8_io1(&mut self) -> G8_IO1_W<'_>

Bit 28 - G8_IO1

pub fn g7_io4(&mut self) -> G7_IO4_W<'_>

Bit 27 - G7_IO4

pub fn g7_io3(&mut self) -> G7_IO3_W<'_>

Bit 26 - G7_IO3

pub fn g7_io2(&mut self) -> G7_IO2_W<'_>

Bit 25 - G7_IO2

pub fn g7_io1(&mut self) -> G7_IO1_W<'_>

Bit 24 - G7_IO1

pub fn g6_io4(&mut self) -> G6_IO4_W<'_>

Bit 23 - G6_IO4

pub fn g6_io3(&mut self) -> G6_IO3_W<'_>

Bit 22 - G6_IO3

pub fn g6_io2(&mut self) -> G6_IO2_W<'_>

Bit 21 - G6_IO2

pub fn g6_io1(&mut self) -> G6_IO1_W<'_>

Bit 20 - G6_IO1

pub fn g5_io4(&mut self) -> G5_IO4_W<'_>

Bit 19 - G5_IO4

pub fn g5_io3(&mut self) -> G5_IO3_W<'_>

Bit 18 - G5_IO3

pub fn g5_io2(&mut self) -> G5_IO2_W<'_>

Bit 17 - G5_IO2

pub fn g5_io1(&mut self) -> G5_IO1_W<'_>

Bit 16 - G5_IO1

pub fn g4_io4(&mut self) -> G4_IO4_W<'_>

Bit 15 - G4_IO4

pub fn g4_io3(&mut self) -> G4_IO3_W<'_>

Bit 14 - G4_IO3

pub fn g4_io2(&mut self) -> G4_IO2_W<'_>

Bit 13 - G4_IO2

pub fn g4_io1(&mut self) -> G4_IO1_W<'_>

Bit 12 - G4_IO1

pub fn g3_io4(&mut self) -> G3_IO4_W<'_>

Bit 11 - G3_IO4

pub fn g3_io3(&mut self) -> G3_IO3_W<'_>

Bit 10 - G3_IO3

pub fn g3_io2(&mut self) -> G3_IO2_W<'_>

Bit 9 - G3_IO2

pub fn g3_io1(&mut self) -> G3_IO1_W<'_>

Bit 8 - G3_IO1

pub fn g2_io4(&mut self) -> G2_IO4_W<'_>

Bit 7 - G2_IO4

pub fn g2_io3(&mut self) -> G2_IO3_W<'_>

Bit 6 - G2_IO3

pub fn g2_io2(&mut self) -> G2_IO2_W<'_>

Bit 5 - G2_IO2

pub fn g2_io1(&mut self) -> G2_IO1_W<'_>

Bit 4 - G2_IO1

pub fn g1_io4(&mut self) -> G1_IO4_W<'_>

Bit 3 - G1_IO4

pub fn g1_io3(&mut self) -> G1_IO3_W<'_>

Bit 2 - G1_IO3

pub fn g1_io2(&mut self) -> G1_IO2_W<'_>

Bit 1 - G1_IO2

pub fn g1_io1(&mut self) -> G1_IO1_W<'_>

Bit 0 - G1_IO1

impl W<u32, Reg<u32, _IOGCSR>>

pub fn g8e(&mut self) -> G8E_W<'_>

Bit 7 - Analog I/O group x enable

pub fn g7e(&mut self) -> G7E_W<'_>

Bit 6 - Analog I/O group x enable

pub fn g6e(&mut self) -> G6E_W<'_>

Bit 5 - Analog I/O group x enable

pub fn g5e(&mut self) -> G5E_W<'_>

Bit 4 - Analog I/O group x enable

pub fn g4e(&mut self) -> G4E_W<'_>

Bit 3 - Analog I/O group x enable

pub fn g3e(&mut self) -> G3E_W<'_>

Bit 2 - Analog I/O group x enable

pub fn g2e(&mut self) -> G2E_W<'_>

Bit 1 - Analog I/O group x enable

pub fn g1e(&mut self) -> G1E_W<'_>

Bit 0 - Analog I/O group x enable

impl W<u32, Reg<u32, _KR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:15 - Key value (write only, read 0x0000)

impl W<u32, Reg<u32, _PR>>

pub fn pr(&mut self) -> PR_W<'_>

Bits 0:2 - Prescaler divider

impl W<u32, Reg<u32, _RLR>>

pub fn rl(&mut self) -> RL_W<'_>

Bits 0:11 - Watchdog counter reload value

impl W<u32, Reg<u32, _WINR>>

pub fn win(&mut self) -> WIN_W<'_>

Bits 0:11 - Watchdog counter window value

impl W<u32, Reg<u32, _CR>>

pub fn wdga(&mut self) -> WDGA_W<'_>

Bit 7 - Activation bit

pub fn t(&mut self) -> T_W<'_>

Bits 0:6 - 7-bit counter (MSB to LSB)

impl W<u32, Reg<u32, _CFR>>

pub fn ewi(&mut self) -> EWI_W<'_>

Bit 9 - Early wakeup interrupt

pub fn w(&mut self) -> W_W<'_>

Bits 0:6 - 7-bit window value

pub fn wdgtb(&mut self) -> WDGTB_W<'_>

Bits 7:8 - Timer base

impl W<u32, Reg<u32, _SR>>

pub fn ewif(&mut self) -> EWIF_W<'_>

Bit 0 - Early wakeup interrupt flag

impl W<u32, Reg<u32, _COMP1_CSR>>

pub fn comp1_en(&mut self) -> COMP1_EN_W<'_>

Bit 0 - Comparator 1 enable bit

pub fn comp1_pwrmode(&mut self) -> COMP1_PWRMODE_W<'_>

Bits 2:3 - Power Mode of the comparator 1

pub fn comp1_inmsel(&mut self) -> COMP1_INMSEL_W<'_>

Bits 4:6 - Comparator 1 Input Minus connection configuration bit

pub fn comp1_inpsel(&mut self) -> COMP1_INPSEL_W<'_>

Bit 7 - Comparator1 input plus selection bit

pub fn comp1_polarity(&mut self) -> COMP1_POLARITY_W<'_>

Bit 15 - Comparator 1 polarity selection bit

pub fn comp1_hyst(&mut self) -> COMP1_HYST_W<'_>

Bits 16:17 - Comparator 1 hysteresis selection bits

pub fn comp1_blanking(&mut self) -> COMP1_BLANKING_W<'_>

Bits 18:20 - Comparator 1 blanking source selection bits

pub fn comp1_brgen(&mut self) -> COMP1_BRGEN_W<'_>

Bit 22 - Scaler bridge enable

pub fn comp1_scalen(&mut self) -> COMP1_SCALEN_W<'_>

Bit 23 - Voltage scaler enable bit

pub fn comp1_lock(&mut self) -> COMP1_LOCK_W<'_>

Bit 31 - COMP1_CSR register lock bit

impl W<u32, Reg<u32, _COMP2_CSR>>

pub fn comp2_en(&mut self) -> COMP2_EN_W<'_>

Bit 0 - Comparator 2 enable bit

pub fn comp2_pwrmode(&mut self) -> COMP2_PWRMODE_W<'_>

Bits 2:3 - Power Mode of the comparator 2

pub fn comp2_inmsel(&mut self) -> COMP2_INMSEL_W<'_>

Bits 4:6 - Comparator 2 Input Minus connection configuration bit

pub fn comp2_inpsel(&mut self) -> COMP2_INPSEL_W<'_>

Bit 7 - Comparator 2 Input Plus connection configuration bit

pub fn comp2_winmode(&mut self) -> COMP2_WINMODE_W<'_>

Bit 9 - Windows mode selection bit

pub fn comp2_polarity(&mut self) -> COMP2_POLARITY_W<'_>

Bit 15 - Comparator 2 polarity selection bit

pub fn comp2_hyst(&mut self) -> COMP2_HYST_W<'_>

Bits 16:17 - Comparator 2 hysteresis selection bits

pub fn comp2_blanking(&mut self) -> COMP2_BLANKING_W<'_>

Bits 18:20 - Comparator 2 blanking source selection bits

pub fn comp2_brgen(&mut self) -> COMP2_BRGEN_W<'_>

Bit 22 - Scaler bridge enable

pub fn comp2_scalen(&mut self) -> COMP2_SCALEN_W<'_>

Bit 23 - Voltage scaler enable bit

pub fn comp2_lock(&mut self) -> COMP2_LOCK_W<'_>

Bit 31 - COMP2_CSR register lock bit

impl W<u32, Reg<u32, _CSSA>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 8:23 - code segment start address

impl W<u32, Reg<u32, _CSL>>

pub fn leng(&mut self) -> LENG_W<'_>

Bits 8:21 - code segment length

impl W<u32, Reg<u32, _NVDSSA>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 8:23 - Non-volatile data segment start address

impl W<u32, Reg<u32, _NVDSL>>

pub fn leng(&mut self) -> LENG_W<'_>

Bits 8:21 - Non-volatile data segment length

impl W<u32, Reg<u32, _VDSSA>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 6:15 - Volatile data segment start address

impl W<u32, Reg<u32, _VDSL>>

pub fn leng(&mut self) -> LENG_W<'_>

Bits 6:15 - Non-volatile data segment length

impl W<u32, Reg<u32, _CR>>

pub fn vde(&mut self) -> VDE_W<'_>

Bit 2 - Volatile data execution

pub fn vds(&mut self) -> VDS_W<'_>

Bit 1 - Volatile data shared

pub fn fpa(&mut self) -> FPA_W<'_>

Bit 0 - Firewall pre alarm

impl W<u32, Reg<u32, _CR1>>

pub fn pe(&mut self) -> PE_W<'_>

Bit 0 - Peripheral enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 1 - TX Interrupt enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 2 - RX Interrupt enable

pub fn addrie(&mut self) -> ADDRIE_W<'_>

Bit 3 - Address match interrupt enable (slave only)

pub fn nackie(&mut self) -> NACKIE_W<'_>

Bit 4 - Not acknowledge received interrupt enable

pub fn stopie(&mut self) -> STOPIE_W<'_>

Bit 5 - STOP detection Interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transfer Complete interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 7 - Error interrupts enable

pub fn dnf(&mut self) -> DNF_W<'_>

Bits 8:11 - Digital noise filter

pub fn anfoff(&mut self) -> ANFOFF_W<'_>

Bit 12 - Analog noise filter OFF

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 14 - DMA transmission requests enable

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 15 - DMA reception requests enable

pub fn sbc(&mut self) -> SBC_W<'_>

Bit 16 - Slave byte control

pub fn nostretch(&mut self) -> NOSTRETCH_W<'_>

Bit 17 - Clock stretching disable

pub fn wupen(&mut self) -> WUPEN_W<'_>

Bit 18 - Wakeup from STOP enable

pub fn gcen(&mut self) -> GCEN_W<'_>

Bit 19 - General call enable

pub fn smbhen(&mut self) -> SMBHEN_W<'_>

Bit 20 - SMBus Host address enable

pub fn smbden(&mut self) -> SMBDEN_W<'_>

Bit 21 - SMBus Device Default address enable

pub fn alerten(&mut self) -> ALERTEN_W<'_>

Bit 22 - SMBUS alert enable

pub fn pecen(&mut self) -> PECEN_W<'_>

Bit 23 - PEC enable

impl W<u32, Reg<u32, _CR2>>

pub fn pecbyte(&mut self) -> PECBYTE_W<'_>

Bit 26 - Packet error checking byte

pub fn autoend(&mut self) -> AUTOEND_W<'_>

Bit 25 - Automatic end mode (master mode)

pub fn reload(&mut self) -> RELOAD_W<'_>

Bit 24 - NBYTES reload mode

pub fn nbytes(&mut self) -> NBYTES_W<'_>

Bits 16:23 - Number of bytes

pub fn nack(&mut self) -> NACK_W<'_>

Bit 15 - NACK generation (slave mode)

pub fn stop(&mut self) -> STOP_W<'_>

Bit 14 - Stop generation (master mode)

pub fn start(&mut self) -> START_W<'_>

Bit 13 - Start generation

pub fn head10r(&mut self) -> HEAD10R_W<'_>

Bit 12 - 10-bit address header only read direction (master receiver mode)

pub fn add10(&mut self) -> ADD10_W<'_>

Bit 11 - 10-bit addressing mode (master mode)

pub fn rd_wrn(&mut self) -> RD_WRN_W<'_>

Bit 10 - Transfer direction (master mode)

pub fn sadd(&mut self) -> SADD_W<'_>

Bits 0:9 - Slave address bit (master mode)

impl W<u32, Reg<u32, _OAR1>>

pub fn oa1(&mut self) -> OA1_W<'_>

Bits 0:9 - Interface address

pub fn oa1mode(&mut self) -> OA1MODE_W<'_>

Bit 10 - Own Address 1 10-bit mode

pub fn oa1en(&mut self) -> OA1EN_W<'_>

Bit 15 - Own Address 1 enable

impl W<u32, Reg<u32, _OAR2>>

pub fn oa2(&mut self) -> OA2_W<'_>

Bits 1:7 - Interface address

pub fn oa2msk(&mut self) -> OA2MSK_W<'_>

Bits 8:10 - Own Address 2 masks

pub fn oa2en(&mut self) -> OA2EN_W<'_>

Bit 15 - Own Address 2 enable

impl W<u32, Reg<u32, _TIMINGR>>

pub fn scll(&mut self) -> SCLL_W<'_>

Bits 0:7 - SCL low period (master mode)

pub fn sclh(&mut self) -> SCLH_W<'_>

Bits 8:15 - SCL high period (master mode)

pub fn sdadel(&mut self) -> SDADEL_W<'_>

Bits 16:19 - Data hold time

pub fn scldel(&mut self) -> SCLDEL_W<'_>

Bits 20:23 - Data setup time

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 28:31 - Timing prescaler

impl W<u32, Reg<u32, _TIMEOUTR>>

pub fn timeouta(&mut self) -> TIMEOUTA_W<'_>

Bits 0:11 - Bus timeout A

pub fn tidle(&mut self) -> TIDLE_W<'_>

Bit 12 - Idle clock timeout detection

pub fn timouten(&mut self) -> TIMOUTEN_W<'_>

Bit 15 - Clock timeout enable

pub fn timeoutb(&mut self) -> TIMEOUTB_W<'_>

Bits 16:27 - Bus timeout B

pub fn texten(&mut self) -> TEXTEN_W<'_>

Bit 31 - Extended clock timeout enable

impl W<u32, Reg<u32, _ISR>>

pub fn txis(&mut self) -> TXIS_W<'_>

Bit 1 - Transmit interrupt status (transmitters)

pub fn txe(&mut self) -> TXE_W<'_>

Bit 0 - Transmit data register empty (transmitters)

impl W<u32, Reg<u32, _ICR>>

pub fn alertcf(&mut self) -> ALERTCF_W<'_>

Bit 13 - Alert flag clear

pub fn timoutcf(&mut self) -> TIMOUTCF_W<'_>

Bit 12 - Timeout detection flag clear

pub fn peccf(&mut self) -> PECCF_W<'_>

Bit 11 - PEC Error flag clear

pub fn ovrcf(&mut self) -> OVRCF_W<'_>

Bit 10 - Overrun/Underrun flag clear

pub fn arlocf(&mut self) -> ARLOCF_W<'_>

Bit 9 - Arbitration lost flag clear

pub fn berrcf(&mut self) -> BERRCF_W<'_>

Bit 8 - Bus error flag clear

pub fn stopcf(&mut self) -> STOPCF_W<'_>

Bit 5 - Stop detection flag clear

pub fn nackcf(&mut self) -> NACKCF_W<'_>

Bit 4 - Not Acknowledge flag clear

pub fn addrcf(&mut self) -> ADDRCF_W<'_>

Bit 3 - Address Matched flag clear

impl W<u32, Reg<u32, _TXDR>>

pub fn txdata(&mut self) -> TXDATA_W<'_>

Bits 0:7 - 8-bit transmit data

impl W<u32, Reg<u32, _ACR>>

pub fn latency(&mut self) -> LATENCY_W<'_>

Bits 0:2 - Latency

pub fn prften(&mut self) -> PRFTEN_W<'_>

Bit 8 - Prefetch enable

pub fn icen(&mut self) -> ICEN_W<'_>

Bit 9 - Instruction cache enable

pub fn dcen(&mut self) -> DCEN_W<'_>

Bit 10 - Data cache enable

pub fn icrst(&mut self) -> ICRST_W<'_>

Bit 11 - Instruction cache reset

pub fn dcrst(&mut self) -> DCRST_W<'_>

Bit 12 - Data cache reset

pub fn run_pd(&mut self) -> RUN_PD_W<'_>

Bit 13 - Flash Power-down mode during Low-power run mode

pub fn sleep_pd(&mut self) -> SLEEP_PD_W<'_>

Bit 14 - Flash Power-down mode during Low-power sleep mode

impl W<u32, Reg<u32, _PDKEYR>>

pub fn pdkeyr(&mut self) -> PDKEYR_W<'_>

Bits 0:31 - RUN_PD in FLASH_ACR key

impl W<u32, Reg<u32, _KEYR>>

pub fn keyr(&mut self) -> KEYR_W<'_>

Bits 0:31 - KEYR

impl W<u32, Reg<u32, _OPTKEYR>>

pub fn optkeyr(&mut self) -> OPTKEYR_W<'_>

Bits 0:31 - Option byte key

impl W<u32, Reg<u32, _SR>>

pub fn eop(&mut self) -> EOP_W<'_>

Bit 0 - End of operation

pub fn operr(&mut self) -> OPERR_W<'_>

Bit 1 - Operation error

pub fn progerr(&mut self) -> PROGERR_W<'_>

Bit 3 - Programming error

pub fn wrperr(&mut self) -> WRPERR_W<'_>

Bit 4 - Write protected error

pub fn pgaerr(&mut self) -> PGAERR_W<'_>

Bit 5 - Programming alignment error

pub fn sizerr(&mut self) -> SIZERR_W<'_>

Bit 6 - Size error

pub fn pgserr(&mut self) -> PGSERR_W<'_>

Bit 7 - Programming sequence error

pub fn miserr(&mut self) -> MISERR_W<'_>

Bit 8 - Fast programming data miss error

pub fn fasterr(&mut self) -> FASTERR_W<'_>

Bit 9 - Fast programming error

pub fn rderr(&mut self) -> RDERR_W<'_>

Bit 14 - PCROP read error

pub fn optverr(&mut self) -> OPTVERR_W<'_>

Bit 15 - Option validity error

impl W<u32, Reg<u32, _CR>>

pub fn pg(&mut self) -> PG_W<'_>

Bit 0 - Programming

pub fn per(&mut self) -> PER_W<'_>

Bit 1 - Page erase

pub fn mer1(&mut self) -> MER1_W<'_>

Bit 2 - Bank 1 Mass erase

pub fn pnb(&mut self) -> PNB_W<'_>

Bits 3:10 - Page number

pub fn bker(&mut self) -> BKER_W<'_>

Bit 11 - Bank erase

pub fn mer2(&mut self) -> MER2_W<'_>

Bit 15 - Bank 2 Mass erase

pub fn start(&mut self) -> START_W<'_>

Bit 16 - Start

pub fn optstrt(&mut self) -> OPTSTRT_W<'_>

Bit 17 - Options modification start

pub fn fstpg(&mut self) -> FSTPG_W<'_>

Bit 18 - Fast programming

pub fn eopie(&mut self) -> EOPIE_W<'_>

Bit 24 - End of operation interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 25 - Error interrupt enable

pub fn rderrie(&mut self) -> RDERRIE_W<'_>

Bit 26 - PCROP read error interrupt enable

pub fn obl_launch(&mut self) -> OBL_LAUNCH_W<'_>

Bit 27 - Force the option byte loading

pub fn optlock(&mut self) -> OPTLOCK_W<'_>

Bit 30 - Options Lock

pub fn lock(&mut self) -> LOCK_W<'_>

Bit 31 - FLASH_CR Lock

impl W<u32, Reg<u32, _ECCR>>

pub fn eccie(&mut self) -> ECCIE_W<'_>

Bit 24 - ECC correction interrupt enable

pub fn eccc(&mut self) -> ECCC_W<'_>

Bit 30 - ECC correction

pub fn eccd(&mut self) -> ECCD_W<'_>

Bit 31 - ECC detection

impl W<u32, Reg<u32, _OPTR>>

pub fn rdp(&mut self) -> RDP_W<'_>

Bits 0:7 - Read protection level

pub fn bor_lev(&mut self) -> BOR_LEV_W<'_>

Bits 8:10 - BOR reset Level

pub fn n_rst_stop(&mut self) -> NRST_STOP_W<'_>

Bit 12 - nRST_STOP

pub fn n_rst_stdby(&mut self) -> NRST_STDBY_W<'_>

Bit 13 - nRST_STDBY

pub fn idwg_sw(&mut self) -> IDWG_SW_W<'_>

Bit 16 - Independent watchdog selection

pub fn iwdg_stop(&mut self) -> IWDG_STOP_W<'_>

Bit 17 - Independent watchdog counter freeze in Stop mode

pub fn iwdg_stdby(&mut self) -> IWDG_STDBY_W<'_>

Bit 18 - Independent watchdog counter freeze in Standby mode

pub fn wwdg_sw(&mut self) -> WWDG_SW_W<'_>

Bit 19 - Window watchdog selection

pub fn bfb2(&mut self) -> BFB2_W<'_>

Bit 20 - Dual-bank boot

pub fn dualbank(&mut self) -> DUALBANK_W<'_>

Bit 21 - Dual-Bank on 512 KB or 256 KB Flash memory devices

pub fn n_boot1(&mut self) -> NBOOT1_W<'_>

Bit 23 - Boot configuration

pub fn sram2_pe(&mut self) -> SRAM2_PE_W<'_>

Bit 24 - SRAM2 parity check enable

pub fn sram2_rst(&mut self) -> SRAM2_RST_W<'_>

Bit 25 - SRAM2 Erase when system reset

pub fn n_swboot0(&mut self) -> NSWBOOT0_W<'_>

Bit 26 - Software BOOT0

pub fn n_boot0(&mut self) -> NBOOT0_W<'_>

Bit 27 - nBOOT0 option bit

impl W<u32, Reg<u32, _PCROP1SR>>

pub fn pcrop1_strt(&mut self) -> PCROP1_STRT_W<'_>

Bits 0:15 - Bank 1 PCROP area start offset

impl W<u32, Reg<u32, _PCROP1ER>>

pub fn pcrop1_end(&mut self) -> PCROP1_END_W<'_>

Bits 0:15 - Bank 1 PCROP area end offset

pub fn pcrop_rdp(&mut self) -> PCROP_RDP_W<'_>

Bit 31 - PCROP area preserved when RDP level decreased

impl W<u32, Reg<u32, _WRP1AR>>

pub fn wrp1a_strt(&mut self) -> WRP1A_STRT_W<'_>

Bits 0:7 - Bank 1 WRP first area start offset

pub fn wrp1a_end(&mut self) -> WRP1A_END_W<'_>

Bits 16:23 - Bank 1 WRP first area A end offset

impl W<u32, Reg<u32, _WRP1BR>>

pub fn wrp1b_strt(&mut self) -> WRP1B_STRT_W<'_>

Bits 16:23 - Bank 1 WRP second area B end offset

pub fn wrp1b_end(&mut self) -> WRP1B_END_W<'_>

Bits 0:7 - Bank 1 WRP second area B start offset

impl W<u32, Reg<u32, _PCROP2SR>>

pub fn pcrop2_strt(&mut self) -> PCROP2_STRT_W<'_>

Bits 0:15 - Bank 2 PCROP area start offset

impl W<u32, Reg<u32, _PCROP2ER>>

pub fn pcrop2_end(&mut self) -> PCROP2_END_W<'_>

Bits 0:15 - Bank 2 PCROP area end offset

impl W<u32, Reg<u32, _WRP2AR>>

pub fn wrp2a_strt(&mut self) -> WRP2A_STRT_W<'_>

Bits 0:7 - Bank 2 WRP first area A start offset

pub fn wrp2a_end(&mut self) -> WRP2A_END_W<'_>

Bits 16:23 - Bank 2 WRP first area A end offset

impl W<u32, Reg<u32, _WRP2BR>>

pub fn wrp2b_strt(&mut self) -> WRP2B_STRT_W<'_>

Bits 0:7 - Bank 2 WRP second area B start offset

pub fn wrp2b_end(&mut self) -> WRP2B_END_W<'_>

Bits 16:23 - Bank 2 WRP second area B end offset

impl W<u32, Reg<u32, _CR1>>

pub fn lpr(&mut self) -> LPR_W<'_>

Bit 14 - Low-power run

pub fn vos(&mut self) -> VOS_W<'_>

Bits 9:10 - Voltage scaling range selection

pub fn dbp(&mut self) -> DBP_W<'_>

Bit 8 - Disable backup domain write protection

pub fn lpms(&mut self) -> LPMS_W<'_>

Bits 0:2 - Low-power mode selection

impl W<u32, Reg<u32, _CR2>>

pub fn usv(&mut self) -> USV_W<'_>

Bit 10 - VDDUSB USB supply valid

pub fn iosv(&mut self) -> IOSV_W<'_>

Bit 9 - VDDIO2 Independent I/Os supply valid

pub fn pvme4(&mut self) -> PVME4_W<'_>

Bit 7 - Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V

pub fn pvme3(&mut self) -> PVME3_W<'_>

Bit 6 - Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V

pub fn pvme2(&mut self) -> PVME2_W<'_>

Bit 5 - Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V

pub fn pvme1(&mut self) -> PVME1_W<'_>

Bit 4 - Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V

pub fn pls(&mut self) -> PLS_W<'_>

Bits 1:3 - Power voltage detector level selection

pub fn pvde(&mut self) -> PVDE_W<'_>

Bit 0 - Power voltage detector enable

impl W<u32, Reg<u32, _CR3>>

pub fn ewf(&mut self) -> EWF_W<'_>

Bit 15 - Enable internal wakeup line

pub fn apc(&mut self) -> APC_W<'_>

Bit 10 - Apply pull-up and pull-down configuration

pub fn rrs(&mut self) -> RRS_W<'_>

Bit 8 - SRAM2 retention in Standby mode

pub fn ewup5(&mut self) -> EWUP5_W<'_>

Bit 4 - Enable Wakeup pin WKUP5

pub fn ewup4(&mut self) -> EWUP4_W<'_>

Bit 3 - Enable Wakeup pin WKUP4

pub fn ewup3(&mut self) -> EWUP3_W<'_>

Bit 2 - Enable Wakeup pin WKUP3

pub fn ewup2(&mut self) -> EWUP2_W<'_>

Bit 1 - Enable Wakeup pin WKUP2

pub fn ewup1(&mut self) -> EWUP1_W<'_>

Bit 0 - Enable Wakeup pin WKUP1

impl W<u32, Reg<u32, _CR4>>

pub fn vbrs(&mut self) -> VBRS_W<'_>

Bit 9 - VBAT battery charging resistor selection

pub fn vbe(&mut self) -> VBE_W<'_>

Bit 8 - VBAT battery charging enable

pub fn wp5(&mut self) -> WP5_W<'_>

Bit 4 - Wakeup pin WKUP5 polarity

pub fn wp4(&mut self) -> WP4_W<'_>

Bit 3 - Wakeup pin WKUP4 polarity

pub fn wp3(&mut self) -> WP3_W<'_>

Bit 2 - Wakeup pin WKUP3 polarity

pub fn wp2(&mut self) -> WP2_W<'_>

Bit 1 - Wakeup pin WKUP2 polarity

pub fn wp1(&mut self) -> WP1_W<'_>

Bit 0 - Wakeup pin WKUP1 polarity

impl W<u32, Reg<u32, _SCR>>

pub fn sbf(&mut self) -> SBF_W<'_>

Bit 8 - Clear standby flag

pub fn wuf5(&mut self) -> WUF5_W<'_>

Bit 4 - Clear wakeup flag 5

pub fn wuf4(&mut self) -> WUF4_W<'_>

Bit 3 - Clear wakeup flag 4

pub fn wuf3(&mut self) -> WUF3_W<'_>

Bit 2 - Clear wakeup flag 3

pub fn wuf2(&mut self) -> WUF2_W<'_>

Bit 1 - Clear wakeup flag 2

pub fn wuf1(&mut self) -> WUF1_W<'_>

Bit 0 - Clear wakeup flag 1

impl W<u32, Reg<u32, _PUCRA>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port A pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port A pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port A pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port A pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port A pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port A pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port A pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port A pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port A pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port A pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port A pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port A pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port A pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port A pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port A pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port A pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRA>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port A pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port A pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port A pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port A pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port A pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port A pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port A pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port A pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port A pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port A pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port A pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port A pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port A pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port A pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port A pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port A pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRB>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port B pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port B pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port B pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port B pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port B pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port B pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port B pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port B pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port B pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port B pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port B pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port B pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port B pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port B pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port B pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port B pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRB>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port B pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port B pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port B pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port B pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port B pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port B pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port B pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port B pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port B pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port B pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port B pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port B pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port B pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port B pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port B pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port B pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRC>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port C pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port C pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port C pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port C pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port C pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port C pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port C pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port C pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port C pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port C pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port C pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port C pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port C pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port C pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port C pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port C pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRC>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port C pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port C pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port C pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port C pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port C pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port C pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port C pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port C pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port C pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port C pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port C pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port C pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port C pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port C pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port C pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port C pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRD>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port D pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port D pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port D pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port D pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port D pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port D pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port D pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port D pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port D pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port D pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port D pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port D pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port D pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port D pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port D pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port D pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRD>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port D pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port D pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port D pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port D pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port D pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port D pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port D pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port D pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port D pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port D pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port D pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port D pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port D pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port D pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port D pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port D pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRE>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port E pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port E pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port E pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port E pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port E pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port E pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port E pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port E pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port E pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port E pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port E pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port E pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port E pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port E pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port E pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port E pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRE>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port E pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port E pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port E pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port E pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port E pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port E pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port E pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port E pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port E pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port E pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port E pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port E pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port E pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port E pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port E pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port E pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRF>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port F pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port F pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port F pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port F pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port F pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port F pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port F pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port F pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port F pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port F pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port F pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port F pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port F pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port F pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port F pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port F pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRF>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port F pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port F pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port F pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port F pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port F pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port F pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port F pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port F pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port F pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port F pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port F pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port F pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port F pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port F pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port F pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port F pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRG>>

pub fn pu15(&mut self) -> PU15_W<'_>

Bit 15 - Port G pull-up bit y (y=0..15)

pub fn pu14(&mut self) -> PU14_W<'_>

Bit 14 - Port G pull-up bit y (y=0..15)

pub fn pu13(&mut self) -> PU13_W<'_>

Bit 13 - Port G pull-up bit y (y=0..15)

pub fn pu12(&mut self) -> PU12_W<'_>

Bit 12 - Port G pull-up bit y (y=0..15)

pub fn pu11(&mut self) -> PU11_W<'_>

Bit 11 - Port G pull-up bit y (y=0..15)

pub fn pu10(&mut self) -> PU10_W<'_>

Bit 10 - Port G pull-up bit y (y=0..15)

pub fn pu9(&mut self) -> PU9_W<'_>

Bit 9 - Port G pull-up bit y (y=0..15)

pub fn pu8(&mut self) -> PU8_W<'_>

Bit 8 - Port G pull-up bit y (y=0..15)

pub fn pu7(&mut self) -> PU7_W<'_>

Bit 7 - Port G pull-up bit y (y=0..15)

pub fn pu6(&mut self) -> PU6_W<'_>

Bit 6 - Port G pull-up bit y (y=0..15)

pub fn pu5(&mut self) -> PU5_W<'_>

Bit 5 - Port G pull-up bit y (y=0..15)

pub fn pu4(&mut self) -> PU4_W<'_>

Bit 4 - Port G pull-up bit y (y=0..15)

pub fn pu3(&mut self) -> PU3_W<'_>

Bit 3 - Port G pull-up bit y (y=0..15)

pub fn pu2(&mut self) -> PU2_W<'_>

Bit 2 - Port G pull-up bit y (y=0..15)

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port G pull-up bit y (y=0..15)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port G pull-up bit y (y=0..15)

impl W<u32, Reg<u32, _PDCRG>>

pub fn pd15(&mut self) -> PD15_W<'_>

Bit 15 - Port G pull-down bit y (y=0..15)

pub fn pd14(&mut self) -> PD14_W<'_>

Bit 14 - Port G pull-down bit y (y=0..15)

pub fn pd13(&mut self) -> PD13_W<'_>

Bit 13 - Port G pull-down bit y (y=0..15)

pub fn pd12(&mut self) -> PD12_W<'_>

Bit 12 - Port G pull-down bit y (y=0..15)

pub fn pd11(&mut self) -> PD11_W<'_>

Bit 11 - Port G pull-down bit y (y=0..15)

pub fn pd10(&mut self) -> PD10_W<'_>

Bit 10 - Port G pull-down bit y (y=0..15)

pub fn pd9(&mut self) -> PD9_W<'_>

Bit 9 - Port G pull-down bit y (y=0..15)

pub fn pd8(&mut self) -> PD8_W<'_>

Bit 8 - Port G pull-down bit y (y=0..15)

pub fn pd7(&mut self) -> PD7_W<'_>

Bit 7 - Port G pull-down bit y (y=0..15)

pub fn pd6(&mut self) -> PD6_W<'_>

Bit 6 - Port G pull-down bit y (y=0..15)

pub fn pd5(&mut self) -> PD5_W<'_>

Bit 5 - Port G pull-down bit y (y=0..15)

pub fn pd4(&mut self) -> PD4_W<'_>

Bit 4 - Port G pull-down bit y (y=0..15)

pub fn pd3(&mut self) -> PD3_W<'_>

Bit 3 - Port G pull-down bit y (y=0..15)

pub fn pd2(&mut self) -> PD2_W<'_>

Bit 2 - Port G pull-down bit y (y=0..15)

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port G pull-down bit y (y=0..15)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port G pull-down bit y (y=0..15)

impl W<u32, Reg<u32, _PUCRH>>

pub fn pu1(&mut self) -> PU1_W<'_>

Bit 1 - Port H pull-up bit y (y=0..1)

pub fn pu0(&mut self) -> PU0_W<'_>

Bit 0 - Port H pull-up bit y (y=0..1)

impl W<u32, Reg<u32, _PDCRH>>

pub fn pd1(&mut self) -> PD1_W<'_>

Bit 1 - Port H pull-down bit y (y=0..1)

pub fn pd0(&mut self) -> PD0_W<'_>

Bit 0 - Port H pull-down bit y (y=0..1)

impl W<u32, Reg<u32, _MEMRMP>>

pub fn fb_mode(&mut self) -> FB_MODE_W<'_>

Bit 8 - Flash Bank mode selection

pub fn qfs(&mut self) -> QFS_W<'_>

Bit 3 - QUADSPI memory mapping swap

pub fn mem_mode(&mut self) -> MEM_MODE_W<'_>

Bits 0:2 - Memory mapping selection

impl W<u32, Reg<u32, _CFGR1>>

pub fn fpu_ie(&mut self) -> FPU_IE_W<'_>

Bits 26:31 - Floating Point Unit interrupts enable bits

pub fn i2c3_fmp(&mut self) -> I2C3_FMP_W<'_>

Bit 22 - I2C3 Fast-mode Plus driving capability activation

pub fn i2c2_fmp(&mut self) -> I2C2_FMP_W<'_>

Bit 21 - I2C2 Fast-mode Plus driving capability activation

pub fn i2c1_fmp(&mut self) -> I2C1_FMP_W<'_>

Bit 20 - I2C1 Fast-mode Plus driving capability activation

pub fn i2c_pb9_fmp(&mut self) -> I2C_PB9_FMP_W<'_>

Bit 19 - Fast-mode Plus (Fm+) driving capability activation on PB9

pub fn i2c_pb8_fmp(&mut self) -> I2C_PB8_FMP_W<'_>

Bit 18 - Fast-mode Plus (Fm+) driving capability activation on PB8

pub fn i2c_pb7_fmp(&mut self) -> I2C_PB7_FMP_W<'_>

Bit 17 - Fast-mode Plus (Fm+) driving capability activation on PB7

pub fn i2c_pb6_fmp(&mut self) -> I2C_PB6_FMP_W<'_>

Bit 16 - Fast-mode Plus (Fm+) driving capability activation on PB6

pub fn boosten(&mut self) -> BOOSTEN_W<'_>

Bit 8 - I/O analog switch voltage booster enable

pub fn fwdis(&mut self) -> FWDIS_W<'_>

Bit 0 - Firewall disable

impl W<u32, Reg<u32, _EXTICR1>>

pub fn exti3(&mut self) -> EXTI3_W<'_>

Bits 12:14 - EXTI 3 configuration bits

pub fn exti2(&mut self) -> EXTI2_W<'_>

Bits 8:10 - EXTI 2 configuration bits

pub fn exti1(&mut self) -> EXTI1_W<'_>

Bits 4:6 - EXTI 1 configuration bits

pub fn exti0(&mut self) -> EXTI0_W<'_>

Bits 0:2 - EXTI 0 configuration bits

impl W<u32, Reg<u32, _EXTICR2>>

pub fn exti7(&mut self) -> EXTI7_W<'_>

Bits 12:14 - EXTI 7 configuration bits

pub fn exti6(&mut self) -> EXTI6_W<'_>

Bits 8:10 - EXTI 6 configuration bits

pub fn exti5(&mut self) -> EXTI5_W<'_>

Bits 4:6 - EXTI 5 configuration bits

pub fn exti4(&mut self) -> EXTI4_W<'_>

Bits 0:2 - EXTI 4 configuration bits

impl W<u32, Reg<u32, _EXTICR3>>

pub fn exti11(&mut self) -> EXTI11_W<'_>

Bits 12:14 - EXTI 11 configuration bits

pub fn exti10(&mut self) -> EXTI10_W<'_>

Bits 8:10 - EXTI 10 configuration bits

pub fn exti9(&mut self) -> EXTI9_W<'_>

Bits 4:6 - EXTI 9 configuration bits

pub fn exti8(&mut self) -> EXTI8_W<'_>

Bits 0:2 - EXTI 8 configuration bits

impl W<u32, Reg<u32, _EXTICR4>>

pub fn exti15(&mut self) -> EXTI15_W<'_>

Bits 12:14 - EXTI15 configuration bits

pub fn exti14(&mut self) -> EXTI14_W<'_>

Bits 8:10 - EXTI14 configuration bits

pub fn exti13(&mut self) -> EXTI13_W<'_>

Bits 4:6 - EXTI13 configuration bits

pub fn exti12(&mut self) -> EXTI12_W<'_>

Bits 0:2 - EXTI12 configuration bits

impl W<u32, Reg<u32, _SCSR>>

pub fn sram2er(&mut self) -> SRAM2ER_W<'_>

Bit 0 - SRAM2 Erase

impl W<u32, Reg<u32, _CFGR2>>

pub fn spf(&mut self) -> SPF_W<'_>

Bit 8 - SRAM2 parity error flag

pub fn eccl(&mut self) -> ECCL_W<'_>

Bit 3 - ECC Lock

pub fn pvdl(&mut self) -> PVDL_W<'_>

Bit 2 - PVD lock enable bit

pub fn spl(&mut self) -> SPL_W<'_>

Bit 1 - SRAM2 parity lock bit

pub fn cll(&mut self) -> CLL_W<'_>

Bit 0 - Cortex LOCKUP (Hardfault) output enable bit

impl W<u32, Reg<u32, _SWPR>>

pub fn p31wp(&mut self) -> P31WP_W<'_>

Bit 31 - SRAM2 page 31 write protection

pub fn p30wp(&mut self) -> P30WP_W<'_>

Bit 30 - P30WP

pub fn p29wp(&mut self) -> P29WP_W<'_>

Bit 29 - P29WP

pub fn p28wp(&mut self) -> P28WP_W<'_>

Bit 28 - P28WP

pub fn p27wp(&mut self) -> P27WP_W<'_>

Bit 27 - P27WP

pub fn p26wp(&mut self) -> P26WP_W<'_>

Bit 26 - P26WP

pub fn p25wp(&mut self) -> P25WP_W<'_>

Bit 25 - P25WP

pub fn p24wp(&mut self) -> P24WP_W<'_>

Bit 24 - P24WP

pub fn p23wp(&mut self) -> P23WP_W<'_>

Bit 23 - P23WP

pub fn p22wp(&mut self) -> P22WP_W<'_>

Bit 22 - P22WP

pub fn p21wp(&mut self) -> P21WP_W<'_>

Bit 21 - P21WP

pub fn p20wp(&mut self) -> P20WP_W<'_>

Bit 20 - P20WP

pub fn p19wp(&mut self) -> P19WP_W<'_>

Bit 19 - P19WP

pub fn p18wp(&mut self) -> P18WP_W<'_>

Bit 18 - P18WP

pub fn p17wp(&mut self) -> P17WP_W<'_>

Bit 17 - P17WP

pub fn p16wp(&mut self) -> P16WP_W<'_>

Bit 16 - P16WP

pub fn p15wp(&mut self) -> P15WP_W<'_>

Bit 15 - P15WP

pub fn p14wp(&mut self) -> P14WP_W<'_>

Bit 14 - P14WP

pub fn p13wp(&mut self) -> P13WP_W<'_>

Bit 13 - P13WP

pub fn p12wp(&mut self) -> P12WP_W<'_>

Bit 12 - P12WP

pub fn p11wp(&mut self) -> P11WP_W<'_>

Bit 11 - P11WP

pub fn p10wp(&mut self) -> P10WP_W<'_>

Bit 10 - P10WP

pub fn p9wp(&mut self) -> P9WP_W<'_>

Bit 9 - P9WP

pub fn p8wp(&mut self) -> P8WP_W<'_>

Bit 8 - P8WP

pub fn p7wp(&mut self) -> P7WP_W<'_>

Bit 7 - P7WP

pub fn p6wp(&mut self) -> P6WP_W<'_>

Bit 6 - P6WP

pub fn p5wp(&mut self) -> P5WP_W<'_>

Bit 5 - P5WP

pub fn p4wp(&mut self) -> P4WP_W<'_>

Bit 4 - P4WP

pub fn p3wp(&mut self) -> P3WP_W<'_>

Bit 3 - P3WP

pub fn p2wp(&mut self) -> P2WP_W<'_>

Bit 2 - P2WP

pub fn p1wp(&mut self) -> P1WP_W<'_>

Bit 1 - P1WP

pub fn p0wp(&mut self) -> P0WP_W<'_>

Bit 0 - P0WP

impl W<u32, Reg<u32, _SKR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - SRAM2 write protection key for software erase

impl W<u32, Reg<u32, _CR>>

pub fn ie(&mut self) -> IE_W<'_>

Bit 3 - Interrupt enable

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 2 - Random number generator enable

impl W<u32, Reg<u32, _SR>>

pub fn seis(&mut self) -> SEIS_W<'_>

Bit 6 - Seed error interrupt status

pub fn ceis(&mut self) -> CEIS_W<'_>

Bit 5 - Clock error interrupt status

impl W<u32, Reg<u32, _CR>>

pub fn dmaouten(&mut self) -> DMAOUTEN_W<'_>

Bit 12 - Enable DMA management of data output phase

pub fn dmainen(&mut self) -> DMAINEN_W<'_>

Bit 11 - Enable DMA management of data input phase

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 10 - Error interrupt enable

pub fn ccfie(&mut self) -> CCFIE_W<'_>

Bit 9 - CCF flag interrupt enable

pub fn errc(&mut self) -> ERRC_W<'_>

Bit 8 - Error clear

pub fn ccfc(&mut self) -> CCFC_W<'_>

Bit 7 - Computation Complete Flag Clear

pub fn chmod(&mut self) -> CHMOD_W<'_>

Bits 5:6 - AES chaining mode

pub fn mode(&mut self) -> MODE_W<'_>

Bits 3:4 - AES operating mode

pub fn datatype(&mut self) -> DATATYPE_W<'_>

Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - AES enable

impl W<u32, Reg<u32, _DINR>>

pub fn aes_dinr(&mut self) -> AES_DINR_W<'_>

Bits 0:31 - Data Input Register

impl W<u32, Reg<u32, _KEYR0>>

pub fn aes_keyr0(&mut self) -> AES_KEYR0_W<'_>

Bits 0:31 - Data Output Register (LSB key [31:0])

impl W<u32, Reg<u32, _KEYR1>>

pub fn aes_keyr1(&mut self) -> AES_KEYR1_W<'_>

Bits 0:31 - AES key register (key [63:32])

impl W<u32, Reg<u32, _KEYR2>>

pub fn aes_keyr2(&mut self) -> AES_KEYR2_W<'_>

Bits 0:31 - AES key register (key [95:64])

impl W<u32, Reg<u32, _KEYR3>>

pub fn aes_keyr3(&mut self) -> AES_KEYR3_W<'_>

Bits 0:31 - AES key register (MSB key [127:96])

impl W<u32, Reg<u32, _IVR0>>

pub fn aes_ivr0(&mut self) -> AES_IVR0_W<'_>

Bits 0:31 - initialization vector register (LSB IVR [31:0])

impl W<u32, Reg<u32, _IVR1>>

pub fn aes_ivr1(&mut self) -> AES_IVR1_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [63:32])

impl W<u32, Reg<u32, _IVR2>>

pub fn aes_ivr2(&mut self) -> AES_IVR2_W<'_>

Bits 0:31 - Initialization Vector Register (IVR [95:64])

impl W<u32, Reg<u32, _IVR3>>

pub fn aes_ivr3(&mut self) -> AES_IVR3_W<'_>

Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])

impl W<u32, Reg<u32, _ISR>>

pub fn jqovf(&mut self) -> JQOVF_W<'_>

Bit 10 - JQOVF

pub fn awd3(&mut self) -> AWD3_W<'_>

Bit 9 - AWD3

pub fn awd2(&mut self) -> AWD2_W<'_>

Bit 8 - AWD2

pub fn awd1(&mut self) -> AWD1_W<'_>

Bit 7 - AWD1

pub fn jeos(&mut self) -> JEOS_W<'_>

Bit 6 - JEOS

pub fn jeoc(&mut self) -> JEOC_W<'_>

Bit 5 - JEOC

pub fn ovr(&mut self) -> OVR_W<'_>

Bit 4 - OVR

pub fn eos(&mut self) -> EOS_W<'_>

Bit 3 - EOS

pub fn eoc(&mut self) -> EOC_W<'_>

Bit 2 - EOC

pub fn eosmp(&mut self) -> EOSMP_W<'_>

Bit 1 - EOSMP

pub fn adrdy(&mut self) -> ADRDY_W<'_>

Bit 0 - ADRDY

impl W<u32, Reg<u32, _IER>>

pub fn jqovfie(&mut self) -> JQOVFIE_W<'_>

Bit 10 - JQOVFIE

pub fn awd3ie(&mut self) -> AWD3IE_W<'_>

Bit 9 - AWD3IE

pub fn awd2ie(&mut self) -> AWD2IE_W<'_>

Bit 8 - AWD2IE

pub fn awd1ie(&mut self) -> AWD1IE_W<'_>

Bit 7 - AWD1IE

pub fn jeosie(&mut self) -> JEOSIE_W<'_>

Bit 6 - JEOSIE

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 5 - JEOCIE

pub fn ovrie(&mut self) -> OVRIE_W<'_>

Bit 4 - OVRIE

pub fn eosie(&mut self) -> EOSIE_W<'_>

Bit 3 - EOSIE

pub fn eocie(&mut self) -> EOCIE_W<'_>

Bit 2 - EOCIE

pub fn eosmpie(&mut self) -> EOSMPIE_W<'_>

Bit 1 - EOSMPIE

pub fn adrdyie(&mut self) -> ADRDYIE_W<'_>

Bit 0 - ADRDYIE

impl W<u32, Reg<u32, _CR>>

pub fn adcal(&mut self) -> ADCAL_W<'_>

Bit 31 - ADCAL

pub fn adcaldif(&mut self) -> ADCALDIF_W<'_>

Bit 30 - ADCALDIF

pub fn deeppwd(&mut self) -> DEEPPWD_W<'_>

Bit 29 - DEEPPWD

pub fn advregen(&mut self) -> ADVREGEN_W<'_>

Bit 28 - ADVREGEN

pub fn jadstp(&mut self) -> JADSTP_W<'_>

Bit 5 - JADSTP

pub fn adstp(&mut self) -> ADSTP_W<'_>

Bit 4 - ADSTP

pub fn jadstart(&mut self) -> JADSTART_W<'_>

Bit 3 - JADSTART

pub fn adstart(&mut self) -> ADSTART_W<'_>

Bit 2 - ADSTART

pub fn addis(&mut self) -> ADDIS_W<'_>

Bit 1 - ADDIS

pub fn aden(&mut self) -> ADEN_W<'_>

Bit 0 - ADEN

impl W<u32, Reg<u32, _CFGR>>

pub fn awdch1ch(&mut self) -> AWDCH1CH_W<'_>

Bits 26:30 - AWDCH1CH

pub fn jauto(&mut self) -> JAUTO_W<'_>

Bit 25 - JAUTO

pub fn jawd1en(&mut self) -> JAWD1EN_W<'_>

Bit 24 - JAWD1EN

pub fn awd1en(&mut self) -> AWD1EN_W<'_>

Bit 23 - AWD1EN

pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>

Bit 22 - AWD1SGL

pub fn jqm(&mut self) -> JQM_W<'_>

Bit 21 - JQM

pub fn jdiscen(&mut self) -> JDISCEN_W<'_>

Bit 20 - JDISCEN

pub fn discnum(&mut self) -> DISCNUM_W<'_>

Bits 17:19 - DISCNUM

pub fn discen(&mut self) -> DISCEN_W<'_>

Bit 16 - DISCEN

pub fn autoff(&mut self) -> AUTOFF_W<'_>

Bit 15 - AUTOFF

pub fn autdly(&mut self) -> AUTDLY_W<'_>

Bit 14 - AUTDLY

pub fn cont(&mut self) -> CONT_W<'_>

Bit 13 - CONT

pub fn ovrmod(&mut self) -> OVRMOD_W<'_>

Bit 12 - OVRMOD

pub fn exten(&mut self) -> EXTEN_W<'_>

Bits 10:11 - EXTEN

pub fn extsel(&mut self) -> EXTSEL_W<'_>

Bits 6:9 - EXTSEL

pub fn align(&mut self) -> ALIGN_W<'_>

Bit 5 - ALIGN

pub fn res(&mut self) -> RES_W<'_>

Bits 3:4 - RES

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 1 - DMACFG

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 0 - DMAEN

impl W<u32, Reg<u32, _CFGR2>>

pub fn rovsm(&mut self) -> ROVSM_W<'_>

Bit 10 - EXTEN

pub fn tovs(&mut self) -> TOVS_W<'_>

Bit 9 - EXTSEL

pub fn ovss(&mut self) -> OVSS_W<'_>

Bits 5:8 - ALIGN

pub fn ovsr(&mut self) -> OVSR_W<'_>

Bits 2:4 - RES

pub fn jovse(&mut self) -> JOVSE_W<'_>

Bit 1 - DMACFG

pub fn rovse(&mut self) -> ROVSE_W<'_>

Bit 0 - DMAEN

impl W<u32, Reg<u32, _SMPR1>>

pub fn smp9(&mut self) -> SMP9_W<'_>

Bits 27:29 - Channel 9 sampling time selection

pub fn smp8(&mut self) -> SMP8_W<'_>

Bits 24:26 - Channel 8 sampling time selection

pub fn smp7(&mut self) -> SMP7_W<'_>

Bits 21:23 - Channel 7 sampling time selection

pub fn smp6(&mut self) -> SMP6_W<'_>

Bits 18:20 - Channel 6 sampling time selection

pub fn smp5(&mut self) -> SMP5_W<'_>

Bits 15:17 - Channel 5 sampling time selection

pub fn smp4(&mut self) -> SMP4_W<'_>

Bits 12:14 - Channel 4 sampling time selection

pub fn smp3(&mut self) -> SMP3_W<'_>

Bits 9:11 - Channel 3 sampling time selection

pub fn smp2(&mut self) -> SMP2_W<'_>

Bits 6:8 - Channel 2 sampling time selection

pub fn smp1(&mut self) -> SMP1_W<'_>

Bits 3:5 - Channel 1 sampling time selection

pub fn smp0(&mut self) -> SMP0_W<'_>

Bits 0:2 - Channel 0 sampling time selection

impl W<u32, Reg<u32, _SMPR2>>

pub fn smp18(&mut self) -> SMP18_W<'_>

Bits 24:26 - Channel 18 sampling time selection

pub fn smp17(&mut self) -> SMP17_W<'_>

Bits 21:23 - Channel 17 sampling time selection

pub fn smp16(&mut self) -> SMP16_W<'_>

Bits 18:20 - Channel 16 sampling time selection

pub fn smp15(&mut self) -> SMP15_W<'_>

Bits 15:17 - Channel 15 sampling time selection

pub fn smp14(&mut self) -> SMP14_W<'_>

Bits 12:14 - Channel 14 sampling time selection

pub fn smp13(&mut self) -> SMP13_W<'_>

Bits 9:11 - Channel 13 sampling time selection

pub fn smp12(&mut self) -> SMP12_W<'_>

Bits 6:8 - Channel 12 sampling time selection

pub fn smp11(&mut self) -> SMP11_W<'_>

Bits 3:5 - Channel 11 sampling time selection

pub fn smp10(&mut self) -> SMP10_W<'_>

Bits 0:2 - Channel 10 sampling time selection

impl W<u32, Reg<u32, _TR1>>

pub fn ht1(&mut self) -> HT1_W<'_>

Bits 16:27 - HT1

pub fn lt1(&mut self) -> LT1_W<'_>

Bits 0:11 - LT1

impl W<u32, Reg<u32, _TR2>>

pub fn ht2(&mut self) -> HT2_W<'_>

Bits 16:23 - HT2

pub fn lt2(&mut self) -> LT2_W<'_>

Bits 0:7 - LT2

impl W<u32, Reg<u32, _TR3>>

pub fn ht3(&mut self) -> HT3_W<'_>

Bits 16:23 - HT3

pub fn lt3(&mut self) -> LT3_W<'_>

Bits 0:7 - LT3

impl W<u32, Reg<u32, _SQR1>>

pub fn sq4(&mut self) -> SQ4_W<'_>

Bits 24:28 - SQ4

pub fn sq3(&mut self) -> SQ3_W<'_>

Bits 18:22 - SQ3

pub fn sq2(&mut self) -> SQ2_W<'_>

Bits 12:16 - SQ2

pub fn sq1(&mut self) -> SQ1_W<'_>

Bits 6:10 - SQ1

pub fn l(&mut self) -> L_W<'_>

Bits 0:3 - Regular channel sequence length

impl W<u32, Reg<u32, _SQR2>>

pub fn sq9(&mut self) -> SQ9_W<'_>

Bits 24:28 - SQ9

pub fn sq8(&mut self) -> SQ8_W<'_>

Bits 18:22 - SQ8

pub fn sq7(&mut self) -> SQ7_W<'_>

Bits 12:16 - SQ7

pub fn sq6(&mut self) -> SQ6_W<'_>

Bits 6:10 - SQ6

pub fn sq5(&mut self) -> SQ5_W<'_>

Bits 0:4 - SQ5

impl W<u32, Reg<u32, _SQR3>>

pub fn sq14(&mut self) -> SQ14_W<'_>

Bits 24:28 - SQ14

pub fn sq13(&mut self) -> SQ13_W<'_>

Bits 18:22 - SQ13

pub fn sq12(&mut self) -> SQ12_W<'_>

Bits 12:16 - SQ12

pub fn sq11(&mut self) -> SQ11_W<'_>

Bits 6:10 - SQ11

pub fn sq10(&mut self) -> SQ10_W<'_>

Bits 0:4 - SQ10

impl W<u32, Reg<u32, _SQR4>>

pub fn sq16(&mut self) -> SQ16_W<'_>

Bits 6:10 - SQ16

pub fn sq15(&mut self) -> SQ15_W<'_>

Bits 0:4 - SQ15

impl W<u32, Reg<u32, _JSQR>>

pub fn jsq4(&mut self) -> JSQ4_W<'_>

Bits 26:30 - JSQ4

pub fn jsq3(&mut self) -> JSQ3_W<'_>

Bits 20:24 - JSQ3

pub fn jsq2(&mut self) -> JSQ2_W<'_>

Bits 14:18 - JSQ2

pub fn jsq1(&mut self) -> JSQ1_W<'_>

Bits 8:12 - JSQ1

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 6:7 - JEXTEN

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 2:5 - JEXTSEL

pub fn jl(&mut self) -> JL_W<'_>

Bits 0:1 - JL

impl W<u32, Reg<u32, _OFR1>>

pub fn offset1_en(&mut self) -> OFFSET1_EN_W<'_>

Bit 31 - OFFSET1_EN

pub fn offset1_ch(&mut self) -> OFFSET1_CH_W<'_>

Bits 26:30 - OFFSET1_CH

pub fn offset1(&mut self) -> OFFSET1_W<'_>

Bits 0:11 - OFFSET1

impl W<u32, Reg<u32, _OFR2>>

pub fn offset2_en(&mut self) -> OFFSET2_EN_W<'_>

Bit 31 - OFFSET2_EN

pub fn offset2_ch(&mut self) -> OFFSET2_CH_W<'_>

Bits 26:30 - OFFSET2_CH

pub fn offset2(&mut self) -> OFFSET2_W<'_>

Bits 0:11 - OFFSET2

impl W<u32, Reg<u32, _OFR3>>

pub fn offset3_en(&mut self) -> OFFSET3_EN_W<'_>

Bit 31 - OFFSET3_EN

pub fn offset3_ch(&mut self) -> OFFSET3_CH_W<'_>

Bits 26:30 - OFFSET3_CH

pub fn offset3(&mut self) -> OFFSET3_W<'_>

Bits 0:11 - OFFSET3

impl W<u32, Reg<u32, _OFR4>>

pub fn offset4_en(&mut self) -> OFFSET4_EN_W<'_>

Bit 31 - OFFSET4_EN

pub fn offset4_ch(&mut self) -> OFFSET4_CH_W<'_>

Bits 26:30 - OFFSET4_CH

pub fn offset4(&mut self) -> OFFSET4_W<'_>

Bits 0:11 - OFFSET4

impl W<u32, Reg<u32, _AWD2CR>>

pub fn awd2ch(&mut self) -> AWD2CH_W<'_>

Bits 1:18 - AWD2CH

impl W<u32, Reg<u32, _AWD3CR>>

pub fn awd3ch(&mut self) -> AWD3CH_W<'_>

Bits 1:18 - AWD3CH

impl W<u32, Reg<u32, _DIFSEL>>

pub fn difsel_1_15(&mut self) -> DIFSEL_1_15_W<'_>

Bits 1:15 - Differential mode for channels 15 to 1

impl W<u32, Reg<u32, _CALFACT>>

pub fn calfact_d(&mut self) -> CALFACT_D_W<'_>

Bits 16:22 - CALFACT_D

pub fn calfact_s(&mut self) -> CALFACT_S_W<'_>

Bits 0:6 - CALFACT_S

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _MODER>>

pub fn moder15(&mut self) -> MODER15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn moder14(&mut self) -> MODER14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn moder13(&mut self) -> MODER13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn moder12(&mut self) -> MODER12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn moder11(&mut self) -> MODER11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn moder10(&mut self) -> MODER10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn moder9(&mut self) -> MODER9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn moder8(&mut self) -> MODER8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn moder7(&mut self) -> MODER7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn moder6(&mut self) -> MODER6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn moder5(&mut self) -> MODER5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn moder4(&mut self) -> MODER4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn moder3(&mut self) -> MODER3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn moder2(&mut self) -> MODER2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn moder1(&mut self) -> MODER1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn moder0(&mut self) -> MODER0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OTYPER>>

pub fn ot15(&mut self) -> OT15_W<'_>

Bit 15 - Port x configuration bits (y = 0..15)

pub fn ot14(&mut self) -> OT14_W<'_>

Bit 14 - Port x configuration bits (y = 0..15)

pub fn ot13(&mut self) -> OT13_W<'_>

Bit 13 - Port x configuration bits (y = 0..15)

pub fn ot12(&mut self) -> OT12_W<'_>

Bit 12 - Port x configuration bits (y = 0..15)

pub fn ot11(&mut self) -> OT11_W<'_>

Bit 11 - Port x configuration bits (y = 0..15)

pub fn ot10(&mut self) -> OT10_W<'_>

Bit 10 - Port x configuration bits (y = 0..15)

pub fn ot9(&mut self) -> OT9_W<'_>

Bit 9 - Port x configuration bits (y = 0..15)

pub fn ot8(&mut self) -> OT8_W<'_>

Bit 8 - Port x configuration bits (y = 0..15)

pub fn ot7(&mut self) -> OT7_W<'_>

Bit 7 - Port x configuration bits (y = 0..15)

pub fn ot6(&mut self) -> OT6_W<'_>

Bit 6 - Port x configuration bits (y = 0..15)

pub fn ot5(&mut self) -> OT5_W<'_>

Bit 5 - Port x configuration bits (y = 0..15)

pub fn ot4(&mut self) -> OT4_W<'_>

Bit 4 - Port x configuration bits (y = 0..15)

pub fn ot3(&mut self) -> OT3_W<'_>

Bit 3 - Port x configuration bits (y = 0..15)

pub fn ot2(&mut self) -> OT2_W<'_>

Bit 2 - Port x configuration bits (y = 0..15)

pub fn ot1(&mut self) -> OT1_W<'_>

Bit 1 - Port x configuration bits (y = 0..15)

pub fn ot0(&mut self) -> OT0_W<'_>

Bit 0 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _OSPEEDR>>

pub fn ospeedr15(&mut self) -> OSPEEDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn ospeedr14(&mut self) -> OSPEEDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn ospeedr13(&mut self) -> OSPEEDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn ospeedr12(&mut self) -> OSPEEDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn ospeedr11(&mut self) -> OSPEEDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn ospeedr10(&mut self) -> OSPEEDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn ospeedr9(&mut self) -> OSPEEDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn ospeedr8(&mut self) -> OSPEEDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn ospeedr7(&mut self) -> OSPEEDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn ospeedr6(&mut self) -> OSPEEDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn ospeedr5(&mut self) -> OSPEEDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn ospeedr4(&mut self) -> OSPEEDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn ospeedr3(&mut self) -> OSPEEDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn ospeedr2(&mut self) -> OSPEEDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn ospeedr1(&mut self) -> OSPEEDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn ospeedr0(&mut self) -> OSPEEDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _PUPDR>>

pub fn pupdr15(&mut self) -> PUPDR15_W<'_>

Bits 30:31 - Port x configuration bits (y = 0..15)

pub fn pupdr14(&mut self) -> PUPDR14_W<'_>

Bits 28:29 - Port x configuration bits (y = 0..15)

pub fn pupdr13(&mut self) -> PUPDR13_W<'_>

Bits 26:27 - Port x configuration bits (y = 0..15)

pub fn pupdr12(&mut self) -> PUPDR12_W<'_>

Bits 24:25 - Port x configuration bits (y = 0..15)

pub fn pupdr11(&mut self) -> PUPDR11_W<'_>

Bits 22:23 - Port x configuration bits (y = 0..15)

pub fn pupdr10(&mut self) -> PUPDR10_W<'_>

Bits 20:21 - Port x configuration bits (y = 0..15)

pub fn pupdr9(&mut self) -> PUPDR9_W<'_>

Bits 18:19 - Port x configuration bits (y = 0..15)

pub fn pupdr8(&mut self) -> PUPDR8_W<'_>

Bits 16:17 - Port x configuration bits (y = 0..15)

pub fn pupdr7(&mut self) -> PUPDR7_W<'_>

Bits 14:15 - Port x configuration bits (y = 0..15)

pub fn pupdr6(&mut self) -> PUPDR6_W<'_>

Bits 12:13 - Port x configuration bits (y = 0..15)

pub fn pupdr5(&mut self) -> PUPDR5_W<'_>

Bits 10:11 - Port x configuration bits (y = 0..15)

pub fn pupdr4(&mut self) -> PUPDR4_W<'_>

Bits 8:9 - Port x configuration bits (y = 0..15)

pub fn pupdr3(&mut self) -> PUPDR3_W<'_>

Bits 6:7 - Port x configuration bits (y = 0..15)

pub fn pupdr2(&mut self) -> PUPDR2_W<'_>

Bits 4:5 - Port x configuration bits (y = 0..15)

pub fn pupdr1(&mut self) -> PUPDR1_W<'_>

Bits 2:3 - Port x configuration bits (y = 0..15)

pub fn pupdr0(&mut self) -> PUPDR0_W<'_>

Bits 0:1 - Port x configuration bits (y = 0..15)

impl W<u32, Reg<u32, _ODR>>

pub fn odr15(&mut self) -> ODR15_W<'_>

Bit 15 - Port output data (y = 0..15)

pub fn odr14(&mut self) -> ODR14_W<'_>

Bit 14 - Port output data (y = 0..15)

pub fn odr13(&mut self) -> ODR13_W<'_>

Bit 13 - Port output data (y = 0..15)

pub fn odr12(&mut self) -> ODR12_W<'_>

Bit 12 - Port output data (y = 0..15)

pub fn odr11(&mut self) -> ODR11_W<'_>

Bit 11 - Port output data (y = 0..15)

pub fn odr10(&mut self) -> ODR10_W<'_>

Bit 10 - Port output data (y = 0..15)

pub fn odr9(&mut self) -> ODR9_W<'_>

Bit 9 - Port output data (y = 0..15)

pub fn odr8(&mut self) -> ODR8_W<'_>

Bit 8 - Port output data (y = 0..15)

pub fn odr7(&mut self) -> ODR7_W<'_>

Bit 7 - Port output data (y = 0..15)

pub fn odr6(&mut self) -> ODR6_W<'_>

Bit 6 - Port output data (y = 0..15)

pub fn odr5(&mut self) -> ODR5_W<'_>

Bit 5 - Port output data (y = 0..15)

pub fn odr4(&mut self) -> ODR4_W<'_>

Bit 4 - Port output data (y = 0..15)

pub fn odr3(&mut self) -> ODR3_W<'_>

Bit 3 - Port output data (y = 0..15)

pub fn odr2(&mut self) -> ODR2_W<'_>

Bit 2 - Port output data (y = 0..15)

pub fn odr1(&mut self) -> ODR1_W<'_>

Bit 1 - Port output data (y = 0..15)

pub fn odr0(&mut self) -> ODR0_W<'_>

Bit 0 - Port output data (y = 0..15)

impl W<u32, Reg<u32, _BSRR>>

pub fn br15(&mut self) -> BR15_W<'_>

Bit 31 - Port x reset bit y (y = 0..15)

pub fn br14(&mut self) -> BR14_W<'_>

Bit 30 - Port x reset bit y (y = 0..15)

pub fn br13(&mut self) -> BR13_W<'_>

Bit 29 - Port x reset bit y (y = 0..15)

pub fn br12(&mut self) -> BR12_W<'_>

Bit 28 - Port x reset bit y (y = 0..15)

pub fn br11(&mut self) -> BR11_W<'_>

Bit 27 - Port x reset bit y (y = 0..15)

pub fn br10(&mut self) -> BR10_W<'_>

Bit 26 - Port x reset bit y (y = 0..15)

pub fn br9(&mut self) -> BR9_W<'_>

Bit 25 - Port x reset bit y (y = 0..15)

pub fn br8(&mut self) -> BR8_W<'_>

Bit 24 - Port x reset bit y (y = 0..15)

pub fn br7(&mut self) -> BR7_W<'_>

Bit 23 - Port x reset bit y (y = 0..15)

pub fn br6(&mut self) -> BR6_W<'_>

Bit 22 - Port x reset bit y (y = 0..15)

pub fn br5(&mut self) -> BR5_W<'_>

Bit 21 - Port x reset bit y (y = 0..15)

pub fn br4(&mut self) -> BR4_W<'_>

Bit 20 - Port x reset bit y (y = 0..15)

pub fn br3(&mut self) -> BR3_W<'_>

Bit 19 - Port x reset bit y (y = 0..15)

pub fn br2(&mut self) -> BR2_W<'_>

Bit 18 - Port x reset bit y (y = 0..15)

pub fn br1(&mut self) -> BR1_W<'_>

Bit 17 - Port x reset bit y (y = 0..15)

pub fn br0(&mut self) -> BR0_W<'_>

Bit 16 - Port x set bit y (y= 0..15)

pub fn bs15(&mut self) -> BS15_W<'_>

Bit 15 - Port x set bit y (y= 0..15)

pub fn bs14(&mut self) -> BS14_W<'_>

Bit 14 - Port x set bit y (y= 0..15)

pub fn bs13(&mut self) -> BS13_W<'_>

Bit 13 - Port x set bit y (y= 0..15)

pub fn bs12(&mut self) -> BS12_W<'_>

Bit 12 - Port x set bit y (y= 0..15)

pub fn bs11(&mut self) -> BS11_W<'_>

Bit 11 - Port x set bit y (y= 0..15)

pub fn bs10(&mut self) -> BS10_W<'_>

Bit 10 - Port x set bit y (y= 0..15)

pub fn bs9(&mut self) -> BS9_W<'_>

Bit 9 - Port x set bit y (y= 0..15)

pub fn bs8(&mut self) -> BS8_W<'_>

Bit 8 - Port x set bit y (y= 0..15)

pub fn bs7(&mut self) -> BS7_W<'_>

Bit 7 - Port x set bit y (y= 0..15)

pub fn bs6(&mut self) -> BS6_W<'_>

Bit 6 - Port x set bit y (y= 0..15)

pub fn bs5(&mut self) -> BS5_W<'_>

Bit 5 - Port x set bit y (y= 0..15)

pub fn bs4(&mut self) -> BS4_W<'_>

Bit 4 - Port x set bit y (y= 0..15)

pub fn bs3(&mut self) -> BS3_W<'_>

Bit 3 - Port x set bit y (y= 0..15)

pub fn bs2(&mut self) -> BS2_W<'_>

Bit 2 - Port x set bit y (y= 0..15)

pub fn bs1(&mut self) -> BS1_W<'_>

Bit 1 - Port x set bit y (y= 0..15)

pub fn bs0(&mut self) -> BS0_W<'_>

Bit 0 - Port x set bit y (y= 0..15)

impl W<u32, Reg<u32, _LCKR>>

pub fn lckk(&mut self) -> LCKK_W<'_>

Bit 16 - Port x lock bit y (y= 0..15)

pub fn lck15(&mut self) -> LCK15_W<'_>

Bit 15 - Port x lock bit y (y= 0..15)

pub fn lck14(&mut self) -> LCK14_W<'_>

Bit 14 - Port x lock bit y (y= 0..15)

pub fn lck13(&mut self) -> LCK13_W<'_>

Bit 13 - Port x lock bit y (y= 0..15)

pub fn lck12(&mut self) -> LCK12_W<'_>

Bit 12 - Port x lock bit y (y= 0..15)

pub fn lck11(&mut self) -> LCK11_W<'_>

Bit 11 - Port x lock bit y (y= 0..15)

pub fn lck10(&mut self) -> LCK10_W<'_>

Bit 10 - Port x lock bit y (y= 0..15)

pub fn lck9(&mut self) -> LCK9_W<'_>

Bit 9 - Port x lock bit y (y= 0..15)

pub fn lck8(&mut self) -> LCK8_W<'_>

Bit 8 - Port x lock bit y (y= 0..15)

pub fn lck7(&mut self) -> LCK7_W<'_>

Bit 7 - Port x lock bit y (y= 0..15)

pub fn lck6(&mut self) -> LCK6_W<'_>

Bit 6 - Port x lock bit y (y= 0..15)

pub fn lck5(&mut self) -> LCK5_W<'_>

Bit 5 - Port x lock bit y (y= 0..15)

pub fn lck4(&mut self) -> LCK4_W<'_>

Bit 4 - Port x lock bit y (y= 0..15)

pub fn lck3(&mut self) -> LCK3_W<'_>

Bit 3 - Port x lock bit y (y= 0..15)

pub fn lck2(&mut self) -> LCK2_W<'_>

Bit 2 - Port x lock bit y (y= 0..15)

pub fn lck1(&mut self) -> LCK1_W<'_>

Bit 1 - Port x lock bit y (y= 0..15)

pub fn lck0(&mut self) -> LCK0_W<'_>

Bit 0 - Port x lock bit y (y= 0..15)

impl W<u32, Reg<u32, _AFRL>>

pub fn afrl7(&mut self) -> AFRL7_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl6(&mut self) -> AFRL6_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl5(&mut self) -> AFRL5_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl4(&mut self) -> AFRL4_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl3(&mut self) -> AFRL3_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl2(&mut self) -> AFRL2_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl1(&mut self) -> AFRL1_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)

pub fn afrl0(&mut self) -> AFRL0_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)

impl W<u32, Reg<u32, _AFRH>>

pub fn afrh15(&mut self) -> AFRH15_W<'_>

Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh14(&mut self) -> AFRH14_W<'_>

Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh13(&mut self) -> AFRH13_W<'_>

Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh12(&mut self) -> AFRH12_W<'_>

Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh11(&mut self) -> AFRH11_W<'_>

Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh10(&mut self) -> AFRH10_W<'_>

Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh9(&mut self) -> AFRH9_W<'_>

Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)

pub fn afrh8(&mut self) -> AFRH8_W<'_>

Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)

impl W<u32, Reg<u32, _CR1>>

pub fn mckdiv(&mut self) -> MCKDIV_W<'_>

Bits 20:23 - Master clock divider

pub fn nodiv(&mut self) -> NODIV_W<'_>

Bit 19 - No divider

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 17 - DMA enable

pub fn saien(&mut self) -> SAIEN_W<'_>

Bit 16 - Audio block A enable

pub fn outdriv(&mut self) -> OUTDRIV_W<'_>

Bit 13 - Output drive

pub fn mono(&mut self) -> MONO_W<'_>

Bit 12 - Mono mode

pub fn syncen(&mut self) -> SYNCEN_W<'_>

Bits 10:11 - Synchronization enable

pub fn ckstr(&mut self) -> CKSTR_W<'_>

Bit 9 - Clock strobing edge

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 8 - Least significant bit first

pub fn ds(&mut self) -> DS_W<'_>

Bits 5:7 - Data size

pub fn prtcfg(&mut self) -> PRTCFG_W<'_>

Bits 2:3 - Protocol configuration

pub fn mode(&mut self) -> MODE_W<'_>

Bits 0:1 - Audio block mode

impl W<u32, Reg<u32, _CR2>>

pub fn comp(&mut self) -> COMP_W<'_>

Bits 14:15 - Companding mode

pub fn cpl(&mut self) -> CPL_W<'_>

Bit 13 - Complement bit

pub fn mutecn(&mut self) -> MUTECN_W<'_>

Bits 7:12 - Mute counter

pub fn muteval(&mut self) -> MUTEVAL_W<'_>

Bit 6 - Mute value

pub fn mute(&mut self) -> MUTE_W<'_>

Bit 5 - Mute

pub fn tris(&mut self) -> TRIS_W<'_>

Bit 4 - Tristate management on data line

pub fn fflush(&mut self) -> FFLUSH_W<'_>

Bit 3 - FIFO flush

pub fn fth(&mut self) -> FTH_W<'_>

Bits 0:2 - FIFO threshold

impl W<u32, Reg<u32, _FRCR>>

pub fn fsoff(&mut self) -> FSOFF_W<'_>

Bit 18 - Frame synchronization offset

pub fn fspol(&mut self) -> FSPOL_W<'_>

Bit 17 - Frame synchronization polarity

pub fn fsdef(&mut self) -> FSDEF_W<'_>

Bit 16 - Frame synchronization definition

pub fn fsall(&mut self) -> FSALL_W<'_>

Bits 8:14 - Frame synchronization active level length

pub fn frl(&mut self) -> FRL_W<'_>

Bits 0:7 - Frame length

impl W<u32, Reg<u32, _SLOTR>>

pub fn sloten(&mut self) -> SLOTEN_W<'_>

Bits 16:31 - Slot enable

pub fn nbslot(&mut self) -> NBSLOT_W<'_>

Bits 8:11 - Number of slots in an audio frame

pub fn slotsz(&mut self) -> SLOTSZ_W<'_>

Bits 6:7 - Slot size

pub fn fboff(&mut self) -> FBOFF_W<'_>

Bits 0:4 - First bit offset

impl W<u32, Reg<u32, _IM>>

pub fn lfsdetie(&mut self) -> LFSDETIE_W<'_>

Bit 6 - Late frame synchronization detection interrupt enable

pub fn afsdetie(&mut self) -> AFSDETIE_W<'_>

Bit 5 - Anticipated frame synchronization detection interrupt enable

pub fn cnrdyie(&mut self) -> CNRDYIE_W<'_>

Bit 4 - Codec not ready interrupt enable

pub fn freqie(&mut self) -> FREQIE_W<'_>

Bit 3 - FIFO request interrupt enable

pub fn wckcfgie(&mut self) -> WCKCFGIE_W<'_>

Bit 2 - Wrong clock configuration interrupt enable

pub fn mutedetie(&mut self) -> MUTEDETIE_W<'_>

Bit 1 - Mute detection interrupt enable

pub fn ovrudrie(&mut self) -> OVRUDRIE_W<'_>

Bit 0 - Overrun/underrun interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn flvl(&mut self) -> FLVL_W<'_>

Bits 16:18 - FIFO level threshold

pub fn lfsdet(&mut self) -> LFSDET_W<'_>

Bit 6 - Late frame synchronization detection

pub fn afsdet(&mut self) -> AFSDET_W<'_>

Bit 5 - Anticipated frame synchronization detection

pub fn cnrdy(&mut self) -> CNRDY_W<'_>

Bit 4 - Codec not ready

pub fn freq(&mut self) -> FREQ_W<'_>

Bit 3 - FIFO request

pub fn wckcfg(&mut self) -> WCKCFG_W<'_>

Bit 2 - Wrong clock configuration flag. This bit is read only

pub fn mutedet(&mut self) -> MUTEDET_W<'_>

Bit 1 - Mute detection

pub fn ovrudr(&mut self) -> OVRUDR_W<'_>

Bit 0 - Overrun / underrun

impl W<u32, Reg<u32, _CLRFR>>

pub fn clfsdet(&mut self) -> CLFSDET_W<'_>

Bit 6 - Clear late frame synchronization detection flag

pub fn cafsdet(&mut self) -> CAFSDET_W<'_>

Bit 5 - Clear anticipated frame synchronization detection flag

pub fn ccnrdy(&mut self) -> CCNRDY_W<'_>

Bit 4 - Clear codec not ready flag

pub fn cwckcfg(&mut self) -> CWCKCFG_W<'_>

Bit 2 - Clear wrong clock configuration flag

pub fn cmutedet(&mut self) -> CMUTEDET_W<'_>

Bit 1 - Mute detection flag

pub fn covrudr(&mut self) -> COVRUDR_W<'_>

Bit 0 - Clear overrun / underrun

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:31 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:31 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:31 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn etr_rmp(&mut self) -> ETR_RMP_W<'_>

Bits 0:2 - Timer2 ETR remap

pub fn ti4_rmp(&mut self) -> TI4_RMP_W<'_>

Bits 3:4 - Internal trigger

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _CR1>>

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn uifremap(&mut self) -> UIFREMAP_W<'_>

Bit 11 - UIF status bit remapping

impl W<u32, Reg<u32, _CR2>>

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc1m_2(&mut self) -> OC1M_2_W<'_>

Bit 16 - Output Compare 1 mode

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR1>>

pub fn ccr1(&mut self) -> CCR1_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn bkf(&mut self) -> BKF_W<'_>

Bits 16:19 - Break filter

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn ti1_rmp(&mut self) -> TI1_RMP_W<'_>

Bits 0:1 - Input capture 1 remap

impl W<u32, Reg<u32, _OR2>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk1e(&mut self) -> BKDFBK1E_W<'_>

Bit 8 - BRK DFSDM_BREAK1 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarit

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn etr_adc1_rmp(&mut self) -> ETR_ADC1_RMP_W<'_>

Bits 0:1 - External trigger remap on ADC1 analog watchdog

pub fn etr_adc3_rmp(&mut self) -> ETR_ADC3_RMP_W<'_>

Bits 2:3 - External trigger remap on ADC3 analog watchdog

pub fn ti1_rmp(&mut self) -> TI1_RMP_W<'_>

Bit 4 - Input Capture 1 remap

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&mut self) -> OC6M_BIT3_W<'_>

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&mut self) -> OC5M_BIT3_W<'_>

Bits 16:18 - Output Compare 5 mode bit 3

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _OR2>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk0e(&mut self) -> BKDFBK0E_W<'_>

Bit 8 - BRK DFSDM_BREAK0 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _OR3>>

pub fn bk2ine(&mut self) -> BK2INE_W<'_>

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W<'_>

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W<'_>

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk0e(&mut self) -> BK2DFBK0E_W<'_>

Bit 8 - BRK2 DFSDM_BREAK0 enable

pub fn bk2inp(&mut self) -> BK2INP_W<'_>

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W<'_>

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W<'_>

Bit 11 - BRK2 COMP2 input polarity

impl W<u32, Reg<u32, _CR1>>

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Low counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Low Auto-reload value

impl W<u32, Reg<u32, _ICR>>

pub fn downcf(&mut self) -> DOWNCF_W<'_>

Bit 6 - Direction change to down Clear Flag

pub fn upcf(&mut self) -> UPCF_W<'_>

Bit 5 - Direction change to UP Clear Flag

pub fn arrokcf(&mut self) -> ARROKCF_W<'_>

Bit 4 - Autoreload register update OK Clear Flag

pub fn cmpokcf(&mut self) -> CMPOKCF_W<'_>

Bit 3 - Compare register update OK Clear Flag

pub fn exttrigcf(&mut self) -> EXTTRIGCF_W<'_>

Bit 2 - External trigger valid edge Clear Flag

pub fn arrmcf(&mut self) -> ARRMCF_W<'_>

Bit 1 - Autoreload match Clear Flag

pub fn cmpmcf(&mut self) -> CMPMCF_W<'_>

Bit 0 - compare match Clear Flag

impl W<u32, Reg<u32, _IER>>

pub fn downie(&mut self) -> DOWNIE_W<'_>

Bit 6 - Direction change to down Interrupt Enable

pub fn upie(&mut self) -> UPIE_W<'_>

Bit 5 - Direction change to UP Interrupt Enable

pub fn arrokie(&mut self) -> ARROKIE_W<'_>

Bit 4 - Autoreload register update OK Interrupt Enable

pub fn cmpokie(&mut self) -> CMPOKIE_W<'_>

Bit 3 - Compare register update OK Interrupt Enable

pub fn exttrigie(&mut self) -> EXTTRIGIE_W<'_>

Bit 2 - External trigger valid edge Interrupt Enable

pub fn arrmie(&mut self) -> ARRMIE_W<'_>

Bit 1 - Autoreload match Interrupt Enable

pub fn cmpmie(&mut self) -> CMPMIE_W<'_>

Bit 0 - Compare match Interrupt Enable

impl W<u32, Reg<u32, _CFGR>>

pub fn enc(&mut self) -> ENC_W<'_>

Bit 24 - Encoder mode enable

pub fn countmode(&mut self) -> COUNTMODE_W<'_>

Bit 23 - counter mode enabled

pub fn preload(&mut self) -> PRELOAD_W<'_>

Bit 22 - Registers update mode

pub fn wavpol(&mut self) -> WAVPOL_W<'_>

Bit 21 - Waveform shape polarity

pub fn wave(&mut self) -> WAVE_W<'_>

Bit 20 - Waveform shape

pub fn timout(&mut self) -> TIMOUT_W<'_>

Bit 19 - Timeout enable

pub fn trigen(&mut self) -> TRIGEN_W<'_>

Bits 17:18 - Trigger enable and polarity

pub fn trigsel(&mut self) -> TRIGSEL_W<'_>

Bits 13:15 - Trigger selector

pub fn presc(&mut self) -> PRESC_W<'_>

Bits 9:11 - Clock prescaler

pub fn trgflt(&mut self) -> TRGFLT_W<'_>

Bits 6:7 - Configurable digital filter for trigger

pub fn ckflt(&mut self) -> CKFLT_W<'_>

Bits 3:4 - Configurable digital filter for external clock

pub fn ckpol(&mut self) -> CKPOL_W<'_>

Bits 1:2 - Clock Polarity

pub fn cksel(&mut self) -> CKSEL_W<'_>

Bit 0 - Clock selector

impl W<u32, Reg<u32, _CR>>

pub fn cntstrt(&mut self) -> CNTSTRT_W<'_>

Bit 2 - Timer start in continuous mode

pub fn sngstrt(&mut self) -> SNGSTRT_W<'_>

Bit 1 - LPTIM start in single mode

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - LPTIM Enable

impl W<u32, Reg<u32, _CMP>>

pub fn cmp(&mut self) -> CMP_W<'_>

Bits 0:15 - Compare value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto reload value

impl W<u32, Reg<u32, _CR1>>

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn eobie(&mut self) -> EOBIE_W<'_>

Bit 27 - End of Block interrupt enable

pub fn rtoie(&mut self) -> RTOIE_W<'_>

Bit 26 - Receiver timeout interrupt enable

pub fn over8(&mut self) -> OVER8_W<'_>

Bit 15 - Oversampling mode

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - Driver Enable de-assertion time

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - Driver Enable assertion time

impl W<u32, Reg<u32, _CR2>>

pub fn rtoen(&mut self) -> RTOEN_W<'_>

Bit 23 - Receiver timeout enable

pub fn abren(&mut self) -> ABREN_W<'_>

Bit 20 - Auto baud rate enable

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn datainv(&mut self) -> DATAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn linen(&mut self) -> LINEN_W<'_>

Bit 14 - LIN mode enable

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 10 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 9 - Clock phase

pub fn lbcl(&mut self) -> LBCL_W<'_>

Bit 8 - Last bit clock pulse

pub fn lbdie(&mut self) -> LBDIE_W<'_>

Bit 6 - LIN break detection interrupt enable

pub fn lbdl(&mut self) -> LBDL_W<'_>

Bit 5 - LIN break detection length

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn add(&mut self) -> ADD_W<'_>

Bits 24:31 - Address of the USART node

pub fn abrmod(&mut self) -> ABRMOD_W<'_>

Bits 21:22 - Auto baud rate mode

impl W<u32, Reg<u32, _CR3>>

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - Ir low-power

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - Ir mode enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:15 - DIV_Mantissa

impl W<u32, Reg<u32, _GTPR>>

pub fn gt(&mut self) -> GT_W<'_>

Bits 8:15 - Guard time value

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:7 - Prescaler value

impl W<u32, Reg<u32, _RTOR>>

pub fn blen(&mut self) -> BLEN_W<'_>

Bits 24:31 - Block Length

pub fn rto(&mut self) -> RTO_W<'_>

Bits 0:23 - Receiver timeout value

impl W<u32, Reg<u32, _RQR>>

pub fn txfrq(&mut self) -> TXFRQ_W<'_>

Bit 4 - Transmit data flush request

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

pub fn abrrq(&mut self) -> ABRRQ_W<'_>

Bit 0 - Auto baud rate request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn eobcf(&mut self) -> EOBCF_W<'_>

Bit 12 - End of block clear flag

pub fn rtocf(&mut self) -> RTOCF_W<'_>

Bit 11 - Receiver timeout clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn lbdcf(&mut self) -> LBDCF_W<'_>

Bit 8 - LIN break detection clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _CR1>>

pub fn m1(&mut self) -> M1_W<'_>

Bit 28 - Word length

pub fn cmie(&mut self) -> CMIE_W<'_>

Bit 14 - Character match interrupt enable

pub fn mme(&mut self) -> MME_W<'_>

Bit 13 - Mute mode enable

pub fn m0(&mut self) -> M0_W<'_>

Bit 12 - Word length

pub fn wake(&mut self) -> WAKE_W<'_>

Bit 11 - Receiver wakeup method

pub fn pce(&mut self) -> PCE_W<'_>

Bit 10 - Parity control enable

pub fn ps(&mut self) -> PS_W<'_>

Bit 9 - Parity selection

pub fn peie(&mut self) -> PEIE_W<'_>

Bit 8 - PE interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 6 - Transmission complete interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 5 - RXNE interrupt enable

pub fn idleie(&mut self) -> IDLEIE_W<'_>

Bit 4 - IDLE interrupt enable

pub fn te(&mut self) -> TE_W<'_>

Bit 3 - Transmitter enable

pub fn re(&mut self) -> RE_W<'_>

Bit 2 - Receiver enable

pub fn uesm(&mut self) -> UESM_W<'_>

Bit 1 - USART enable in Stop mode

pub fn ue(&mut self) -> UE_W<'_>

Bit 0 - USART enable

pub fn deat(&mut self) -> DEAT_W<'_>

Bits 21:25 - Driver Enable assertion time

pub fn dedt(&mut self) -> DEDT_W<'_>

Bits 16:20 - Driver Enable de-assertion time

impl W<u32, Reg<u32, _CR2>>

pub fn msbfirst(&mut self) -> MSBFIRST_W<'_>

Bit 19 - Most significant bit first

pub fn datainv(&mut self) -> DATAINV_W<'_>

Bit 18 - Binary data inversion

pub fn txinv(&mut self) -> TXINV_W<'_>

Bit 17 - TX pin active level inversion

pub fn rxinv(&mut self) -> RXINV_W<'_>

Bit 16 - RX pin active level inversion

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 15 - Swap TX/RX pins

pub fn stop(&mut self) -> STOP_W<'_>

Bits 12:13 - STOP bits

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 11 - Clock enable

pub fn addm7(&mut self) -> ADDM7_W<'_>

Bit 4 - 7-bit Address Detection/4-bit Address Detection

pub fn add(&mut self) -> ADD_W<'_>

Bits 24:31 - Address of the USART node

impl W<u32, Reg<u32, _CR3>>

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from Stop mode interrupt enable

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from Stop mode interrupt flag selection

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable

impl W<u32, Reg<u32, _BRR>>

pub fn brr(&mut self) -> BRR_W<'_>

Bits 0:19 - BRR

impl W<u32, Reg<u32, _RQR>>

pub fn rxfrq(&mut self) -> RXFRQ_W<'_>

Bit 3 - Receive data flush request

pub fn mmrq(&mut self) -> MMRQ_W<'_>

Bit 2 - Mute mode request

pub fn sbkrq(&mut self) -> SBKRQ_W<'_>

Bit 1 - Send break request

impl W<u32, Reg<u32, _ICR>>

pub fn wucf(&mut self) -> WUCF_W<'_>

Bit 20 - Wakeup from Stop mode clear flag

pub fn cmcf(&mut self) -> CMCF_W<'_>

Bit 17 - Character match clear flag

pub fn ctscf(&mut self) -> CTSCF_W<'_>

Bit 9 - CTS clear flag

pub fn tccf(&mut self) -> TCCF_W<'_>

Bit 6 - Transmission complete clear flag

pub fn idlecf(&mut self) -> IDLECF_W<'_>

Bit 4 - Idle line detected clear flag

pub fn orecf(&mut self) -> ORECF_W<'_>

Bit 3 - Overrun error clear flag

pub fn ncf(&mut self) -> NCF_W<'_>

Bit 2 - Noise detected clear flag

pub fn fecf(&mut self) -> FECF_W<'_>

Bit 1 - Framing error clear flag

pub fn pecf(&mut self) -> PECF_W<'_>

Bit 0 - Parity error clear flag

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W<'_>

Bits 0:8 - Transmit data value

impl W<u32, Reg<u32, _CR1>>

pub fn bidimode(&mut self) -> BIDIMODE_W<'_>

Bit 15 - Bidirectional data mode enable

pub fn bidioe(&mut self) -> BIDIOE_W<'_>

Bit 14 - Output enable in bidirectional mode

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 13 - Hardware CRC calculation enable

pub fn crcnext(&mut self) -> CRCNEXT_W<'_>

Bit 12 - CRC transfer next

pub fn crcl(&mut self) -> CRCL_W<'_>

Bit 11 - CRC length

pub fn rxonly(&mut self) -> RXONLY_W<'_>

Bit 10 - Receive only

pub fn ssm(&mut self) -> SSM_W<'_>

Bit 9 - Software slave management

pub fn ssi(&mut self) -> SSI_W<'_>

Bit 8 - Internal slave select

pub fn lsbfirst(&mut self) -> LSBFIRST_W<'_>

Bit 7 - Frame format

pub fn spe(&mut self) -> SPE_W<'_>

Bit 6 - SPI enable

pub fn br(&mut self) -> BR_W<'_>

Bits 3:5 - Baud rate control

pub fn mstr(&mut self) -> MSTR_W<'_>

Bit 2 - Master selection

pub fn cpol(&mut self) -> CPOL_W<'_>

Bit 1 - Clock polarity

pub fn cpha(&mut self) -> CPHA_W<'_>

Bit 0 - Clock phase

impl W<u32, Reg<u32, _CR2>>

pub fn rxdmaen(&mut self) -> RXDMAEN_W<'_>

Bit 0 - Rx buffer DMA enable

pub fn txdmaen(&mut self) -> TXDMAEN_W<'_>

Bit 1 - Tx buffer DMA enable

pub fn ssoe(&mut self) -> SSOE_W<'_>

Bit 2 - SS output enable

pub fn nssp(&mut self) -> NSSP_W<'_>

Bit 3 - NSS pulse management

pub fn frf(&mut self) -> FRF_W<'_>

Bit 4 - Frame format

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 5 - Error interrupt enable

pub fn rxneie(&mut self) -> RXNEIE_W<'_>

Bit 6 - RX buffer not empty interrupt enable

pub fn txeie(&mut self) -> TXEIE_W<'_>

Bit 7 - Tx buffer empty interrupt enable

pub fn ds(&mut self) -> DS_W<'_>

Bits 8:11 - Data size

pub fn frxth(&mut self) -> FRXTH_W<'_>

Bit 12 - FIFO reception threshold

pub fn ldma_rx(&mut self) -> LDMA_RX_W<'_>

Bit 13 - Last DMA transfer for reception

pub fn ldma_tx(&mut self) -> LDMA_TX_W<'_>

Bit 14 - Last DMA transfer for transmission

impl W<u32, Reg<u32, _SR>>

pub fn crcerr(&mut self) -> CRCERR_W<'_>

Bit 4 - CRC error flag

impl W<u32, Reg<u32, _DR>>

pub fn dr(&mut self) -> DR_W<'_>

Bits 0:15 - Data register

impl W<u32, Reg<u32, _CRCPR>>

pub fn crcpoly(&mut self) -> CRCPOLY_W<'_>

Bits 0:15 - CRC polynomial register

impl W<u32, Reg<u32, _POWER>>

pub fn pwrctrl(&mut self) -> PWRCTRL_W<'_>

Bits 0:1 - PWRCTRL

impl W<u32, Reg<u32, _CLKCR>>

pub fn hwfc_en(&mut self) -> HWFC_EN_W<'_>

Bit 14 - HW Flow Control enable

pub fn negedge(&mut self) -> NEGEDGE_W<'_>

Bit 13 - SDIO_CK dephasing selection bit

pub fn widbus(&mut self) -> WIDBUS_W<'_>

Bits 11:12 - Wide bus mode enable bit

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 10 - Clock divider bypass enable bit

pub fn pwrsav(&mut self) -> PWRSAV_W<'_>

Bit 9 - Power saving configuration bit

pub fn clken(&mut self) -> CLKEN_W<'_>

Bit 8 - Clock enable bit

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 0:7 - Clock divide factor

impl W<u32, Reg<u32, _ARG>>

pub fn cmdarg(&mut self) -> CMDARG_W<'_>

Bits 0:31 - Command argument

impl W<u32, Reg<u32, _CMD>>

pub fn ce_atacmd(&mut self) -> CE_ATACMD_W<'_>

Bit 14 - CE-ATA command

pub fn n_ien(&mut self) -> NIEN_W<'_>

Bit 13 - not Interrupt Enable

pub fn encmdcompl(&mut self) -> ENCMDCOMPL_W<'_>

Bit 12 - Enable CMD completion

pub fn sdiosuspend(&mut self) -> SDIOSUSPEND_W<'_>

Bit 11 - SD I/O suspend command

pub fn cpsmen(&mut self) -> CPSMEN_W<'_>

Bit 10 - Command path state machine (CPSM) Enable bit

pub fn waitpend(&mut self) -> WAITPEND_W<'_>

Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)

pub fn waitint(&mut self) -> WAITINT_W<'_>

Bit 8 - CPSM waits for interrupt request

pub fn waitresp(&mut self) -> WAITRESP_W<'_>

Bits 6:7 - Wait for response bits

pub fn cmdindex(&mut self) -> CMDINDEX_W<'_>

Bits 0:5 - Command index

impl W<u32, Reg<u32, _DTIMER>>

pub fn datatime(&mut self) -> DATATIME_W<'_>

Bits 0:31 - Data timeout period

impl W<u32, Reg<u32, _DLEN>>

pub fn datalength(&mut self) -> DATALENGTH_W<'_>

Bits 0:24 - Data length value

impl W<u32, Reg<u32, _DCTRL>>

pub fn sdioen(&mut self) -> SDIOEN_W<'_>

Bit 11 - SD I/O enable functions

pub fn rwmod(&mut self) -> RWMOD_W<'_>

Bit 10 - Read wait mode

pub fn rwstop(&mut self) -> RWSTOP_W<'_>

Bit 9 - Read wait stop

pub fn rwstart(&mut self) -> RWSTART_W<'_>

Bit 8 - Read wait start

pub fn dblocksize(&mut self) -> DBLOCKSIZE_W<'_>

Bits 4:7 - Data block size

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 3 - DMA enable bit

pub fn dtmode(&mut self) -> DTMODE_W<'_>

Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer

pub fn dtdir(&mut self) -> DTDIR_W<'_>

Bit 1 - Data transfer direction selection

pub fn dten(&mut self) -> DTEN_W<'_>

Bit 0 - DTEN

impl W<u32, Reg<u32, _ICR>>

pub fn ceataendc(&mut self) -> CEATAENDC_W<'_>

Bit 23 - CEATAEND flag clear bit

pub fn sdioitc(&mut self) -> SDIOITC_W<'_>

Bit 22 - SDIOIT flag clear bit

pub fn dbckendc(&mut self) -> DBCKENDC_W<'_>

Bit 10 - DBCKEND flag clear bit

pub fn stbiterrc(&mut self) -> STBITERRC_W<'_>

Bit 9 - STBITERR flag clear bit

pub fn dataendc(&mut self) -> DATAENDC_W<'_>

Bit 8 - DATAEND flag clear bit

pub fn cmdsentc(&mut self) -> CMDSENTC_W<'_>

Bit 7 - CMDSENT flag clear bit

pub fn cmdrendc(&mut self) -> CMDRENDC_W<'_>

Bit 6 - CMDREND flag clear bit

pub fn rxoverrc(&mut self) -> RXOVERRC_W<'_>

Bit 5 - RXOVERR flag clear bit

pub fn txunderrc(&mut self) -> TXUNDERRC_W<'_>

Bit 4 - TXUNDERR flag clear bit

pub fn dtimeoutc(&mut self) -> DTIMEOUTC_W<'_>

Bit 3 - DTIMEOUT flag clear bit

pub fn ctimeoutc(&mut self) -> CTIMEOUTC_W<'_>

Bit 2 - CTIMEOUT flag clear bit

pub fn dcrcfailc(&mut self) -> DCRCFAILC_W<'_>

Bit 1 - DCRCFAIL flag clear bit

pub fn ccrcfailc(&mut self) -> CCRCFAILC_W<'_>

Bit 0 - CCRCFAIL flag clear bit

impl W<u32, Reg<u32, _MASK>>

pub fn ceataendie(&mut self) -> CEATAENDIE_W<'_>

Bit 23 - CE-ATA command completion signal received interrupt enable

pub fn sdioitie(&mut self) -> SDIOITIE_W<'_>

Bit 22 - SDIO mode interrupt received interrupt enable

pub fn rxdavlie(&mut self) -> RXDAVLIE_W<'_>

Bit 21 - Data available in Rx FIFO interrupt enable

pub fn txdavlie(&mut self) -> TXDAVLIE_W<'_>

Bit 20 - Data available in Tx FIFO interrupt enable

pub fn rxfifoeie(&mut self) -> RXFIFOEIE_W<'_>

Bit 19 - Rx FIFO empty interrupt enable

pub fn txfifoeie(&mut self) -> TXFIFOEIE_W<'_>

Bit 18 - Tx FIFO empty interrupt enable

pub fn rxfifofie(&mut self) -> RXFIFOFIE_W<'_>

Bit 17 - Rx FIFO full interrupt enable

pub fn txfifofie(&mut self) -> TXFIFOFIE_W<'_>

Bit 16 - Tx FIFO full interrupt enable

pub fn rxfifohfie(&mut self) -> RXFIFOHFIE_W<'_>

Bit 15 - Rx FIFO half full interrupt enable

pub fn txfifoheie(&mut self) -> TXFIFOHEIE_W<'_>

Bit 14 - Tx FIFO half empty interrupt enable

pub fn rxactie(&mut self) -> RXACTIE_W<'_>

Bit 13 - Data receive acting interrupt enable

pub fn txactie(&mut self) -> TXACTIE_W<'_>

Bit 12 - Data transmit acting interrupt enable

pub fn cmdactie(&mut self) -> CMDACTIE_W<'_>

Bit 11 - Command acting interrupt enable

pub fn dbckendie(&mut self) -> DBCKENDIE_W<'_>

Bit 10 - Data block end interrupt enable

pub fn stbiterrie(&mut self) -> STBITERRIE_W<'_>

Bit 9 - Start bit error interrupt enable

pub fn dataendie(&mut self) -> DATAENDIE_W<'_>

Bit 8 - Data end interrupt enable

pub fn cmdsentie(&mut self) -> CMDSENTIE_W<'_>

Bit 7 - Command sent interrupt enable

pub fn cmdrendie(&mut self) -> CMDRENDIE_W<'_>

Bit 6 - Command response received interrupt enable

pub fn rxoverrie(&mut self) -> RXOVERRIE_W<'_>

Bit 5 - Rx FIFO overrun error interrupt enable

pub fn txunderrie(&mut self) -> TXUNDERRIE_W<'_>

Bit 4 - Tx FIFO underrun error interrupt enable

pub fn dtimeoutie(&mut self) -> DTIMEOUTIE_W<'_>

Bit 3 - Data timeout interrupt enable

pub fn ctimeoutie(&mut self) -> CTIMEOUTIE_W<'_>

Bit 2 - Command timeout interrupt enable

pub fn dcrcfailie(&mut self) -> DCRCFAILIE_W<'_>

Bit 1 - Data CRC fail interrupt enable

pub fn ccrcfailie(&mut self) -> CCRCFAILIE_W<'_>

Bit 0 - Command CRC fail interrupt enable

impl W<u32, Reg<u32, _FIFO>>

pub fn fifodata(&mut self) -> FIFODATA_W<'_>

Bits 0:31 - Receive and transmit FIFO data

impl W<u32, Reg<u32, _IMR1>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Interrupt Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Interrupt Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Interrupt Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Interrupt Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Interrupt Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Interrupt Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Interrupt Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Interrupt Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Interrupt Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Interrupt Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Interrupt Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Interrupt Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Interrupt Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Interrupt Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Interrupt Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Interrupt Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Interrupt Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Interrupt Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Interrupt Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Interrupt Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Interrupt Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Interrupt Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Interrupt Mask on line 22

pub fn mr23(&mut self) -> MR23_W<'_>

Bit 23 - Interrupt Mask on line 23

pub fn mr24(&mut self) -> MR24_W<'_>

Bit 24 - Interrupt Mask on line 24

pub fn mr25(&mut self) -> MR25_W<'_>

Bit 25 - Interrupt Mask on line 25

pub fn mr26(&mut self) -> MR26_W<'_>

Bit 26 - Interrupt Mask on line 26

pub fn mr27(&mut self) -> MR27_W<'_>

Bit 27 - Interrupt Mask on line 27

pub fn mr28(&mut self) -> MR28_W<'_>

Bit 28 - Interrupt Mask on line 28

pub fn mr29(&mut self) -> MR29_W<'_>

Bit 29 - Interrupt Mask on line 29

pub fn mr30(&mut self) -> MR30_W<'_>

Bit 30 - Interrupt Mask on line 30

pub fn mr31(&mut self) -> MR31_W<'_>

Bit 31 - Interrupt Mask on line 31

impl W<u32, Reg<u32, _EMR1>>

pub fn mr0(&mut self) -> MR0_W<'_>

Bit 0 - Event Mask on line 0

pub fn mr1(&mut self) -> MR1_W<'_>

Bit 1 - Event Mask on line 1

pub fn mr2(&mut self) -> MR2_W<'_>

Bit 2 - Event Mask on line 2

pub fn mr3(&mut self) -> MR3_W<'_>

Bit 3 - Event Mask on line 3

pub fn mr4(&mut self) -> MR4_W<'_>

Bit 4 - Event Mask on line 4

pub fn mr5(&mut self) -> MR5_W<'_>

Bit 5 - Event Mask on line 5

pub fn mr6(&mut self) -> MR6_W<'_>

Bit 6 - Event Mask on line 6

pub fn mr7(&mut self) -> MR7_W<'_>

Bit 7 - Event Mask on line 7

pub fn mr8(&mut self) -> MR8_W<'_>

Bit 8 - Event Mask on line 8

pub fn mr9(&mut self) -> MR9_W<'_>

Bit 9 - Event Mask on line 9

pub fn mr10(&mut self) -> MR10_W<'_>

Bit 10 - Event Mask on line 10

pub fn mr11(&mut self) -> MR11_W<'_>

Bit 11 - Event Mask on line 11

pub fn mr12(&mut self) -> MR12_W<'_>

Bit 12 - Event Mask on line 12

pub fn mr13(&mut self) -> MR13_W<'_>

Bit 13 - Event Mask on line 13

pub fn mr14(&mut self) -> MR14_W<'_>

Bit 14 - Event Mask on line 14

pub fn mr15(&mut self) -> MR15_W<'_>

Bit 15 - Event Mask on line 15

pub fn mr16(&mut self) -> MR16_W<'_>

Bit 16 - Event Mask on line 16

pub fn mr17(&mut self) -> MR17_W<'_>

Bit 17 - Event Mask on line 17

pub fn mr18(&mut self) -> MR18_W<'_>

Bit 18 - Event Mask on line 18

pub fn mr19(&mut self) -> MR19_W<'_>

Bit 19 - Event Mask on line 19

pub fn mr20(&mut self) -> MR20_W<'_>

Bit 20 - Event Mask on line 20

pub fn mr21(&mut self) -> MR21_W<'_>

Bit 21 - Event Mask on line 21

pub fn mr22(&mut self) -> MR22_W<'_>

Bit 22 - Event Mask on line 22

pub fn mr23(&mut self) -> MR23_W<'_>

Bit 23 - Event Mask on line 23

pub fn mr24(&mut self) -> MR24_W<'_>

Bit 24 - Event Mask on line 24

pub fn mr25(&mut self) -> MR25_W<'_>

Bit 25 - Event Mask on line 25

pub fn mr26(&mut self) -> MR26_W<'_>

Bit 26 - Event Mask on line 26

pub fn mr27(&mut self) -> MR27_W<'_>

Bit 27 - Event Mask on line 27

pub fn mr28(&mut self) -> MR28_W<'_>

Bit 28 - Event Mask on line 28

pub fn mr29(&mut self) -> MR29_W<'_>

Bit 29 - Event Mask on line 29

pub fn mr30(&mut self) -> MR30_W<'_>

Bit 30 - Event Mask on line 30

pub fn mr31(&mut self) -> MR31_W<'_>

Bit 31 - Event Mask on line 31

impl W<u32, Reg<u32, _RTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Rising trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Rising trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Rising trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Rising trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Rising trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Rising trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Rising trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Rising trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Rising trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Rising trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Rising trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Rising trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Rising trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Rising trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Rising trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Rising trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Rising trigger event configuration of line 16

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Rising trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Rising trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Rising trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Rising trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Rising trigger event configuration of line 22

impl W<u32, Reg<u32, _FTSR1>>

pub fn tr0(&mut self) -> TR0_W<'_>

Bit 0 - Falling trigger event configuration of line 0

pub fn tr1(&mut self) -> TR1_W<'_>

Bit 1 - Falling trigger event configuration of line 1

pub fn tr2(&mut self) -> TR2_W<'_>

Bit 2 - Falling trigger event configuration of line 2

pub fn tr3(&mut self) -> TR3_W<'_>

Bit 3 - Falling trigger event configuration of line 3

pub fn tr4(&mut self) -> TR4_W<'_>

Bit 4 - Falling trigger event configuration of line 4

pub fn tr5(&mut self) -> TR5_W<'_>

Bit 5 - Falling trigger event configuration of line 5

pub fn tr6(&mut self) -> TR6_W<'_>

Bit 6 - Falling trigger event configuration of line 6

pub fn tr7(&mut self) -> TR7_W<'_>

Bit 7 - Falling trigger event configuration of line 7

pub fn tr8(&mut self) -> TR8_W<'_>

Bit 8 - Falling trigger event configuration of line 8

pub fn tr9(&mut self) -> TR9_W<'_>

Bit 9 - Falling trigger event configuration of line 9

pub fn tr10(&mut self) -> TR10_W<'_>

Bit 10 - Falling trigger event configuration of line 10

pub fn tr11(&mut self) -> TR11_W<'_>

Bit 11 - Falling trigger event configuration of line 11

pub fn tr12(&mut self) -> TR12_W<'_>

Bit 12 - Falling trigger event configuration of line 12

pub fn tr13(&mut self) -> TR13_W<'_>

Bit 13 - Falling trigger event configuration of line 13

pub fn tr14(&mut self) -> TR14_W<'_>

Bit 14 - Falling trigger event configuration of line 14

pub fn tr15(&mut self) -> TR15_W<'_>

Bit 15 - Falling trigger event configuration of line 15

pub fn tr16(&mut self) -> TR16_W<'_>

Bit 16 - Falling trigger event configuration of line 16

pub fn tr18(&mut self) -> TR18_W<'_>

Bit 18 - Falling trigger event configuration of line 18

pub fn tr19(&mut self) -> TR19_W<'_>

Bit 19 - Falling trigger event configuration of line 19

pub fn tr20(&mut self) -> TR20_W<'_>

Bit 20 - Falling trigger event configuration of line 20

pub fn tr21(&mut self) -> TR21_W<'_>

Bit 21 - Falling trigger event configuration of line 21

pub fn tr22(&mut self) -> TR22_W<'_>

Bit 22 - Falling trigger event configuration of line 22

impl W<u32, Reg<u32, _SWIER1>>

pub fn swier0(&mut self) -> SWIER0_W<'_>

Bit 0 - Software Interrupt on line 0

pub fn swier1(&mut self) -> SWIER1_W<'_>

Bit 1 - Software Interrupt on line 1

pub fn swier2(&mut self) -> SWIER2_W<'_>

Bit 2 - Software Interrupt on line 2

pub fn swier3(&mut self) -> SWIER3_W<'_>

Bit 3 - Software Interrupt on line 3

pub fn swier4(&mut self) -> SWIER4_W<'_>

Bit 4 - Software Interrupt on line 4

pub fn swier5(&mut self) -> SWIER5_W<'_>

Bit 5 - Software Interrupt on line 5

pub fn swier6(&mut self) -> SWIER6_W<'_>

Bit 6 - Software Interrupt on line 6

pub fn swier7(&mut self) -> SWIER7_W<'_>

Bit 7 - Software Interrupt on line 7

pub fn swier8(&mut self) -> SWIER8_W<'_>

Bit 8 - Software Interrupt on line 8

pub fn swier9(&mut self) -> SWIER9_W<'_>

Bit 9 - Software Interrupt on line 9

pub fn swier10(&mut self) -> SWIER10_W<'_>

Bit 10 - Software Interrupt on line 10

pub fn swier11(&mut self) -> SWIER11_W<'_>

Bit 11 - Software Interrupt on line 11

pub fn swier12(&mut self) -> SWIER12_W<'_>

Bit 12 - Software Interrupt on line 12

pub fn swier13(&mut self) -> SWIER13_W<'_>

Bit 13 - Software Interrupt on line 13

pub fn swier14(&mut self) -> SWIER14_W<'_>

Bit 14 - Software Interrupt on line 14

pub fn swier15(&mut self) -> SWIER15_W<'_>

Bit 15 - Software Interrupt on line 15

pub fn swier16(&mut self) -> SWIER16_W<'_>

Bit 16 - Software Interrupt on line 16

pub fn swier18(&mut self) -> SWIER18_W<'_>

Bit 18 - Software Interrupt on line 18

pub fn swier19(&mut self) -> SWIER19_W<'_>

Bit 19 - Software Interrupt on line 19

pub fn swier20(&mut self) -> SWIER20_W<'_>

Bit 20 - Software Interrupt on line 20

pub fn swier21(&mut self) -> SWIER21_W<'_>

Bit 21 - Software Interrupt on line 21

pub fn swier22(&mut self) -> SWIER22_W<'_>

Bit 22 - Software Interrupt on line 22

impl W<u32, Reg<u32, _PR1>>

pub fn pr0(&mut self) -> PR0_W<'_>

Bit 0 - Pending bit 0

pub fn pr1(&mut self) -> PR1_W<'_>

Bit 1 - Pending bit 1

pub fn pr2(&mut self) -> PR2_W<'_>

Bit 2 - Pending bit 2

pub fn pr3(&mut self) -> PR3_W<'_>

Bit 3 - Pending bit 3

pub fn pr4(&mut self) -> PR4_W<'_>

Bit 4 - Pending bit 4

pub fn pr5(&mut self) -> PR5_W<'_>

Bit 5 - Pending bit 5

pub fn pr6(&mut self) -> PR6_W<'_>

Bit 6 - Pending bit 6

pub fn pr7(&mut self) -> PR7_W<'_>

Bit 7 - Pending bit 7

pub fn pr8(&mut self) -> PR8_W<'_>

Bit 8 - Pending bit 8

pub fn pr9(&mut self) -> PR9_W<'_>

Bit 9 - Pending bit 9

pub fn pr10(&mut self) -> PR10_W<'_>

Bit 10 - Pending bit 10

pub fn pr11(&mut self) -> PR11_W<'_>

Bit 11 - Pending bit 11

pub fn pr12(&mut self) -> PR12_W<'_>

Bit 12 - Pending bit 12

pub fn pr13(&mut self) -> PR13_W<'_>

Bit 13 - Pending bit 13

pub fn pr14(&mut self) -> PR14_W<'_>

Bit 14 - Pending bit 14

pub fn pr15(&mut self) -> PR15_W<'_>

Bit 15 - Pending bit 15

pub fn pr16(&mut self) -> PR16_W<'_>

Bit 16 - Pending bit 16

pub fn pr18(&mut self) -> PR18_W<'_>

Bit 18 - Pending bit 18

pub fn pr19(&mut self) -> PR19_W<'_>

Bit 19 - Pending bit 19

pub fn pr20(&mut self) -> PR20_W<'_>

Bit 20 - Pending bit 20

pub fn pr21(&mut self) -> PR21_W<'_>

Bit 21 - Pending bit 21

pub fn pr22(&mut self) -> PR22_W<'_>

Bit 22 - Pending bit 22

impl W<u32, Reg<u32, _IMR2>>

pub fn mr32(&mut self) -> MR32_W<'_>

Bit 0 - Interrupt Mask on external/internal line 32

pub fn mr33(&mut self) -> MR33_W<'_>

Bit 1 - Interrupt Mask on external/internal line 33

pub fn mr34(&mut self) -> MR34_W<'_>

Bit 2 - Interrupt Mask on external/internal line 34

pub fn mr35(&mut self) -> MR35_W<'_>

Bit 3 - Interrupt Mask on external/internal line 35

pub fn mr36(&mut self) -> MR36_W<'_>

Bit 4 - Interrupt Mask on external/internal line 36

pub fn mr37(&mut self) -> MR37_W<'_>

Bit 5 - Interrupt Mask on external/internal line 37

pub fn mr38(&mut self) -> MR38_W<'_>

Bit 6 - Interrupt Mask on external/internal line 38

pub fn mr39(&mut self) -> MR39_W<'_>

Bit 7 - Interrupt Mask on external/internal line 39

impl W<u32, Reg<u32, _EMR2>>

pub fn mr32(&mut self) -> MR32_W<'_>

Bit 0 - Event mask on external/internal line 32

pub fn mr33(&mut self) -> MR33_W<'_>

Bit 1 - Event mask on external/internal line 33

pub fn mr34(&mut self) -> MR34_W<'_>

Bit 2 - Event mask on external/internal line 34

pub fn mr35(&mut self) -> MR35_W<'_>

Bit 3 - Event mask on external/internal line 35

pub fn mr36(&mut self) -> MR36_W<'_>

Bit 4 - Event mask on external/internal line 36

pub fn mr37(&mut self) -> MR37_W<'_>

Bit 5 - Event mask on external/internal line 37

pub fn mr38(&mut self) -> MR38_W<'_>

Bit 6 - Event mask on external/internal line 38

pub fn mr39(&mut self) -> MR39_W<'_>

Bit 7 - Event mask on external/internal line 39

impl W<u32, Reg<u32, _RTSR2>>

pub fn rt35(&mut self) -> RT35_W<'_>

Bit 3 - Rising trigger event configuration bit of line 35

pub fn rt36(&mut self) -> RT36_W<'_>

Bit 4 - Rising trigger event configuration bit of line 36

pub fn rt37(&mut self) -> RT37_W<'_>

Bit 5 - Rising trigger event configuration bit of line 37

pub fn rt38(&mut self) -> RT38_W<'_>

Bit 6 - Rising trigger event configuration bit of line 38

impl W<u32, Reg<u32, _FTSR2>>

pub fn ft35(&mut self) -> FT35_W<'_>

Bit 3 - Falling trigger event configuration bit of line 35

pub fn ft36(&mut self) -> FT36_W<'_>

Bit 4 - Falling trigger event configuration bit of line 36

pub fn ft37(&mut self) -> FT37_W<'_>

Bit 5 - Falling trigger event configuration bit of line 37

pub fn ft38(&mut self) -> FT38_W<'_>

Bit 6 - Falling trigger event configuration bit of line 38

impl W<u32, Reg<u32, _SWIER2>>

pub fn swi35(&mut self) -> SWI35_W<'_>

Bit 3 - Software interrupt on line 35

pub fn swi36(&mut self) -> SWI36_W<'_>

Bit 4 - Software interrupt on line 36

pub fn swi37(&mut self) -> SWI37_W<'_>

Bit 5 - Software interrupt on line 37

pub fn swi38(&mut self) -> SWI38_W<'_>

Bit 6 - Software interrupt on line 38

impl W<u32, Reg<u32, _PR2>>

pub fn pif35(&mut self) -> PIF35_W<'_>

Bit 3 - Pending interrupt flag on line 35

pub fn pif36(&mut self) -> PIF36_W<'_>

Bit 4 - Pending interrupt flag on line 36

pub fn pif37(&mut self) -> PIF37_W<'_>

Bit 5 - Pending interrupt flag on line 37

pub fn pif38(&mut self) -> PIF38_W<'_>

Bit 6 - Pending interrupt flag on line 38

impl W<u32, Reg<u32, _CSR>>

pub fn envr(&mut self) -> ENVR_W<'_>

Bit 0 - Voltage reference buffer enable

pub fn hiz(&mut self) -> HIZ_W<'_>

Bit 1 - High impedance mode

pub fn vrs(&mut self) -> VRS_W<'_>

Bit 2 - Voltage reference scale

impl W<u32, Reg<u32, _CCR>>

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 0:5 - Trimming code

impl W<u32, Reg<u32, _TIR>>

pub fn stid(&mut self) -> STID_W<'_>

Bits 21:31 - STID

pub fn exid(&mut self) -> EXID_W<'_>

Bits 3:20 - EXID

pub fn ide(&mut self) -> IDE_W<'_>

Bit 2 - IDE

pub fn rtr(&mut self) -> RTR_W<'_>

Bit 1 - RTR

pub fn txrq(&mut self) -> TXRQ_W<'_>

Bit 0 - TXRQ

impl W<u32, Reg<u32, _TDTR>>

pub fn time(&mut self) -> TIME_W<'_>

Bits 16:31 - TIME

pub fn tgt(&mut self) -> TGT_W<'_>

Bit 8 - TGT

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - DLC

impl W<u32, Reg<u32, _TDLR>>

pub fn data3(&mut self) -> DATA3_W<'_>

Bits 24:31 - DATA3

pub fn data2(&mut self) -> DATA2_W<'_>

Bits 16:23 - DATA2

pub fn data1(&mut self) -> DATA1_W<'_>

Bits 8:15 - DATA1

pub fn data0(&mut self) -> DATA0_W<'_>

Bits 0:7 - DATA0

impl W<u32, Reg<u32, _TDHR>>

pub fn data7(&mut self) -> DATA7_W<'_>

Bits 24:31 - DATA7

pub fn data6(&mut self) -> DATA6_W<'_>

Bits 16:23 - DATA6

pub fn data5(&mut self) -> DATA5_W<'_>

Bits 8:15 - DATA5

pub fn data4(&mut self) -> DATA4_W<'_>

Bits 0:7 - DATA4

impl W<u32, Reg<u32, _FR1>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _FR2>>

pub fn fb(&mut self) -> FB_W<'_>

Bits 0:31 - Filter bits

impl W<u32, Reg<u32, _MCR>>

pub fn dbf(&mut self) -> DBF_W<'_>

Bit 16 - DBF

pub fn reset(&mut self) -> RESET_W<'_>

Bit 15 - RESET

pub fn ttcm(&mut self) -> TTCM_W<'_>

Bit 7 - TTCM

pub fn abom(&mut self) -> ABOM_W<'_>

Bit 6 - ABOM

pub fn awum(&mut self) -> AWUM_W<'_>

Bit 5 - AWUM

pub fn nart(&mut self) -> NART_W<'_>

Bit 4 - NART

pub fn rflm(&mut self) -> RFLM_W<'_>

Bit 3 - RFLM

pub fn txfp(&mut self) -> TXFP_W<'_>

Bit 2 - TXFP

pub fn sleep(&mut self) -> SLEEP_W<'_>

Bit 1 - SLEEP

pub fn inrq(&mut self) -> INRQ_W<'_>

Bit 0 - INRQ

impl W<u32, Reg<u32, _MSR>>

pub fn slaki(&mut self) -> SLAKI_W<'_>

Bit 4 - SLAKI

pub fn wkui(&mut self) -> WKUI_W<'_>

Bit 3 - WKUI

pub fn erri(&mut self) -> ERRI_W<'_>

Bit 2 - ERRI

impl W<u32, Reg<u32, _TSR>>

pub fn abrq2(&mut self) -> ABRQ2_W<'_>

Bit 23 - ABRQ2

pub fn terr2(&mut self) -> TERR2_W<'_>

Bit 19 - TERR2

pub fn alst2(&mut self) -> ALST2_W<'_>

Bit 18 - ALST2

pub fn txok2(&mut self) -> TXOK2_W<'_>

Bit 17 - TXOK2

pub fn rqcp2(&mut self) -> RQCP2_W<'_>

Bit 16 - RQCP2

pub fn abrq1(&mut self) -> ABRQ1_W<'_>

Bit 15 - ABRQ1

pub fn terr1(&mut self) -> TERR1_W<'_>

Bit 11 - TERR1

pub fn alst1(&mut self) -> ALST1_W<'_>

Bit 10 - ALST1

pub fn txok1(&mut self) -> TXOK1_W<'_>

Bit 9 - TXOK1

pub fn rqcp1(&mut self) -> RQCP1_W<'_>

Bit 8 - RQCP1

pub fn abrq0(&mut self) -> ABRQ0_W<'_>

Bit 7 - ABRQ0

pub fn terr0(&mut self) -> TERR0_W<'_>

Bit 3 - TERR0

pub fn alst0(&mut self) -> ALST0_W<'_>

Bit 2 - ALST0

pub fn txok0(&mut self) -> TXOK0_W<'_>

Bit 1 - TXOK0

pub fn rqcp0(&mut self) -> RQCP0_W<'_>

Bit 0 - RQCP0

impl W<u32, Reg<u32, _RFR>>

pub fn rfom(&mut self) -> RFOM_W<'_>

Bit 5 - RFOM0

pub fn fovr(&mut self) -> FOVR_W<'_>

Bit 4 - FOVR0

pub fn full(&mut self) -> FULL_W<'_>

Bit 3 - FULL0

impl W<u32, Reg<u32, _IER>>

pub fn slkie(&mut self) -> SLKIE_W<'_>

Bit 17 - SLKIE

pub fn wkuie(&mut self) -> WKUIE_W<'_>

Bit 16 - WKUIE

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 15 - ERRIE

pub fn lecie(&mut self) -> LECIE_W<'_>

Bit 11 - LECIE

pub fn bofie(&mut self) -> BOFIE_W<'_>

Bit 10 - BOFIE

pub fn epvie(&mut self) -> EPVIE_W<'_>

Bit 9 - EPVIE

pub fn ewgie(&mut self) -> EWGIE_W<'_>

Bit 8 - EWGIE

pub fn fovie1(&mut self) -> FOVIE1_W<'_>

Bit 6 - FOVIE1

pub fn ffie1(&mut self) -> FFIE1_W<'_>

Bit 5 - FFIE1

pub fn fmpie1(&mut self) -> FMPIE1_W<'_>

Bit 4 - FMPIE1

pub fn fovie0(&mut self) -> FOVIE0_W<'_>

Bit 3 - FOVIE0

pub fn ffie0(&mut self) -> FFIE0_W<'_>

Bit 2 - FFIE0

pub fn fmpie0(&mut self) -> FMPIE0_W<'_>

Bit 1 - FMPIE0

pub fn tmeie(&mut self) -> TMEIE_W<'_>

Bit 0 - TMEIE

impl W<u32, Reg<u32, _ESR>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 4:6 - LEC

impl W<u32, Reg<u32, _BTR>>

pub fn silm(&mut self) -> SILM_W<'_>

Bit 31 - SILM

pub fn lbkm(&mut self) -> LBKM_W<'_>

Bit 30 - LBKM

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 24:25 - SJW

pub fn ts2(&mut self) -> TS2_W<'_>

Bits 20:22 - TS2

pub fn ts1(&mut self) -> TS1_W<'_>

Bits 16:19 - TS1

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:9 - BRP

impl W<u32, Reg<u32, _TR>>

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _DR>>

pub fn yt(&mut self) -> YT_W<'_>

Bits 20:23 - Year tens in BCD format

pub fn yu(&mut self) -> YU_W<'_>

Bits 16:19 - Year units in BCD format

pub fn wdu(&mut self) -> WDU_W<'_>

Bits 13:15 - Week day units

pub fn mt(&mut self) -> MT_W<'_>

Bit 12 - Month tens in BCD format

pub fn mu(&mut self) -> MU_W<'_>

Bits 8:11 - Month units in BCD format

pub fn dt(&mut self) -> DT_W<'_>

Bits 4:5 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 0:3 - Date units in BCD format

impl W<u32, Reg<u32, _CR>>

pub fn wucksel(&mut self) -> WUCKSEL_W<'_>

Bits 0:2 - Wakeup clock selection

pub fn tsedge(&mut self) -> TSEDGE_W<'_>

Bit 3 - Time-stamp event active edge

pub fn refckon(&mut self) -> REFCKON_W<'_>

Bit 4 - Reference clock detection enable (50 or 60 Hz)

pub fn bypshad(&mut self) -> BYPSHAD_W<'_>

Bit 5 - Bypass the shadow registers

pub fn fmt(&mut self) -> FMT_W<'_>

Bit 6 - Hour format

pub fn alrae(&mut self) -> ALRAE_W<'_>

Bit 8 - Alarm A enable

pub fn alrbe(&mut self) -> ALRBE_W<'_>

Bit 9 - Alarm B enable

pub fn wute(&mut self) -> WUTE_W<'_>

Bit 10 - Wakeup timer enable

pub fn tse(&mut self) -> TSE_W<'_>

Bit 11 - Time stamp enable

pub fn alraie(&mut self) -> ALRAIE_W<'_>

Bit 12 - Alarm A interrupt enable

pub fn alrbie(&mut self) -> ALRBIE_W<'_>

Bit 13 - Alarm B interrupt enable

pub fn wutie(&mut self) -> WUTIE_W<'_>

Bit 14 - Wakeup timer interrupt enable

pub fn tsie(&mut self) -> TSIE_W<'_>

Bit 15 - Time-stamp interrupt enable

pub fn add1h(&mut self) -> ADD1H_W<'_>

Bit 16 - Add 1 hour (summer time change)

pub fn sub1h(&mut self) -> SUB1H_W<'_>

Bit 17 - Subtract 1 hour (winter time change)

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 18 - Backup

pub fn cosel(&mut self) -> COSEL_W<'_>

Bit 19 - Calibration output selection

pub fn pol(&mut self) -> POL_W<'_>

Bit 20 - Output polarity

pub fn osel(&mut self) -> OSEL_W<'_>

Bits 21:22 - Output selection

pub fn coe(&mut self) -> COE_W<'_>

Bit 23 - Calibration output enable

pub fn itse(&mut self) -> ITSE_W<'_>

Bit 24 - timestamp on internal event enable

impl W<u32, Reg<u32, _ISR>>

pub fn shpf(&mut self) -> SHPF_W<'_>

Bit 3 - Shift operation pending

pub fn rsf(&mut self) -> RSF_W<'_>

Bit 5 - Registers synchronization flag

pub fn init(&mut self) -> INIT_W<'_>

Bit 7 - Initialization mode

pub fn alraf(&mut self) -> ALRAF_W<'_>

Bit 8 - Alarm A flag

pub fn alrbf(&mut self) -> ALRBF_W<'_>

Bit 9 - Alarm B flag

pub fn wutf(&mut self) -> WUTF_W<'_>

Bit 10 - Wakeup timer flag

pub fn tsf(&mut self) -> TSF_W<'_>

Bit 11 - Time-stamp flag

pub fn tsovf(&mut self) -> TSOVF_W<'_>

Bit 12 - Time-stamp overflow flag

pub fn tamp1f(&mut self) -> TAMP1F_W<'_>

Bit 13 - Tamper detection flag

pub fn tamp2f(&mut self) -> TAMP2F_W<'_>

Bit 14 - RTC_TAMP2 detection flag

pub fn tamp3f(&mut self) -> TAMP3F_W<'_>

Bit 15 - RTC_TAMP3 detection flag

impl W<u32, Reg<u32, _PRER>>

pub fn prediv_a(&mut self) -> PREDIV_A_W<'_>

Bits 16:22 - Asynchronous prescaler factor

pub fn prediv_s(&mut self) -> PREDIV_S_W<'_>

Bits 0:14 - Synchronous prescaler factor

impl W<u32, Reg<u32, _WUTR>>

pub fn wut(&mut self) -> WUT_W<'_>

Bits 0:15 - Wakeup auto-reload value bits

impl W<u32, Reg<u32, _ALRMAR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm A date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm A hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm A minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm A seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _ALRMBR>>

pub fn msk4(&mut self) -> MSK4_W<'_>

Bit 31 - Alarm B date mask

pub fn wdsel(&mut self) -> WDSEL_W<'_>

Bit 30 - Week day selection

pub fn dt(&mut self) -> DT_W<'_>

Bits 28:29 - Date tens in BCD format

pub fn du(&mut self) -> DU_W<'_>

Bits 24:27 - Date units or day in BCD format

pub fn msk3(&mut self) -> MSK3_W<'_>

Bit 23 - Alarm B hours mask

pub fn pm(&mut self) -> PM_W<'_>

Bit 22 - AM/PM notation

pub fn ht(&mut self) -> HT_W<'_>

Bits 20:21 - Hour tens in BCD format

pub fn hu(&mut self) -> HU_W<'_>

Bits 16:19 - Hour units in BCD format

pub fn msk2(&mut self) -> MSK2_W<'_>

Bit 15 - Alarm B minutes mask

pub fn mnt(&mut self) -> MNT_W<'_>

Bits 12:14 - Minute tens in BCD format

pub fn mnu(&mut self) -> MNU_W<'_>

Bits 8:11 - Minute units in BCD format

pub fn msk1(&mut self) -> MSK1_W<'_>

Bit 7 - Alarm B seconds mask

pub fn st(&mut self) -> ST_W<'_>

Bits 4:6 - Second tens in BCD format

pub fn su(&mut self) -> SU_W<'_>

Bits 0:3 - Second units in BCD format

impl W<u32, Reg<u32, _WPR>>

pub fn key(&mut self) -> KEY_W<'_>

Bits 0:7 - Write protection key

impl W<u32, Reg<u32, _SHIFTR>>

pub fn add1s(&mut self) -> ADD1S_W<'_>

Bit 31 - Add one second

pub fn subfs(&mut self) -> SUBFS_W<'_>

Bits 0:14 - Subtract a fraction of a second

impl W<u32, Reg<u32, _CALR>>

pub fn calp(&mut self) -> CALP_W<'_>

Bit 15 - Increase frequency of RTC by 488.5 ppm

pub fn calw8(&mut self) -> CALW8_W<'_>

Bit 14 - Use an 8-second calibration cycle period

pub fn calw16(&mut self) -> CALW16_W<'_>

Bit 13 - Use a 16-second calibration cycle period

pub fn calm(&mut self) -> CALM_W<'_>

Bits 0:8 - Calibration minus

impl W<u32, Reg<u32, _TAMPCR>>

pub fn tamp1e(&mut self) -> TAMP1E_W<'_>

Bit 0 - Tamper 1 detection enable

pub fn tamp1trg(&mut self) -> TAMP1TRG_W<'_>

Bit 1 - Active level for tamper 1

pub fn tampie(&mut self) -> TAMPIE_W<'_>

Bit 2 - Tamper interrupt enable

pub fn tamp2e(&mut self) -> TAMP2E_W<'_>

Bit 3 - Tamper 2 detection enable

pub fn tamp2trg(&mut self) -> TAMP2TRG_W<'_>

Bit 4 - Active level for tamper 2

pub fn tamp3e(&mut self) -> TAMP3E_W<'_>

Bit 5 - Tamper 3 detection enable

pub fn tamp3trg(&mut self) -> TAMP3TRG_W<'_>

Bit 6 - Active level for tamper 3

pub fn tampts(&mut self) -> TAMPTS_W<'_>

Bit 7 - Activate timestamp on tamper detection event

pub fn tampfreq(&mut self) -> TAMPFREQ_W<'_>

Bits 8:10 - Tamper sampling frequency

pub fn tampflt(&mut self) -> TAMPFLT_W<'_>

Bits 11:12 - Tamper filter count

pub fn tampprch(&mut self) -> TAMPPRCH_W<'_>

Bits 13:14 - Tamper precharge duration

pub fn tamppudis(&mut self) -> TAMPPUDIS_W<'_>

Bit 15 - TAMPER pull-up disable

pub fn tamp1ie(&mut self) -> TAMP1IE_W<'_>

Bit 16 - Tamper 1 interrupt enable

pub fn tamp1noerase(&mut self) -> TAMP1NOERASE_W<'_>

Bit 17 - Tamper 1 no erase

pub fn tamp1mf(&mut self) -> TAMP1MF_W<'_>

Bit 18 - Tamper 1 mask flag

pub fn tamp2ie(&mut self) -> TAMP2IE_W<'_>

Bit 19 - Tamper 2 interrupt enable

pub fn tamp2noerase(&mut self) -> TAMP2NOERASE_W<'_>

Bit 20 - Tamper 2 no erase

pub fn tamp2mf(&mut self) -> TAMP2MF_W<'_>

Bit 21 - Tamper 2 mask flag

pub fn tamp3ie(&mut self) -> TAMP3IE_W<'_>

Bit 22 - Tamper 3 interrupt enable

pub fn tamp3noerase(&mut self) -> TAMP3NOERASE_W<'_>

Bit 23 - Tamper 3 no erase

pub fn tamp3mf(&mut self) -> TAMP3MF_W<'_>

Bit 24 - Tamper 3 mask flag

impl W<u32, Reg<u32, _ALRMASSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _ALRMBSSR>>

pub fn maskss(&mut self) -> MASKSS_W<'_>

Bits 24:27 - Mask the most-significant bits starting at this bit

pub fn ss(&mut self) -> SS_W<'_>

Bits 0:14 - Sub seconds value

impl W<u32, Reg<u32, _OR>>

pub fn rtc_alarm_type(&mut self) -> RTC_ALARM_TYPE_W<'_>

Bit 0 - RTC_ALARM on PC13 output type

pub fn rtc_out_rmp(&mut self) -> RTC_OUT_RMP_W<'_>

Bit 1 - RTC_OUT remap

impl W<u32, Reg<u32, _BKPR>>

pub fn bkp(&mut self) -> BKP_W<'_>

Bits 0:31 - BKP

impl W<u32, Reg<u32, _CR>>

pub fn rxdma(&mut self) -> RXDMA_W<'_>

Bit 0 - Reception DMA enable

pub fn txdma(&mut self) -> TXDMA_W<'_>

Bit 1 - Transmission DMA enable

pub fn rxmode(&mut self) -> RXMODE_W<'_>

Bit 2 - Reception buffering mode

pub fn txmode(&mut self) -> TXMODE_W<'_>

Bit 3 - Transmission buffering mode

pub fn lpbk(&mut self) -> LPBK_W<'_>

Bit 4 - Loopback mode enable

pub fn swpme(&mut self) -> SWPME_W<'_>

Bit 5 - Single wire protocol master interface enable

pub fn deact(&mut self) -> DEACT_W<'_>

Bit 10 - Single wire protocol master interface deactivate

impl W<u32, Reg<u32, _BRR>>

pub fn br(&mut self) -> BR_W<'_>

Bits 0:5 - Bitrate prescaler

impl W<u32, Reg<u32, _ICR>>

pub fn crxbff(&mut self) -> CRXBFF_W<'_>

Bit 0 - Clear receive buffer full flag

pub fn ctxbef(&mut self) -> CTXBEF_W<'_>

Bit 1 - Clear transmit buffer empty flag

pub fn crxberf(&mut self) -> CRXBERF_W<'_>

Bit 2 - Clear receive CRC error flag

pub fn crxovrf(&mut self) -> CRXOVRF_W<'_>

Bit 3 - Clear receive overrun error flag

pub fn ctxunrf(&mut self) -> CTXUNRF_W<'_>

Bit 4 - Clear transmit underrun error flag

pub fn ctcf(&mut self) -> CTCF_W<'_>

Bit 7 - Clear transfer complete flag

pub fn csrf(&mut self) -> CSRF_W<'_>

Bit 8 - Clear slave resume flag

impl W<u32, Reg<u32, _IER>>

pub fn rxbfie(&mut self) -> RXBFIE_W<'_>

Bit 0 - Receive buffer full interrupt enable

pub fn txbeie(&mut self) -> TXBEIE_W<'_>

Bit 1 - Transmit buffer empty interrupt enable

pub fn rxberie(&mut self) -> RXBERIE_W<'_>

Bit 2 - Receive CRC error interrupt enable

pub fn rxovrie(&mut self) -> RXOVRIE_W<'_>

Bit 3 - Receive overrun error interrupt enable

pub fn txunrie(&mut self) -> TXUNRIE_W<'_>

Bit 4 - Transmit underrun error interrupt enable

pub fn rie(&mut self) -> RIE_W<'_>

Bit 5 - Receive interrupt enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Transmit interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 7 - Transmit complete interrupt enable

pub fn srie(&mut self) -> SRIE_W<'_>

Bit 8 - Slave resume interrupt enable

impl W<u32, Reg<u32, _TDR>>

pub fn td(&mut self) -> TD_W<'_>

Bits 0:31 - Transmit data

impl W<u32, Reg<u32, _OR>>

pub fn swp_tbyp(&mut self) -> SWP_TBYP_W<'_>

Bit 0 - SWP transceiver bypass

pub fn swp_class(&mut self) -> SWP_CLASS_W<'_>

Bit 1 - SWP class selection

impl W<u32, Reg<u32, _OPAMP1_CSR>>

pub fn opaen(&mut self) -> OPAEN_W<'_>

Bit 0 - Operational amplifier Enable

pub fn opalpm(&mut self) -> OPALPM_W<'_>

Bit 1 - Operational amplifier Low Power Mode

pub fn opamode(&mut self) -> OPAMODE_W<'_>

Bits 2:3 - Operational amplifier PGA mode

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 4:5 - Operational amplifier Programmable amplifier gain value

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 8:9 - Inverting input selection

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bit 10 - Non inverted input selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 12 - Calibration mode enabled

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bit 13 - Calibration selection

pub fn usertrim(&mut self) -> USERTRIM_W<'_>

Bit 14 - allows to switch from AOP offset trimmed values to AOP offset

pub fn calout(&mut self) -> CALOUT_W<'_>

Bit 15 - Operational amplifier calibration output

pub fn opa_range(&mut self) -> OPA_RANGE_W<'_>

Bit 31 - Operational amplifier power supply range for stability

impl W<u32, Reg<u32, _OPAMP1_OTR>>

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 0:4 - Trim for NMOS differential pairs

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 8:12 - Trim for PMOS differential pairs

impl W<u32, Reg<u32, _OPAMP1_LPOTR>>

pub fn trimlpoffsetn(&mut self) -> TRIMLPOFFSETN_W<'_>

Bits 0:4 - Trim for NMOS differential pairs

pub fn trimlpoffsetp(&mut self) -> TRIMLPOFFSETP_W<'_>

Bits 8:12 - Trim for PMOS differential pairs

impl W<u32, Reg<u32, _OPAMP2_CSR>>

pub fn opaen(&mut self) -> OPAEN_W<'_>

Bit 0 - Operational amplifier Enable

pub fn opalpm(&mut self) -> OPALPM_W<'_>

Bit 1 - Operational amplifier Low Power Mode

pub fn opamode(&mut self) -> OPAMODE_W<'_>

Bits 2:3 - Operational amplifier PGA mode

pub fn pga_gain(&mut self) -> PGA_GAIN_W<'_>

Bits 4:5 - Operational amplifier Programmable amplifier gain value

pub fn vm_sel(&mut self) -> VM_SEL_W<'_>

Bits 8:9 - Inverting input selection

pub fn vp_sel(&mut self) -> VP_SEL_W<'_>

Bit 10 - Non inverted input selection

pub fn calon(&mut self) -> CALON_W<'_>

Bit 12 - Calibration mode enabled

pub fn calsel(&mut self) -> CALSEL_W<'_>

Bit 13 - Calibration selection

pub fn usertrim(&mut self) -> USERTRIM_W<'_>

Bit 14 - allows to switch from AOP offset trimmed values to AOP offset

pub fn calout(&mut self) -> CALOUT_W<'_>

Bit 15 - Operational amplifier calibration output

impl W<u32, Reg<u32, _OPAMP2_OTR>>

pub fn trimoffsetn(&mut self) -> TRIMOFFSETN_W<'_>

Bits 0:4 - Trim for NMOS differential pairs

pub fn trimoffsetp(&mut self) -> TRIMOFFSETP_W<'_>

Bits 8:12 - Trim for PMOS differential pairs

impl W<u32, Reg<u32, _OPAMP2_LPOTR>>

pub fn trimlpoffsetn(&mut self) -> TRIMLPOFFSETN_W<'_>

Bits 0:4 - Trim for NMOS differential pairs

pub fn trimlpoffsetp(&mut self) -> TRIMLPOFFSETP_W<'_>

Bits 8:12 - Trim for PMOS differential pairs

impl W<u32, Reg<u32, _CR>>

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 8:13 - HSI48 oscillator smooth trimming

pub fn swsync(&mut self) -> SWSYNC_W<'_>

Bit 7 - Generate software SYNC event

pub fn autotrimen(&mut self) -> AUTOTRIMEN_W<'_>

Bit 6 - Automatic trimming enable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 5 - Frequency error counter enable

pub fn esyncie(&mut self) -> ESYNCIE_W<'_>

Bit 3 - Expected SYNC interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 2 - Synchronization or trimming error interrupt enable

pub fn syncwarnie(&mut self) -> SYNCWARNIE_W<'_>

Bit 1 - SYNC warning interrupt enable

pub fn syncokie(&mut self) -> SYNCOKIE_W<'_>

Bit 0 - SYNC event OK interrupt enable

impl W<u32, Reg<u32, _CFGR>>

pub fn syncpol(&mut self) -> SYNCPOL_W<'_>

Bit 31 - SYNC polarity selection

pub fn syncsrc(&mut self) -> SYNCSRC_W<'_>

Bits 28:29 - SYNC signal source selection

pub fn syncdiv(&mut self) -> SYNCDIV_W<'_>

Bits 24:26 - SYNC divider

pub fn felim(&mut self) -> FELIM_W<'_>

Bits 16:23 - Frequency error limit

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:15 - Counter reload value

impl W<u32, Reg<u32, _ICR>>

pub fn esyncc(&mut self) -> ESYNCC_W<'_>

Bit 3 - Expected SYNC clear flag

pub fn errc(&mut self) -> ERRC_W<'_>

Bit 2 - Error clear flag

pub fn syncwarnc(&mut self) -> SYNCWARNC_W<'_>

Bit 1 - SYNC warning clear flag

pub fn syncokc(&mut self) -> SYNCOKC_W<'_>

Bit 0 - SYNC event OK clear flag

impl W<u32, Reg<u32, _EP0R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP1R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP2R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP3R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP4R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP5R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP6R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _EP7R>>

pub fn ea(&mut self) -> EA_W<'_>

Bits 0:3 - Endpoint address

pub fn stat_tx(&mut self) -> STAT_TX_W<'_>

Bits 4:5 - Status bits, for transmission transfers

pub fn dtog_tx(&mut self) -> DTOG_TX_W<'_>

Bit 6 - Data Toggle, for transmission transfers

pub fn ctr_tx(&mut self) -> CTR_TX_W<'_>

Bit 7 - Correct Transfer for transmission

pub fn ep_kind(&mut self) -> EP_KIND_W<'_>

Bit 8 - Endpoint kind

pub fn ep_type(&mut self) -> EP_TYPE_W<'_>

Bits 9:10 - Endpoint type

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 11 - Setup transaction completed

pub fn stat_rx(&mut self) -> STAT_RX_W<'_>

Bits 12:13 - Status bits, for reception transfers

pub fn dtog_rx(&mut self) -> DTOG_RX_W<'_>

Bit 14 - Data Toggle, for reception transfers

pub fn ctr_rx(&mut self) -> CTR_RX_W<'_>

Bit 15 - Correct transfer for reception

impl W<u32, Reg<u32, _CNTR>>

pub fn fres(&mut self) -> FRES_W<'_>

Bit 0 - Force USB Reset

pub fn pdwn(&mut self) -> PDWN_W<'_>

Bit 1 - Power down

pub fn lpmode(&mut self) -> LPMODE_W<'_>

Bit 2 - Low-power mode

pub fn fsusp(&mut self) -> FSUSP_W<'_>

Bit 3 - Force suspend

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 4 - Resume request

pub fn l1resume(&mut self) -> L1RESUME_W<'_>

Bit 5 - LPM L1 Resume request

pub fn l1reqm(&mut self) -> L1REQM_W<'_>

Bit 7 - LPM L1 state request interrupt mask

pub fn esofm(&mut self) -> ESOFM_W<'_>

Bit 8 - Expected start of frame interrupt mask

pub fn sofm(&mut self) -> SOFM_W<'_>

Bit 9 - Start of frame interrupt mask

pub fn resetm(&mut self) -> RESETM_W<'_>

Bit 10 - USB reset interrupt mask

pub fn suspm(&mut self) -> SUSPM_W<'_>

Bit 11 - Suspend mode interrupt mask

pub fn wkupm(&mut self) -> WKUPM_W<'_>

Bit 12 - Wakeup interrupt mask

pub fn errm(&mut self) -> ERRM_W<'_>

Bit 13 - Error interrupt mask

pub fn pmaovrm(&mut self) -> PMAOVRM_W<'_>

Bit 14 - Packet memory area over / underrun interrupt mask

pub fn ctrm(&mut self) -> CTRM_W<'_>

Bit 15 - Correct transfer interrupt mask

impl W<u32, Reg<u32, _ISTR>>

pub fn l1req(&mut self) -> L1REQ_W<'_>

Bit 7 - LPM L1 state request

pub fn esof(&mut self) -> ESOF_W<'_>

Bit 8 - Expected start frame

pub fn sof(&mut self) -> SOF_W<'_>

Bit 9 - start of frame

pub fn reset(&mut self) -> RESET_W<'_>

Bit 10 - reset request

pub fn susp(&mut self) -> SUSP_W<'_>

Bit 11 - Suspend mode request

pub fn wkup(&mut self) -> WKUP_W<'_>

Bit 12 - Wakeup

pub fn err(&mut self) -> ERR_W<'_>

Bit 13 - Error

pub fn pmaovr(&mut self) -> PMAOVR_W<'_>

Bit 14 - Packet memory area over / underrun

impl W<u32, Reg<u32, _DADDR>>

pub fn add(&mut self) -> ADD_W<'_>

Bits 0:6 - Device address

pub fn ef(&mut self) -> EF_W<'_>

Bit 7 - Enable function

impl W<u32, Reg<u32, _BTABLE>>

pub fn btable(&mut self) -> BTABLE_W<'_>

Bits 3:15 - Buffer table

impl W<u32, Reg<u32, _CR>>

pub fn prescaler(&mut self) -> PRESCALER_W<'_>

Bits 24:31 - Clock prescaler

pub fn pmm(&mut self) -> PMM_W<'_>

Bit 23 - Polling match mode

pub fn apms(&mut self) -> APMS_W<'_>

Bit 22 - Automatic poll mode stop

pub fn toie(&mut self) -> TOIE_W<'_>

Bit 20 - TimeOut interrupt enable

pub fn smie(&mut self) -> SMIE_W<'_>

Bit 19 - Status match interrupt enable

pub fn ftie(&mut self) -> FTIE_W<'_>

Bit 18 - FIFO threshold interrupt enable

pub fn tcie(&mut self) -> TCIE_W<'_>

Bit 17 - Transfer complete interrupt enable

pub fn teie(&mut self) -> TEIE_W<'_>

Bit 16 - Transfer error interrupt enable

pub fn fthres(&mut self) -> FTHRES_W<'_>

Bits 8:12 - IFO threshold level

pub fn fsel(&mut self) -> FSEL_W<'_>

Bit 7 - FLASH memory selection

pub fn dfm(&mut self) -> DFM_W<'_>

Bit 6 - Dual-flash mode

pub fn sshift(&mut self) -> SSHIFT_W<'_>

Bit 4 - Sample shift

pub fn tcen(&mut self) -> TCEN_W<'_>

Bit 3 - Timeout counter enable

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 2 - DMA enable

pub fn abort(&mut self) -> ABORT_W<'_>

Bit 1 - Abort request

pub fn en(&mut self) -> EN_W<'_>

Bit 0 - Enable

impl W<u32, Reg<u32, _DCR>>

pub fn fsize(&mut self) -> FSIZE_W<'_>

Bits 16:20 - FLASH memory size

pub fn csht(&mut self) -> CSHT_W<'_>

Bits 8:10 - Chip select high time

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bit 0 - Mode 0 / mode 3

impl W<u32, Reg<u32, _FCR>>

pub fn ctof(&mut self) -> CTOF_W<'_>

Bit 4 - Clear timeout flag

pub fn csmf(&mut self) -> CSMF_W<'_>

Bit 3 - Clear status match flag

pub fn ctcf(&mut self) -> CTCF_W<'_>

Bit 1 - Clear transfer complete flag

pub fn ctef(&mut self) -> CTEF_W<'_>

Bit 0 - Clear transfer error flag

impl W<u32, Reg<u32, _DLR>>

pub fn dl(&mut self) -> DL_W<'_>

Bits 0:31 - Data length

impl W<u32, Reg<u32, _CCR>>

pub fn ddrm(&mut self) -> DDRM_W<'_>

Bit 31 - Double data rate mode

pub fn dhhc(&mut self) -> DHHC_W<'_>

Bit 30 - DDR hold half cycle

pub fn sioo(&mut self) -> SIOO_W<'_>

Bit 28 - Send instruction only once mode

pub fn fmode(&mut self) -> FMODE_W<'_>

Bits 26:27 - Functional mode

pub fn dmode(&mut self) -> DMODE_W<'_>

Bits 24:25 - Data mode

pub fn dcyc(&mut self) -> DCYC_W<'_>

Bits 18:22 - Number of dummy cycles

pub fn absize(&mut self) -> ABSIZE_W<'_>

Bits 16:17 - Alternate bytes size

pub fn abmode(&mut self) -> ABMODE_W<'_>

Bits 14:15 - Alternate bytes mode

pub fn adsize(&mut self) -> ADSIZE_W<'_>

Bits 12:13 - Address size

pub fn admode(&mut self) -> ADMODE_W<'_>

Bits 10:11 - Address mode

pub fn imode(&mut self) -> IMODE_W<'_>

Bits 8:9 - Instruction mode

pub fn instruction(&mut self) -> INSTRUCTION_W<'_>

Bits 0:7 - Instruction

impl W<u32, Reg<u32, _AR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 0:31 - Address

impl W<u32, Reg<u32, _ABR>>

pub fn alternate(&mut self) -> ALTERNATE_W<'_>

Bits 0:31 - ALTERNATE

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _PSMKR>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 0:31 - Status mask

impl W<u32, Reg<u32, _PSMAR>>

pub fn match_(&mut self) -> MATCH_W<'_>

Bits 0:31 - Status match

impl W<u32, Reg<u32, _PIR>>

pub fn interval(&mut self) -> INTERVAL_W<'_>

Bits 0:15 - Polling interval

impl W<u32, Reg<u32, _LPTR>>

pub fn timeout(&mut self) -> TIMEOUT_W<'_>

Bits 0:15 - Timeout period

impl W<u32, Reg<u32, _BCR1>>

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn cclken(&mut self) -> CCLKEN_W<'_>

Bit 20 - CCLKEN

pub fn wfdis(&mut self) -> WFDIS_W<'_>

Bit 21 - Write FIFO Disable

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _BTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - BUSTURN

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

impl W<u32, Reg<u32, _BCR>>

pub fn cburstrw(&mut self) -> CBURSTRW_W<'_>

Bit 19 - CBURSTRW

pub fn asyncwait(&mut self) -> ASYNCWAIT_W<'_>

Bit 15 - ASYNCWAIT

pub fn extmod(&mut self) -> EXTMOD_W<'_>

Bit 14 - EXTMOD

pub fn waiten(&mut self) -> WAITEN_W<'_>

Bit 13 - WAITEN

pub fn wren(&mut self) -> WREN_W<'_>

Bit 12 - WREN

pub fn waitcfg(&mut self) -> WAITCFG_W<'_>

Bit 11 - WAITCFG

pub fn wrapmod(&mut self) -> WRAPMOD_W<'_>

Bit 10 - WRAPMOD

pub fn waitpol(&mut self) -> WAITPOL_W<'_>

Bit 9 - WAITPOL

pub fn bursten(&mut self) -> BURSTEN_W<'_>

Bit 8 - BURSTEN

pub fn faccen(&mut self) -> FACCEN_W<'_>

Bit 6 - FACCEN

pub fn mwid(&mut self) -> MWID_W<'_>

Bits 4:5 - MWID

pub fn mtyp(&mut self) -> MTYP_W<'_>

Bits 2:3 - MTYP

pub fn muxen(&mut self) -> MUXEN_W<'_>

Bit 1 - MUXEN

pub fn mbken(&mut self) -> MBKEN_W<'_>

Bit 0 - MBKEN

pub fn wfdis(&mut self) -> WFDIS_W<'_>

Bit 21 - Write FIFO disable

pub fn cclken(&mut self) -> CCLKEN_W<'_>

Bit 20 - CCLKEN

pub fn cpsize(&mut self) -> CPSIZE_W<'_>

Bits 16:18 - CRAM page size

impl W<u32, Reg<u32, _PCR>>

pub fn eccps(&mut self) -> ECCPS_W<'_>

Bits 17:19 - ECCPS

pub fn tar(&mut self) -> TAR_W<'_>

Bits 13:16 - TAR

pub fn tclr(&mut self) -> TCLR_W<'_>

Bits 9:12 - TCLR

pub fn eccen(&mut self) -> ECCEN_W<'_>

Bit 6 - ECCEN

pub fn pwid(&mut self) -> PWID_W<'_>

Bits 4:5 - PWID

pub fn ptyp(&mut self) -> PTYP_W<'_>

Bit 3 - PTYP

pub fn pbken(&mut self) -> PBKEN_W<'_>

Bit 2 - PBKEN

pub fn pwaiten(&mut self) -> PWAITEN_W<'_>

Bit 1 - PWAITEN

impl W<u32, Reg<u32, _SR>>

pub fn ifen(&mut self) -> IFEN_W<'_>

Bit 5 - IFEN

pub fn ilen(&mut self) -> ILEN_W<'_>

Bit 4 - ILEN

pub fn iren(&mut self) -> IREN_W<'_>

Bit 3 - IREN

pub fn ifs(&mut self) -> IFS_W<'_>

Bit 2 - IFS

pub fn ils(&mut self) -> ILS_W<'_>

Bit 1 - ILS

pub fn irs(&mut self) -> IRS_W<'_>

Bit 0 - IRS

impl W<u32, Reg<u32, _PMEM>>

pub fn memhiz(&mut self) -> MEMHIZ_W<'_>

Bits 24:31 - MEMHIZx

pub fn memhold(&mut self) -> MEMHOLD_W<'_>

Bits 16:23 - MEMHOLDx

pub fn memwait(&mut self) -> MEMWAIT_W<'_>

Bits 8:15 - MEMWAITx

pub fn memset(&mut self) -> MEMSET_W<'_>

Bits 0:7 - MEMSETx

impl W<u32, Reg<u32, _PATT>>

pub fn atthiz(&mut self) -> ATTHIZ_W<'_>

Bits 24:31 - ATTHIZx

pub fn atthold(&mut self) -> ATTHOLD_W<'_>

Bits 16:23 - ATTHOLDx

pub fn attwait(&mut self) -> ATTWAIT_W<'_>

Bits 8:15 - ATTWAITx

pub fn attset(&mut self) -> ATTSET_W<'_>

Bits 0:7 - ATTSETx

impl W<u32, Reg<u32, _BWTR>>

pub fn accmod(&mut self) -> ACCMOD_W<'_>

Bits 28:29 - ACCMOD

pub fn datlat(&mut self) -> DATLAT_W<'_>

Bits 24:27 - DATLAT

pub fn clkdiv(&mut self) -> CLKDIV_W<'_>

Bits 20:23 - CLKDIV

pub fn datast(&mut self) -> DATAST_W<'_>

Bits 8:15 - DATAST

pub fn addhld(&mut self) -> ADDHLD_W<'_>

Bits 4:7 - ADDHLD

pub fn addset(&mut self) -> ADDSET_W<'_>

Bits 0:3 - ADDSET

pub fn busturn(&mut self) -> BUSTURN_W<'_>

Bits 16:19 - Bus turnaround phase duration

impl W<u32, Reg<u32, _CFGR1>>

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>

Bit 31 - DFSDMEN

pub fn ckoutsrc(&mut self) -> CKOUTSRC_W<'_>

Bit 30 - CKOUTSRC

pub fn ckoutdiv(&mut self) -> CKOUTDIV_W<'_>

Bits 16:23 - CKOUTDIV

pub fn datpack(&mut self) -> DATPACK_W<'_>

Bits 14:15 - DATPACK

pub fn datmpx(&mut self) -> DATMPX_W<'_>

Bits 12:13 - DATMPX

pub fn chinsel(&mut self) -> CHINSEL_W<'_>

Bit 8 - CHINSEL

pub fn chen(&mut self) -> CHEN_W<'_>

Bit 7 - CHEN

pub fn ckaben(&mut self) -> CKABEN_W<'_>

Bit 6 - CKABEN

pub fn scden(&mut self) -> SCDEN_W<'_>

Bit 5 - SCDEN

pub fn spicksel(&mut self) -> SPICKSEL_W<'_>

Bits 2:3 - SPICKSEL

pub fn sitp(&mut self) -> SITP_W<'_>

Bits 0:1 - SITP

impl W<u32, Reg<u32, _CFGR2>>

pub fn offset(&mut self) -> OFFSET_W<'_>

Bits 8:31 - OFFSET

pub fn dtrbs(&mut self) -> DTRBS_W<'_>

Bits 3:7 - DTRBS

impl W<u32, Reg<u32, _AWSCDR>>

pub fn awford(&mut self) -> AWFORD_W<'_>

Bits 22:23 - AWFORD

pub fn awfosr(&mut self) -> AWFOSR_W<'_>

Bits 16:20 - AWFOSR

pub fn bkscd(&mut self) -> BKSCD_W<'_>

Bits 12:15 - BKSCD

pub fn scdt(&mut self) -> SCDT_W<'_>

Bits 0:7 - SCDT

impl W<u32, Reg<u32, _WDATR>>

pub fn wdata(&mut self) -> WDATA_W<'_>

Bits 0:15 - WDATA

impl W<u32, Reg<u32, _DATINR>>

pub fn indat1(&mut self) -> INDAT1_W<'_>

Bits 16:31 - INDAT1

pub fn indat0(&mut self) -> INDAT0_W<'_>

Bits 0:15 - INDAT0

impl W<u32, Reg<u32, _CR2>>

pub fn awfsel(&mut self) -> AWFSEL_W<'_>

Bit 30 - Analog watchdog fast mode select

pub fn fast(&mut self) -> FAST_W<'_>

Bit 29 - Fast conversion mode selection for regular conversions

pub fn rch(&mut self) -> RCH_W<'_>

Bits 24:26 - Regular channel selection

pub fn rdmaen(&mut self) -> RDMAEN_W<'_>

Bit 21 - DMA channel enabled to read data for the regular conversion

pub fn rsync(&mut self) -> RSYNC_W<'_>

Bit 19 - Launch regular conversion synchronously with DFSDM0

pub fn rcont(&mut self) -> RCONT_W<'_>

Bit 18 - Continuous mode selection for regular conversions

pub fn rswstart(&mut self) -> RSWSTART_W<'_>

Bit 17 - Software start of a conversion on the regular channel

pub fn jexten(&mut self) -> JEXTEN_W<'_>

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn jextsel(&mut self) -> JEXTSEL_W<'_>

Bits 8:10 - Trigger signal selection for launching injected conversions

pub fn jdmaen(&mut self) -> JDMAEN_W<'_>

Bit 5 - DMA channel enabled to read data for the injected channel group

pub fn jscan(&mut self) -> JSCAN_W<'_>

Bit 4 - Scanning conversion mode for injected conversions

pub fn jsync(&mut self) -> JSYNC_W<'_>

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

pub fn jswstart(&mut self) -> JSWSTART_W<'_>

Bit 1 - Start a conversion of the injected group of channels

pub fn dfen(&mut self) -> DFEN_W<'_>

Bit 0 - DFSDM enable

impl W<u32, Reg<u32, _ICR>>

pub fn clrscdf(&mut self) -> CLRSCDF_W<'_>

Bits 24:31 - Clear the short-circuit detector flag

pub fn clrckabf(&mut self) -> CLRCKABF_W<'_>

Bits 16:23 - Clear the clock absence flag

pub fn clrrovrf(&mut self) -> CLRROVRF_W<'_>

Bit 3 - Clear the regular conversion overrun flag

pub fn clrjovrf(&mut self) -> CLRJOVRF_W<'_>

Bit 2 - Clear the injected conversion overrun flag

impl W<u32, Reg<u32, _JCHGR>>

pub fn jchg(&mut self) -> JCHG_W<'_>

Bits 0:7 - Injected channel group selection

impl W<u32, Reg<u32, _FCR>>

pub fn ford(&mut self) -> FORD_W<'_>

Bits 29:31 - Sinc filter order

pub fn fosr(&mut self) -> FOSR_W<'_>

Bits 16:25 - Sinc filter oversampling ratio (decimation rate)

pub fn iosr(&mut self) -> IOSR_W<'_>

Bits 0:7 - Integrator oversampling ratio (averaging length)

impl W<u32, Reg<u32, _AWHTR>>

pub fn awht(&mut self) -> AWHT_W<'_>

Bits 8:31 - Analog watchdog high threshold

pub fn bkawh(&mut self) -> BKAWH_W<'_>

Bits 0:3 - Break signal assignment to analog watchdog high threshold event

impl W<u32, Reg<u32, _AWLTR>>

pub fn awlt(&mut self) -> AWLT_W<'_>

Bits 8:31 - Analog watchdog low threshold

pub fn bkawl(&mut self) -> BKAWL_W<'_>

Bits 0:3 - Break signal assignment to analog watchdog low threshold event

impl W<u32, Reg<u32, _AWCFR>>

pub fn clrawhtf(&mut self) -> CLRAWHTF_W<'_>

Bits 8:15 - Clear the analog watchdog high threshold flag

pub fn clrawltf(&mut self) -> CLRAWLTF_W<'_>

Bits 0:7 - Clear the analog watchdog low threshold flag

impl W<u32, Reg<u32, _DFSDM0_CR2>>

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 16:23 - Analog watchdog channel selection

pub fn exch(&mut self) -> EXCH_W<'_>

Bits 8:15 - Extremes detector channel selection

pub fn ckabie(&mut self) -> CKABIE_W<'_>

Bit 6 - Clock absence interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>

Bit 5 - Short-circuit detector interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 4 - Analog watchdog interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>

Bit 3 - Regular data overrun interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>

Bit 2 - Injected data overrun interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>

Bit 1 - Regular end of conversion interrupt enable

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 0 - Injected end of conversion interrupt enable

impl W<u32, Reg<u32, _DFSDM1_CR2>>

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 16:23 - Analog watchdog channel selection

pub fn exch(&mut self) -> EXCH_W<'_>

Bits 8:15 - Extremes detector channel selection

pub fn ckabie(&mut self) -> CKABIE_W<'_>

Bit 6 - Clock absence interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>

Bit 5 - Short-circuit detector interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 4 - Analog watchdog interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>

Bit 3 - Regular data overrun interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>

Bit 2 - Injected data overrun interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>

Bit 1 - Regular end of conversion interrupt enable

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 0 - Injected end of conversion interrupt enable

impl W<u32, Reg<u32, _DFSDM2_CR2>>

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 16:23 - Analog watchdog channel selection

pub fn exch(&mut self) -> EXCH_W<'_>

Bits 8:15 - Extremes detector channel selection

pub fn ckabie(&mut self) -> CKABIE_W<'_>

Bit 6 - Clock absence interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>

Bit 5 - Short-circuit detector interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 4 - Analog watchdog interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>

Bit 3 - Regular data overrun interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>

Bit 2 - Injected data overrun interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>

Bit 1 - Regular end of conversion interrupt enable

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 0 - Injected end of conversion interrupt enable

impl W<u32, Reg<u32, _DFSDM3_CR2>>

pub fn awdch(&mut self) -> AWDCH_W<'_>

Bits 16:23 - Analog watchdog channel selection

pub fn exch(&mut self) -> EXCH_W<'_>

Bits 8:15 - Extremes detector channel selection

pub fn ckabie(&mut self) -> CKABIE_W<'_>

Bit 6 - Clock absence interrupt enable

pub fn scdie(&mut self) -> SCDIE_W<'_>

Bit 5 - Short-circuit detector interrupt enable

pub fn awdie(&mut self) -> AWDIE_W<'_>

Bit 4 - Analog watchdog interrupt enable

pub fn rovrie(&mut self) -> ROVRIE_W<'_>

Bit 3 - Regular data overrun interrupt enable

pub fn jovrie(&mut self) -> JOVRIE_W<'_>

Bit 2 - Injected data overrun interrupt enable

pub fn reocie(&mut self) -> REOCIE_W<'_>

Bit 1 - Regular end of conversion interrupt enable

pub fn jeocie(&mut self) -> JEOCIE_W<'_>

Bit 0 - Injected end of conversion interrupt enable

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ois4(&mut self) -> OIS4_W<'_>

Bit 14 - Output Idle state 4

pub fn ois3n(&mut self) -> OIS3N_W<'_>

Bit 13 - Output Idle state 3

pub fn ois3(&mut self) -> OIS3_W<'_>

Bit 12 - Output Idle state 3

pub fn ois2n(&mut self) -> OIS2N_W<'_>

Bit 11 - Output Idle state 2

pub fn ois2(&mut self) -> OIS2_W<'_>

Bit 10 - Output Idle state 2

pub fn ois1n(&mut self) -> OIS1N_W<'_>

Bit 9 - Output Idle state 1

pub fn ois1(&mut self) -> OIS1_W<'_>

Bit 8 - Output Idle state 1

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

pub fn ccus(&mut self) -> CCUS_W<'_>

Bit 2 - Capture/compare control update selection

pub fn ccpc(&mut self) -> CCPC_W<'_>

Bit 0 - Capture/compare preloaded control

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

pub fn bie(&mut self) -> BIE_W<'_>

Bit 7 - Break interrupt enable

pub fn comie(&mut self) -> COMIE_W<'_>

Bit 5 - COM interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn bif(&mut self) -> BIF_W<'_>

Bit 7 - Break interrupt flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn comif(&mut self) -> COMIF_W<'_>

Bit 5 - COM interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn bg(&mut self) -> BG_W<'_>

Bit 7 - Break generation

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn comg(&mut self) -> COMG_W<'_>

Bit 5 - Capture/Compare control update generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output Compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output Compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output Compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output Compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output Compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output Compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output Compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output Compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3ne(&mut self) -> CC3NE_W<'_>

Bit 10 - Capture/Compare 3 complementary output enable

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2ne(&mut self) -> CC2NE_W<'_>

Bit 6 - Capture/Compare 2 complementary output enable

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1ne(&mut self) -> CC1NE_W<'_>

Bit 2 - Capture/Compare 1 complementary output enable

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _RCR>>

pub fn rep(&mut self) -> REP_W<'_>

Bits 0:7 - Repetition counter value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _BDTR>>

pub fn moe(&mut self) -> MOE_W<'_>

Bit 15 - Main output enable

pub fn aoe(&mut self) -> AOE_W<'_>

Bit 14 - Automatic output enable

pub fn bkp(&mut self) -> BKP_W<'_>

Bit 13 - Break polarity

pub fn bke(&mut self) -> BKE_W<'_>

Bit 12 - Break enable

pub fn ossr(&mut self) -> OSSR_W<'_>

Bit 11 - Off-state selection for Run mode

pub fn ossi(&mut self) -> OSSI_W<'_>

Bit 10 - Off-state selection for Idle mode

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 8:9 - Lock configuration

pub fn dtg(&mut self) -> DTG_W<'_>

Bits 0:7 - Dead-time generator setup

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR1>>

pub fn etr_adc2_rmp(&mut self) -> ETR_ADC2_RMP_W<'_>

Bits 0:1 - External trigger remap on ADC2 analog watchdog

pub fn etr_adc3_rmp(&mut self) -> ETR_ADC3_RMP_W<'_>

Bits 2:3 - External trigger remap on ADC3 analog watchdog

pub fn ti1_rmp(&mut self) -> TI1_RMP_W<'_>

Bit 4 - Input Capture 1 remap

impl W<u32, Reg<u32, _CCMR3_OUTPUT>>

pub fn oc6m_bit3(&mut self) -> OC6M_BIT3_W<'_>

Bit 24 - Output Compare 6 mode bit 3

pub fn oc5m_bit3(&mut self) -> OC5M_BIT3_W<'_>

Bits 16:18 - Output Compare 5 mode bit 3

pub fn oc6ce(&mut self) -> OC6CE_W<'_>

Bit 15 - Output compare 6 clear enable

pub fn oc6m(&mut self) -> OC6M_W<'_>

Bits 12:14 - Output compare 6 mode

pub fn oc6pe(&mut self) -> OC6PE_W<'_>

Bit 11 - Output compare 6 preload enable

pub fn oc6fe(&mut self) -> OC6FE_W<'_>

Bit 10 - Output compare 6 fast enable

pub fn oc5ce(&mut self) -> OC5CE_W<'_>

Bit 7 - Output compare 5 clear enable

pub fn oc5m(&mut self) -> OC5M_W<'_>

Bits 4:6 - Output compare 5 mode

pub fn oc5pe(&mut self) -> OC5PE_W<'_>

Bit 3 - Output compare 5 preload enable

pub fn oc5fe(&mut self) -> OC5FE_W<'_>

Bit 2 - Output compare 5 fast enable

impl W<u32, Reg<u32, _CCR5>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare value

pub fn gc5c1(&mut self) -> GC5C1_W<'_>

Bit 29 - Group Channel 5 and Channel 1

pub fn gc5c2(&mut self) -> GC5C2_W<'_>

Bit 30 - Group Channel 5 and Channel 2

pub fn gc5c3(&mut self) -> GC5C3_W<'_>

Bit 31 - Group Channel 5 and Channel 3

impl W<u32, Reg<u32, _CCR6>>

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare value

impl W<u32, Reg<u32, _OR2>>

pub fn bkine(&mut self) -> BKINE_W<'_>

Bit 0 - BRK BKIN input enable

pub fn bkcmp1e(&mut self) -> BKCMP1E_W<'_>

Bit 1 - BRK COMP1 enable

pub fn bkcmp2e(&mut self) -> BKCMP2E_W<'_>

Bit 2 - BRK COMP2 enable

pub fn bkdfbk2e(&mut self) -> BKDFBK2E_W<'_>

Bit 8 - BRK DFSDM_BREAK2 enable

pub fn bkinp(&mut self) -> BKINP_W<'_>

Bit 9 - BRK BKIN input polarity

pub fn bkcmp1p(&mut self) -> BKCMP1P_W<'_>

Bit 10 - BRK COMP1 input polarity

pub fn bkcmp2p(&mut self) -> BKCMP2P_W<'_>

Bit 11 - BRK COMP2 input polarity

pub fn etrsel(&mut self) -> ETRSEL_W<'_>

Bits 14:16 - ETR source selection

impl W<u32, Reg<u32, _OR3>>

pub fn bk2ine(&mut self) -> BK2INE_W<'_>

Bit 0 - BRK2 BKIN input enable

pub fn bk2cmp1e(&mut self) -> BK2CMP1E_W<'_>

Bit 1 - BRK2 COMP1 enable

pub fn bk2cmp2e(&mut self) -> BK2CMP2E_W<'_>

Bit 2 - BRK2 COMP2 enable

pub fn bk2dfbk3e(&mut self) -> BK2DFBK3E_W<'_>

Bit 8 - BRK2 DFSDM_BREAK3 enable

pub fn bk2inp(&mut self) -> BK2INP_W<'_>

Bit 9 - BRK2 BKIN input polarity

pub fn bk2cmp1p(&mut self) -> BK2CMP1P_W<'_>

Bit 10 - BRK2 COMP1 input polarity

pub fn bk2cmp2p(&mut self) -> BK2CMP2P_W<'_>

Bit 11 - BRK2 COMP2 input polarity

impl W<u32, Reg<u32, _CR>>

pub fn pllsai2on(&mut self) -> PLLSAI2ON_W<'_>

Bit 28 - SAI2 PLL enable

pub fn pllsai1on(&mut self) -> PLLSAI1ON_W<'_>

Bit 26 - SAI1 PLL enable

pub fn pllon(&mut self) -> PLLON_W<'_>

Bit 24 - Main PLL enable

pub fn csson(&mut self) -> CSSON_W<'_>

Bit 19 - Clock security system enable

pub fn hsebyp(&mut self) -> HSEBYP_W<'_>

Bit 18 - HSE crystal oscillator bypass

pub fn hseon(&mut self) -> HSEON_W<'_>

Bit 16 - HSE clock enable

pub fn hsiasfs(&mut self) -> HSIASFS_W<'_>

Bit 11 - HSI automatic start from Stop

pub fn hsikeron(&mut self) -> HSIKERON_W<'_>

Bit 9 - HSI always enable for peripheral kernels

pub fn hsion(&mut self) -> HSION_W<'_>

Bit 8 - HSI clock enable

pub fn msirange(&mut self) -> MSIRANGE_W<'_>

Bits 4:7 - MSI clock ranges

pub fn msirgsel(&mut self) -> MSIRGSEL_W<'_>

Bit 3 - MSI clock range selection

pub fn msipllen(&mut self) -> MSIPLLEN_W<'_>

Bit 2 - MSI clock PLL enable

pub fn msion(&mut self) -> MSION_W<'_>

Bit 0 - MSI clock enable

impl W<u32, Reg<u32, _ICSCR>>

pub fn hsitrim(&mut self) -> HSITRIM_W<'_>

Bits 24:28 - HSI clock trimming

pub fn msitrim(&mut self) -> MSITRIM_W<'_>

Bits 8:15 - MSI clock trimming

impl W<u32, Reg<u32, _CFGR>>

pub fn mcosel(&mut self) -> MCOSEL_W<'_>

Bits 24:26 - Microcontroller clock output

pub fn stopwuck(&mut self) -> STOPWUCK_W<'_>

Bit 15 - Wakeup from Stop and CSS backup clock selection

pub fn ppre2(&mut self) -> PPRE2_W<'_>

Bits 11:13 - APB high-speed prescaler (APB2)

pub fn ppre1(&mut self) -> PPRE1_W<'_>

Bits 8:10 - PB low-speed prescaler (APB1)

pub fn hpre(&mut self) -> HPRE_W<'_>

Bits 4:7 - AHB prescaler

pub fn sw(&mut self) -> SW_W<'_>

Bits 0:1 - System clock switch

impl W<u32, Reg<u32, _PLLCFGR>>

pub fn pllr(&mut self) -> PLLR_W<'_>

Bits 25:26 - Main PLL division factor for PLLCLK (system clock)

pub fn pllren(&mut self) -> PLLREN_W<'_>

Bit 24 - Main PLL PLLCLK output enable

pub fn pllq(&mut self) -> PLLQ_W<'_>

Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)

pub fn pllqen(&mut self) -> PLLQEN_W<'_>

Bit 20 - Main PLL PLLUSB1CLK output enable

pub fn pllp(&mut self) -> PLLP_W<'_>

Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)

pub fn pllpen(&mut self) -> PLLPEN_W<'_>

Bit 16 - Main PLL PLLSAI3CLK output enable

pub fn plln(&mut self) -> PLLN_W<'_>

Bits 8:14 - Main PLL multiplication factor for VCO

pub fn pllm(&mut self) -> PLLM_W<'_>

Bits 4:6 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock

pub fn pllsrc(&mut self) -> PLLSRC_W<'_>

Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source

impl W<u32, Reg<u32, _PLLSAI1CFGR>>

pub fn pllsai1r(&mut self) -> PLLSAI1R_W<'_>

Bits 25:26 - PLLSAI1 division factor for PLLADC1CLK (ADC clock)

pub fn pllsai1ren(&mut self) -> PLLSAI1REN_W<'_>

Bit 24 - PLLSAI1 PLLADC1CLK output enable

pub fn pllsai1q(&mut self) -> PLLSAI1Q_W<'_>

Bits 21:22 - SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)

pub fn pllsai1qen(&mut self) -> PLLSAI1QEN_W<'_>

Bit 20 - SAI1PLL PLLUSB2CLK output enable

pub fn pllsai1p(&mut self) -> PLLSAI1P_W<'_>

Bit 17 - SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)

pub fn pllsai1pen(&mut self) -> PLLSAI1PEN_W<'_>

Bit 16 - SAI1PLL PLLSAI1CLK output enable

pub fn pllsai1n(&mut self) -> PLLSAI1N_W<'_>

Bits 8:14 - SAI1PLL multiplication factor for VCO

impl W<u32, Reg<u32, _PLLSAI2CFGR>>

pub fn pllsai2r(&mut self) -> PLLSAI2R_W<'_>

Bits 25:26 - PLLSAI2 division factor for PLLADC2CLK (ADC clock)

pub fn pllsai2ren(&mut self) -> PLLSAI2REN_W<'_>

Bit 24 - PLLSAI2 PLLADC2CLK output enable

pub fn pllsai2p(&mut self) -> PLLSAI2P_W<'_>

Bit 17 - SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)

pub fn pllsai2pen(&mut self) -> PLLSAI2PEN_W<'_>

Bit 16 - SAI2PLL PLLSAI2CLK output enable

pub fn pllsai2n(&mut self) -> PLLSAI2N_W<'_>

Bits 8:14 - SAI2PLL multiplication factor for VCO

impl W<u32, Reg<u32, _CIER>>

pub fn lsecssie(&mut self) -> LSECSSIE_W<'_>

Bit 9 - LSE clock security system interrupt enable

pub fn pllsai2rdyie(&mut self) -> PLLSAI2RDYIE_W<'_>

Bit 7 - PLLSAI2 ready interrupt enable

pub fn pllsai1rdyie(&mut self) -> PLLSAI1RDYIE_W<'_>

Bit 6 - PLLSAI1 ready interrupt enable

pub fn pllrdyie(&mut self) -> PLLRDYIE_W<'_>

Bit 5 - PLL ready interrupt enable

pub fn hserdyie(&mut self) -> HSERDYIE_W<'_>

Bit 4 - HSE ready interrupt enable

pub fn hsirdyie(&mut self) -> HSIRDYIE_W<'_>

Bit 3 - HSI ready interrupt enable

pub fn msirdyie(&mut self) -> MSIRDYIE_W<'_>

Bit 2 - MSI ready interrupt enable

pub fn lserdyie(&mut self) -> LSERDYIE_W<'_>

Bit 1 - LSE ready interrupt enable

pub fn lsirdyie(&mut self) -> LSIRDYIE_W<'_>

Bit 0 - LSI ready interrupt enable

impl W<u32, Reg<u32, _CICR>>

pub fn lsecssc(&mut self) -> LSECSSC_W<'_>

Bit 9 - LSE Clock security system interrupt clear

pub fn cssc(&mut self) -> CSSC_W<'_>

Bit 8 - Clock security system interrupt clear

pub fn pllsai2rdyc(&mut self) -> PLLSAI2RDYC_W<'_>

Bit 7 - PLLSAI2 ready interrupt clear

pub fn pllsai1rdyc(&mut self) -> PLLSAI1RDYC_W<'_>

Bit 6 - PLLSAI1 ready interrupt clear

pub fn pllrdyc(&mut self) -> PLLRDYC_W<'_>

Bit 5 - PLL ready interrupt clear

pub fn hserdyc(&mut self) -> HSERDYC_W<'_>

Bit 4 - HSE ready interrupt clear

pub fn hsirdyc(&mut self) -> HSIRDYC_W<'_>

Bit 3 - HSI ready interrupt clear

pub fn msirdyc(&mut self) -> MSIRDYC_W<'_>

Bit 2 - MSI ready interrupt clear

pub fn lserdyc(&mut self) -> LSERDYC_W<'_>

Bit 1 - LSE ready interrupt clear

pub fn lsirdyc(&mut self) -> LSIRDYC_W<'_>

Bit 0 - LSI ready interrupt clear

impl W<u32, Reg<u32, _AHB1RSTR>>

pub fn tscrst(&mut self) -> TSCRST_W<'_>

Bit 16 - Touch Sensing Controller reset

pub fn crcrst(&mut self) -> CRCRST_W<'_>

Bit 11 - CRC reset

pub fn flashrst(&mut self) -> FLASHRST_W<'_>

Bit 8 - Flash memory interface reset

pub fn dma2rst(&mut self) -> DMA2RST_W<'_>

Bit 1 - DMA2 reset

pub fn dma1rst(&mut self) -> DMA1RST_W<'_>

Bit 0 - DMA1 reset

impl W<u32, Reg<u32, _AHB2RSTR>>

pub fn rngrst(&mut self) -> RNGRST_W<'_>

Bit 18 - Random number generator reset

pub fn aesrst(&mut self) -> AESRST_W<'_>

Bit 16 - AES hardware accelerator reset

pub fn adcrst(&mut self) -> ADCRST_W<'_>

Bit 13 - ADC reset

pub fn otgfsrst(&mut self) -> OTGFSRST_W<'_>

Bit 12 - USB OTG FS reset

pub fn gpiohrst(&mut self) -> GPIOHRST_W<'_>

Bit 7 - IO port H reset

pub fn gpiogrst(&mut self) -> GPIOGRST_W<'_>

Bit 6 - IO port G reset

pub fn gpiofrst(&mut self) -> GPIOFRST_W<'_>

Bit 5 - IO port F reset

pub fn gpioerst(&mut self) -> GPIOERST_W<'_>

Bit 4 - IO port E reset

pub fn gpiodrst(&mut self) -> GPIODRST_W<'_>

Bit 3 - IO port D reset

pub fn gpiocrst(&mut self) -> GPIOCRST_W<'_>

Bit 2 - IO port C reset

pub fn gpiobrst(&mut self) -> GPIOBRST_W<'_>

Bit 1 - IO port B reset

pub fn gpioarst(&mut self) -> GPIOARST_W<'_>

Bit 0 - IO port A reset

impl W<u32, Reg<u32, _AHB3RSTR>>

pub fn qspirst(&mut self) -> QSPIRST_W<'_>

Bit 8 - Quad SPI memory interface reset

pub fn fmcrst(&mut self) -> FMCRST_W<'_>

Bit 0 - Flexible memory controller reset

impl W<u32, Reg<u32, _APB1RSTR1>>

pub fn lptim1rst(&mut self) -> LPTIM1RST_W<'_>

Bit 31 - Low Power Timer 1 reset

pub fn opamprst(&mut self) -> OPAMPRST_W<'_>

Bit 30 - OPAMP interface reset

pub fn dac1rst(&mut self) -> DAC1RST_W<'_>

Bit 29 - DAC1 interface reset

pub fn pwrrst(&mut self) -> PWRRST_W<'_>

Bit 28 - Power interface reset

pub fn can1rst(&mut self) -> CAN1RST_W<'_>

Bit 25 - CAN1 reset

pub fn i2c3rst(&mut self) -> I2C3RST_W<'_>

Bit 23 - I2C3 reset

pub fn i2c2rst(&mut self) -> I2C2RST_W<'_>

Bit 22 - I2C2 reset

pub fn i2c1rst(&mut self) -> I2C1RST_W<'_>

Bit 21 - I2C1 reset

pub fn uart5rst(&mut self) -> UART5RST_W<'_>

Bit 20 - UART5 reset

pub fn uart4rst(&mut self) -> UART4RST_W<'_>

Bit 19 - UART4 reset

pub fn usart3rst(&mut self) -> USART3RST_W<'_>

Bit 18 - USART3 reset

pub fn usart2rst(&mut self) -> USART2RST_W<'_>

Bit 17 - USART2 reset

pub fn spi3rst(&mut self) -> SPI3RST_W<'_>

Bit 15 - SPI3 reset

pub fn spi2rst(&mut self) -> SPI2RST_W<'_>

Bit 14 - SPI2 reset

pub fn lcdrst(&mut self) -> LCDRST_W<'_>

Bit 9 - LCD interface reset

pub fn tim7rst(&mut self) -> TIM7RST_W<'_>

Bit 5 - TIM7 timer reset

pub fn tim6rst(&mut self) -> TIM6RST_W<'_>

Bit 4 - TIM6 timer reset

pub fn tim5rst(&mut self) -> TIM5RST_W<'_>

Bit 3 - TIM5 timer reset

pub fn tim4rst(&mut self) -> TIM4RST_W<'_>

Bit 2 - TIM3 timer reset

pub fn tim3rst(&mut self) -> TIM3RST_W<'_>

Bit 1 - TIM3 timer reset

pub fn tim2rst(&mut self) -> TIM2RST_W<'_>

Bit 0 - TIM2 timer reset

impl W<u32, Reg<u32, _APB1RSTR2>>

pub fn lptim2rst(&mut self) -> LPTIM2RST_W<'_>

Bit 5 - Low-power timer 2 reset

pub fn swpmi1rst(&mut self) -> SWPMI1RST_W<'_>

Bit 2 - Single wire protocol reset

pub fn lpuart1rst(&mut self) -> LPUART1RST_W<'_>

Bit 0 - Low-power UART 1 reset

impl W<u32, Reg<u32, _APB2RSTR>>

pub fn dfsdmrst(&mut self) -> DFSDMRST_W<'_>

Bit 24 - Digital filters for sigma-delata modulators (DFSDM) reset

pub fn sai2rst(&mut self) -> SAI2RST_W<'_>

Bit 22 - Serial audio interface 2 (SAI2) reset

pub fn sai1rst(&mut self) -> SAI1RST_W<'_>

Bit 21 - Serial audio interface 1 (SAI1) reset

pub fn tim17rst(&mut self) -> TIM17RST_W<'_>

Bit 18 - TIM17 timer reset

pub fn tim16rst(&mut self) -> TIM16RST_W<'_>

Bit 17 - TIM16 timer reset

pub fn tim15rst(&mut self) -> TIM15RST_W<'_>

Bit 16 - TIM15 timer reset

pub fn usart1rst(&mut self) -> USART1RST_W<'_>

Bit 14 - USART1 reset

pub fn tim8rst(&mut self) -> TIM8RST_W<'_>

Bit 13 - TIM8 timer reset

pub fn spi1rst(&mut self) -> SPI1RST_W<'_>

Bit 12 - SPI1 reset

pub fn tim1rst(&mut self) -> TIM1RST_W<'_>

Bit 11 - TIM1 timer reset

pub fn sdmmcrst(&mut self) -> SDMMCRST_W<'_>

Bit 10 - SDMMC reset

pub fn syscfgrst(&mut self) -> SYSCFGRST_W<'_>

Bit 0 - System configuration (SYSCFG) reset

impl W<u32, Reg<u32, _AHB1ENR>>

pub fn tscen(&mut self) -> TSCEN_W<'_>

Bit 16 - Touch Sensing Controller clock enable

pub fn crcen(&mut self) -> CRCEN_W<'_>

Bit 11 - CRC clock enable

pub fn flashen(&mut self) -> FLASHEN_W<'_>

Bit 8 - Flash memory interface clock enable

pub fn dma2en(&mut self) -> DMA2EN_W<'_>

Bit 1 - DMA2 clock enable

pub fn dma1en(&mut self) -> DMA1EN_W<'_>

Bit 0 - DMA1 clock enable

impl W<u32, Reg<u32, _AHB2ENR>>

pub fn rngen(&mut self) -> RNGEN_W<'_>

Bit 18 - Random Number Generator clock enable

pub fn aesen(&mut self) -> AESEN_W<'_>

Bit 16 - AES accelerator clock enable

pub fn adcen(&mut self) -> ADCEN_W<'_>

Bit 13 - ADC clock enable

pub fn otgfsen(&mut self) -> OTGFSEN_W<'_>

Bit 12 - OTG full speed clock enable

pub fn gpiohen(&mut self) -> GPIOHEN_W<'_>

Bit 7 - IO port H clock enable

pub fn gpiogen(&mut self) -> GPIOGEN_W<'_>

Bit 6 - IO port G clock enable

pub fn gpiofen(&mut self) -> GPIOFEN_W<'_>

Bit 5 - IO port F clock enable

pub fn gpioeen(&mut self) -> GPIOEEN_W<'_>

Bit 4 - IO port E clock enable

pub fn gpioden(&mut self) -> GPIODEN_W<'_>

Bit 3 - IO port D clock enable

pub fn gpiocen(&mut self) -> GPIOCEN_W<'_>

Bit 2 - IO port C clock enable

pub fn gpioben(&mut self) -> GPIOBEN_W<'_>

Bit 1 - IO port B clock enable

pub fn gpioaen(&mut self) -> GPIOAEN_W<'_>

Bit 0 - IO port A clock enable

impl W<u32, Reg<u32, _AHB3ENR>>

pub fn qspien(&mut self) -> QSPIEN_W<'_>

Bit 8 - QSPIEN

pub fn fmcen(&mut self) -> FMCEN_W<'_>

Bit 0 - Flexible memory controller clock enable

impl W<u32, Reg<u32, _APB1ENR1>>

pub fn lptim1en(&mut self) -> LPTIM1EN_W<'_>

Bit 31 - Low power timer 1 clock enable

pub fn opampen(&mut self) -> OPAMPEN_W<'_>

Bit 30 - OPAMP interface clock enable

pub fn dac1en(&mut self) -> DAC1EN_W<'_>

Bit 29 - DAC1 interface clock enable

pub fn pwren(&mut self) -> PWREN_W<'_>

Bit 28 - Power interface clock enable

pub fn can1en(&mut self) -> CAN1EN_W<'_>

Bit 25 - CAN1 clock enable

pub fn i2c3en(&mut self) -> I2C3EN_W<'_>

Bit 23 - I2C3 clock enable

pub fn i2c2en(&mut self) -> I2C2EN_W<'_>

Bit 22 - I2C2 clock enable

pub fn i2c1en(&mut self) -> I2C1EN_W<'_>

Bit 21 - I2C1 clock enable

pub fn uart5en(&mut self) -> UART5EN_W<'_>

Bit 20 - UART5 clock enable

pub fn uart4en(&mut self) -> UART4EN_W<'_>

Bit 19 - UART4 clock enable

pub fn usart3en(&mut self) -> USART3EN_W<'_>

Bit 18 - USART3 clock enable

pub fn usart2en(&mut self) -> USART2EN_W<'_>

Bit 17 - USART2 clock enable

pub fn spi3en(&mut self) -> SPI3EN_W<'_>

Bit 15 - SPI peripheral 3 clock enable

pub fn spi2en(&mut self) -> SPI2EN_W<'_>

Bit 14 - SPI2 clock enable

pub fn wwdgen(&mut self) -> WWDGEN_W<'_>

Bit 11 - Window watchdog clock enable

pub fn lcden(&mut self) -> LCDEN_W<'_>

Bit 9 - LCD clock enable

pub fn tim7en(&mut self) -> TIM7EN_W<'_>

Bit 5 - TIM7 timer clock enable

pub fn tim6en(&mut self) -> TIM6EN_W<'_>

Bit 4 - TIM6 timer clock enable

pub fn tim5en(&mut self) -> TIM5EN_W<'_>

Bit 3 - TIM5 timer clock enable

pub fn tim4en(&mut self) -> TIM4EN_W<'_>

Bit 2 - TIM4 timer clock enable

pub fn tim3en(&mut self) -> TIM3EN_W<'_>

Bit 1 - TIM3 timer clock enable

pub fn tim2en(&mut self) -> TIM2EN_W<'_>

Bit 0 - TIM2 timer clock enable

pub fn rtcapben(&mut self) -> RTCAPBEN_W<'_>

Bit 10 - Enables the real time clock (RTC) peripheral

impl W<u32, Reg<u32, _APB1ENR2>>

pub fn lptim2en(&mut self) -> LPTIM2EN_W<'_>

Bit 5 - LPTIM2EN

pub fn swpmi1en(&mut self) -> SWPMI1EN_W<'_>

Bit 2 - Single wire protocol clock enable

pub fn lpuart1en(&mut self) -> LPUART1EN_W<'_>

Bit 0 - Low power UART 1 clock enable

impl W<u32, Reg<u32, _APB2ENR>>

pub fn dfsdmen(&mut self) -> DFSDMEN_W<'_>

Bit 24 - DFSDM timer clock enable

pub fn sai2en(&mut self) -> SAI2EN_W<'_>

Bit 22 - SAI2 clock enable

pub fn sai1en(&mut self) -> SAI1EN_W<'_>

Bit 21 - SAI1 clock enable

pub fn tim17en(&mut self) -> TIM17EN_W<'_>

Bit 18 - TIM17 timer clock enable

pub fn tim16en(&mut self) -> TIM16EN_W<'_>

Bit 17 - TIM16 timer clock enable

pub fn tim15en(&mut self) -> TIM15EN_W<'_>

Bit 16 - TIM15 timer clock enable

pub fn usart1en(&mut self) -> USART1EN_W<'_>

Bit 14 - USART1clock enable

pub fn tim8en(&mut self) -> TIM8EN_W<'_>

Bit 13 - TIM8 timer clock enable

pub fn spi1en(&mut self) -> SPI1EN_W<'_>

Bit 12 - SPI1 clock enable

pub fn tim1en(&mut self) -> TIM1EN_W<'_>

Bit 11 - TIM1 timer clock enable

pub fn sdmmcen(&mut self) -> SDMMCEN_W<'_>

Bit 10 - SDMMC clock enable

pub fn firewallen(&mut self) -> FIREWALLEN_W<'_>

Bit 7 - Firewall clock enable

pub fn syscfgen(&mut self) -> SYSCFGEN_W<'_>

Bit 0 - SYSCFG clock enable

impl W<u32, Reg<u32, _AHB1SMENR>>

pub fn tscsmen(&mut self) -> TSCSMEN_W<'_>

Bit 16 - Touch Sensing Controller clocks enable during Sleep and Stop modes

pub fn crcsmen(&mut self) -> CRCSMEN_W<'_>

Bit 11 - CRCSMEN

pub fn sram1smen(&mut self) -> SRAM1SMEN_W<'_>

Bit 9 - SRAM1 interface clocks enable during Sleep and Stop modes

pub fn flashsmen(&mut self) -> FLASHSMEN_W<'_>

Bit 8 - Flash memory interface clocks enable during Sleep and Stop modes

pub fn dma2smen(&mut self) -> DMA2SMEN_W<'_>

Bit 1 - DMA2 clocks enable during Sleep and Stop modes

pub fn dma1smen(&mut self) -> DMA1SMEN_W<'_>

Bit 0 - DMA1 clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _AHB2SMENR>>

pub fn rngsmen(&mut self) -> RNGSMEN_W<'_>

Bit 18 - Random Number Generator clocks enable during Sleep and Stop modes

pub fn aessmen(&mut self) -> AESSMEN_W<'_>

Bit 16 - AES accelerator clocks enable during Sleep and Stop modes

pub fn adcfssmen(&mut self) -> ADCFSSMEN_W<'_>

Bit 13 - ADC clocks enable during Sleep and Stop modes

pub fn otgfssmen(&mut self) -> OTGFSSMEN_W<'_>

Bit 12 - OTG full speed clocks enable during Sleep and Stop modes

pub fn sram2smen(&mut self) -> SRAM2SMEN_W<'_>

Bit 9 - SRAM2 interface clocks enable during Sleep and Stop modes

pub fn gpiohsmen(&mut self) -> GPIOHSMEN_W<'_>

Bit 7 - IO port H clocks enable during Sleep and Stop modes

pub fn gpiogsmen(&mut self) -> GPIOGSMEN_W<'_>

Bit 6 - IO port G clocks enable during Sleep and Stop modes

pub fn gpiofsmen(&mut self) -> GPIOFSMEN_W<'_>

Bit 5 - IO port F clocks enable during Sleep and Stop modes

pub fn gpioesmen(&mut self) -> GPIOESMEN_W<'_>

Bit 4 - IO port E clocks enable during Sleep and Stop modes

pub fn gpiodsmen(&mut self) -> GPIODSMEN_W<'_>

Bit 3 - IO port D clocks enable during Sleep and Stop modes

pub fn gpiocsmen(&mut self) -> GPIOCSMEN_W<'_>

Bit 2 - IO port C clocks enable during Sleep and Stop modes

pub fn gpiobsmen(&mut self) -> GPIOBSMEN_W<'_>

Bit 1 - IO port B clocks enable during Sleep and Stop modes

pub fn gpioasmen(&mut self) -> GPIOASMEN_W<'_>

Bit 0 - IO port A clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _AHB3SMENR>>

pub fn qspismen(&mut self) -> QSPISMEN_W<'_>

Bit 8 - QSPISMEN

pub fn fmcsmen(&mut self) -> FMCSMEN_W<'_>

Bit 0 - Flexible memory controller clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _APB1SMENR1>>

pub fn lptim1smen(&mut self) -> LPTIM1SMEN_W<'_>

Bit 31 - Low power timer 1 clocks enable during Sleep and Stop modes

pub fn opampsmen(&mut self) -> OPAMPSMEN_W<'_>

Bit 30 - OPAMP interface clocks enable during Sleep and Stop modes

pub fn dac1smen(&mut self) -> DAC1SMEN_W<'_>

Bit 29 - DAC1 interface clocks enable during Sleep and Stop modes

pub fn pwrsmen(&mut self) -> PWRSMEN_W<'_>

Bit 28 - Power interface clocks enable during Sleep and Stop modes

pub fn can1smen(&mut self) -> CAN1SMEN_W<'_>

Bit 25 - CAN1 clocks enable during Sleep and Stop modes

pub fn i2c3smen(&mut self) -> I2C3SMEN_W<'_>

Bit 23 - I2C3 clocks enable during Sleep and Stop modes

pub fn i2c2smen(&mut self) -> I2C2SMEN_W<'_>

Bit 22 - I2C2 clocks enable during Sleep and Stop modes

pub fn i2c1smen(&mut self) -> I2C1SMEN_W<'_>

Bit 21 - I2C1 clocks enable during Sleep and Stop modes

pub fn uart5smen(&mut self) -> UART5SMEN_W<'_>

Bit 20 - UART5 clocks enable during Sleep and Stop modes

pub fn uart4smen(&mut self) -> UART4SMEN_W<'_>

Bit 19 - UART4 clocks enable during Sleep and Stop modes

pub fn usart3smen(&mut self) -> USART3SMEN_W<'_>

Bit 18 - USART3 clocks enable during Sleep and Stop modes

pub fn usart2smen(&mut self) -> USART2SMEN_W<'_>

Bit 17 - USART2 clocks enable during Sleep and Stop modes

pub fn sp3smen(&mut self) -> SP3SMEN_W<'_>

Bit 15 - SPI3 clocks enable during Sleep and Stop modes

pub fn spi2smen(&mut self) -> SPI2SMEN_W<'_>

Bit 14 - SPI2 clocks enable during Sleep and Stop modes

pub fn wwdgsmen(&mut self) -> WWDGSMEN_W<'_>

Bit 11 - Window watchdog clocks enable during Sleep and Stop modes

pub fn lcdsmen(&mut self) -> LCDSMEN_W<'_>

Bit 9 - LCD clocks enable during Sleep and Stop modes

pub fn tim7smen(&mut self) -> TIM7SMEN_W<'_>

Bit 5 - TIM7 timer clocks enable during Sleep and Stop modes

pub fn tim6smen(&mut self) -> TIM6SMEN_W<'_>

Bit 4 - TIM6 timer clocks enable during Sleep and Stop modes

pub fn tim5smen(&mut self) -> TIM5SMEN_W<'_>

Bit 3 - TIM5 timer clocks enable during Sleep and Stop modes

pub fn tim4smen(&mut self) -> TIM4SMEN_W<'_>

Bit 2 - TIM4 timer clocks enable during Sleep and Stop modes

pub fn tim3smen(&mut self) -> TIM3SMEN_W<'_>

Bit 1 - TIM3 timer clocks enable during Sleep and Stop modes

pub fn tim2smen(&mut self) -> TIM2SMEN_W<'_>

Bit 0 - TIM2 timer clocks enable during Sleep and Stop modes

pub fn rtcapbsmen(&mut self) -> RTCAPBSMEN_W<'_>

Bit 10 - RTC APB clock enable during Sleep and Stop modes

impl W<u32, Reg<u32, _APB1SMENR2>>

pub fn lptim2smen(&mut self) -> LPTIM2SMEN_W<'_>

Bit 5 - LPTIM2SMEN

pub fn swpmi1smen(&mut self) -> SWPMI1SMEN_W<'_>

Bit 2 - Single wire protocol clocks enable during Sleep and Stop modes

pub fn lpuart1smen(&mut self) -> LPUART1SMEN_W<'_>

Bit 0 - Low power UART 1 clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _APB2SMENR>>

pub fn dfsdmsmen(&mut self) -> DFSDMSMEN_W<'_>

Bit 24 - DFSDM timer clocks enable during Sleep and Stop modes

pub fn sai2smen(&mut self) -> SAI2SMEN_W<'_>

Bit 22 - SAI2 clocks enable during Sleep and Stop modes

pub fn sai1smen(&mut self) -> SAI1SMEN_W<'_>

Bit 21 - SAI1 clocks enable during Sleep and Stop modes

pub fn tim17smen(&mut self) -> TIM17SMEN_W<'_>

Bit 18 - TIM17 timer clocks enable during Sleep and Stop modes

pub fn tim16smen(&mut self) -> TIM16SMEN_W<'_>

Bit 17 - TIM16 timer clocks enable during Sleep and Stop modes

pub fn tim15smen(&mut self) -> TIM15SMEN_W<'_>

Bit 16 - TIM15 timer clocks enable during Sleep and Stop modes

pub fn usart1smen(&mut self) -> USART1SMEN_W<'_>

Bit 14 - USART1clocks enable during Sleep and Stop modes

pub fn tim8smen(&mut self) -> TIM8SMEN_W<'_>

Bit 13 - TIM8 timer clocks enable during Sleep and Stop modes

pub fn spi1smen(&mut self) -> SPI1SMEN_W<'_>

Bit 12 - SPI1 clocks enable during Sleep and Stop modes

pub fn tim1smen(&mut self) -> TIM1SMEN_W<'_>

Bit 11 - TIM1 timer clocks enable during Sleep and Stop modes

pub fn sdmmcsmen(&mut self) -> SDMMCSMEN_W<'_>

Bit 10 - SDMMC clocks enable during Sleep and Stop modes

pub fn syscfgsmen(&mut self) -> SYSCFGSMEN_W<'_>

Bit 0 - SYSCFG clocks enable during Sleep and Stop modes

impl W<u32, Reg<u32, _CCIPR>>

pub fn dfsdmsel(&mut self) -> DFSDMSEL_W<'_>

Bit 31 - DFSDM clock source selection

pub fn swpmi1sel(&mut self) -> SWPMI1SEL_W<'_>

Bit 30 - SWPMI1 clock source selection

pub fn adcsel(&mut self) -> ADCSEL_W<'_>

Bits 28:29 - ADCs clock source selection

pub fn clk48sel(&mut self) -> CLK48SEL_W<'_>

Bits 26:27 - 48 MHz clock source selection

pub fn sai2sel(&mut self) -> SAI2SEL_W<'_>

Bits 24:25 - SAI2 clock source selection

pub fn sai1sel(&mut self) -> SAI1SEL_W<'_>

Bits 22:23 - SAI1 clock source selection

pub fn lptim2sel(&mut self) -> LPTIM2SEL_W<'_>

Bits 20:21 - Low power timer 2 clock source selection

pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<'_>

Bits 18:19 - Low power timer 1 clock source selection

pub fn i2c3sel(&mut self) -> I2C3SEL_W<'_>

Bits 16:17 - I2C3 clock source selection

pub fn i2c2sel(&mut self) -> I2C2SEL_W<'_>

Bits 14:15 - I2C2 clock source selection

pub fn i2c1sel(&mut self) -> I2C1SEL_W<'_>

Bits 12:13 - I2C1 clock source selection

pub fn lpuart1sel(&mut self) -> LPUART1SEL_W<'_>

Bits 10:11 - LPUART1 clock source selection

pub fn uart5sel(&mut self) -> UART5SEL_W<'_>

Bits 8:9 - UART5 clock source selection

pub fn uart4sel(&mut self) -> UART4SEL_W<'_>

Bits 6:7 - UART4 clock source selection

pub fn usart3sel(&mut self) -> USART3SEL_W<'_>

Bits 4:5 - USART3 clock source selection

pub fn usart2sel(&mut self) -> USART2SEL_W<'_>

Bits 2:3 - USART2 clock source selection

pub fn usart1sel(&mut self) -> USART1SEL_W<'_>

Bits 0:1 - USART1 clock source selection

impl W<u32, Reg<u32, _BDCR>>

pub fn lscosel(&mut self) -> LSCOSEL_W<'_>

Bit 25 - Low speed clock output selection

pub fn lscoen(&mut self) -> LSCOEN_W<'_>

Bit 24 - Low speed clock output enable

pub fn bdrst(&mut self) -> BDRST_W<'_>

Bit 16 - Backup domain software reset

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 15 - RTC clock enable

pub fn rtcsel(&mut self) -> RTCSEL_W<'_>

Bits 8:9 - RTC clock source selection

pub fn lsecsson(&mut self) -> LSECSSON_W<'_>

Bit 5 - LSECSSON

pub fn lsedrv(&mut self) -> LSEDRV_W<'_>

Bits 3:4 - SE oscillator drive capability

pub fn lsebyp(&mut self) -> LSEBYP_W<'_>

Bit 2 - LSE oscillator bypass

pub fn lseon(&mut self) -> LSEON_W<'_>

Bit 0 - LSE oscillator enable

impl W<u32, Reg<u32, _CSR>>

pub fn rmvf(&mut self) -> RMVF_W<'_>

Bit 23 - Remove reset flag

pub fn msisrange(&mut self) -> MSISRANGE_W<'_>

Bits 8:11 - SI range after Standby mode

pub fn lsion(&mut self) -> LSION_W<'_>

Bit 0 - LSI oscillator enable

impl W<u32, Reg<u32, _CRRCR>>

pub fn hsi48on(&mut self) -> HSI48ON_W<'_>

Bit 0 - Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.

impl W<u32, Reg<u32, _CCR>>

pub fn mult(&mut self) -> MULT_W<'_>

Bits 0:4 - Multi ADC mode selection

pub fn delay(&mut self) -> DELAY_W<'_>

Bits 8:11 - Delay between 2 sampling phases

pub fn dmacfg(&mut self) -> DMACFG_W<'_>

Bit 13 - DMA configuration (for multi-ADC mode)

pub fn mdma(&mut self) -> MDMA_W<'_>

Bits 14:15 - Direct memory access mode for multi ADC mode

pub fn ckmode(&mut self) -> CKMODE_W<'_>

Bits 16:17 - ADC clock mode

pub fn vrefen(&mut self) -> VREFEN_W<'_>

Bit 22 - VREFINT enable

pub fn ch18sel(&mut self) -> CH18SEL_W<'_>

Bit 23 - CH18 selection (Vbat)

pub fn ch17sel(&mut self) -> CH17SEL_W<'_>

Bit 24 - CH17 selection (temperature)

impl W<u32, Reg<u32, _CR>>

pub fn dbg_sleep(&mut self) -> DBG_SLEEP_W<'_>

Bit 0 - Debug Sleep Mode

pub fn dbg_stop(&mut self) -> DBG_STOP_W<'_>

Bit 1 - Debug Stop Mode

pub fn dbg_standby(&mut self) -> DBG_STANDBY_W<'_>

Bit 2 - Debug Standby Mode

pub fn trace_ioen(&mut self) -> TRACE_IOEN_W<'_>

Bit 5 - Trace pin assignment control

pub fn trace_mode(&mut self) -> TRACE_MODE_W<'_>

Bits 6:7 - Trace pin assignment control

impl W<u32, Reg<u32, _APB1_FZR1>>

pub fn dbg_timer2_stop(&mut self) -> DBG_TIMER2_STOP_W<'_>

Bit 0 - Debug Timer 2 stopped when Core is halted

pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W<'_>

Bit 1 - TIM3 counter stopped when core is halted

pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W<'_>

Bit 2 - TIM4 counter stopped when core is halted

pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W<'_>

Bit 3 - TIM5 counter stopped when core is halted

pub fn dbg_timer6_stop(&mut self) -> DBG_TIMER6_STOP_W<'_>

Bit 4 - Debug Timer 6 stopped when Core is halted

pub fn dbg_tim7_stop(&mut self) -> DBG_TIM7_STOP_W<'_>

Bit 5 - TIM7 counter stopped when core is halted

pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<'_>

Bit 10 - Debug RTC stopped when Core is halted

pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<'_>

Bit 11 - Debug Window Wachdog stopped when Core is halted

pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<'_>

Bit 12 - Debug Independent Wachdog stopped when Core is halted

pub fn dbg_i2c1_stop(&mut self) -> DBG_I2C1_STOP_W<'_>

Bit 21 - I2C1 SMBUS timeout mode stopped when core is halted

pub fn dbg_i2c2_stop(&mut self) -> DBG_I2C2_STOP_W<'_>

Bit 22 - I2C2 SMBUS timeout mode stopped when core is halted

pub fn dbg_i2c3_stop(&mut self) -> DBG_I2C3_STOP_W<'_>

Bit 23 - I2C3 SMBUS timeout counter stopped when core is halted

pub fn dbg_can_stop(&mut self) -> DBG_CAN_STOP_W<'_>

Bit 25 - bxCAN stopped when core is halted

pub fn dbg_lptimer_stop(&mut self) -> DBG_LPTIMER_STOP_W<'_>

Bit 31 - LPTIM1 counter stopped when core is halted

impl W<u32, Reg<u32, _APB1_FZR2>>

pub fn dbg_lptim2_stop(&mut self) -> DBG_LPTIM2_STOP_W<'_>

Bit 5 - LPTIM2 counter stopped when core is halted

impl W<u32, Reg<u32, _APB2_FZR>>

pub fn dbg_tim1_stop(&mut self) -> DBG_TIM1_STOP_W<'_>

Bit 11 - TIM1 counter stopped when core is halted

pub fn dbg_tim8_stop(&mut self) -> DBG_TIM8_STOP_W<'_>

Bit 13 - TIM8 counter stopped when core is halted

pub fn dbg_tim15_stop(&mut self) -> DBG_TIM15_STOP_W<'_>

Bit 16 - TIM15 counter stopped when core is halted

pub fn dbg_tim16_stop(&mut self) -> DBG_TIM16_STOP_W<'_>

Bit 17 - TIM16 counter stopped when core is halted

pub fn dbg_tim17_stop(&mut self) -> DBG_TIM17_STOP_W<'_>

Bit 18 - TIM17 counter stopped when core is halted

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W<'_>

Bit 0 - LSPACT

pub fn user(&mut self) -> USER_W<'_>

Bit 1 - USER

pub fn thread(&mut self) -> THREAD_W<'_>

Bit 3 - THREAD

pub fn hfrdy(&mut self) -> HFRDY_W<'_>

Bit 4 - HFRDY

pub fn mmrdy(&mut self) -> MMRDY_W<'_>

Bit 5 - MMRDY

pub fn bfrdy(&mut self) -> BFRDY_W<'_>

Bit 6 - BFRDY

pub fn monrdy(&mut self) -> MONRDY_W<'_>

Bit 8 - MONRDY

pub fn lspen(&mut self) -> LSPEN_W<'_>

Bit 30 - LSPEN

pub fn aspen(&mut self) -> ASPEN_W<'_>

Bit 31 - ASPEN

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W<'_>

Bits 3:31 - Location of unpopulated floating-point

impl W<u32, Reg<u32, _FPSCR>>

pub fn ioc(&mut self) -> IOC_W<'_>

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&mut self) -> DZC_W<'_>

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&mut self) -> OFC_W<'_>

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&mut self) -> UFC_W<'_>

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&mut self) -> IXC_W<'_>

Bit 4 - Inexact cumulative exception bit

pub fn idc(&mut self) -> IDC_W<'_>

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&mut self) -> RMODE_W<'_>

Bits 22:23 - Rounding Mode control field

pub fn fz(&mut self) -> FZ_W<'_>

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&mut self) -> DN_W<'_>

Bit 25 - Default NaN mode control bit

pub fn ahp(&mut self) -> AHP_W<'_>

Bit 26 - Alternative half-precision control bit

pub fn v(&mut self) -> V_W<'_>

Bit 28 - Overflow condition code flag

pub fn c(&mut self) -> C_W<'_>

Bit 29 - Carry condition code flag

pub fn z(&mut self) -> Z_W<'_>

Bit 30 - Zero condition code flag

pub fn n(&mut self) -> N_W<'_>

Bit 31 - Negative condition code flag

impl W<u32, Reg<u32, _CTRL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Counter enable

pub fn tickint(&mut self) -> TICKINT_W<'_>

Bit 1 - SysTick exception request enable

pub fn clksource(&mut self) -> CLKSOURCE_W<'_>

Bit 2 - Clock source selection

pub fn countflag(&mut self) -> COUNTFLAG_W<'_>

Bit 16 - COUNTFLAG

impl W<u32, Reg<u32, _LOAD>>

pub fn reload(&mut self) -> RELOAD_W<'_>

Bits 0:23 - RELOAD value

impl W<u32, Reg<u32, _VAL>>

pub fn current(&mut self) -> CURRENT_W<'_>

Bits 0:23 - Current counter value

impl W<u32, Reg<u32, _CALIB>>

pub fn tenms(&mut self) -> TENMS_W<'_>

Bits 0:23 - Calibration value

pub fn skew(&mut self) -> SKEW_W<'_>

Bit 30 - SKEW flag: Indicates whether the TENMS value is exact

pub fn noref(&mut self) -> NOREF_W<'_>

Bit 31 - NOREF flag. Reads as zero

impl W<u32, Reg<u32, _STIR>>

pub fn intid(&mut self) -> INTID_W<'_>

Bits 0:8 - Software generated interrupt ID

impl W<u32, Reg<u32, _CPACR>>

pub fn cp(&mut self) -> CP_W<'_>

Bits 20:23 - CP

impl W<u32, Reg<u32, _ACTRL>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W<'_>

Bit 0 - DISMCYCINT

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W<'_>

Bit 1 - DISDEFWBUF

pub fn disfold(&mut self) -> DISFOLD_W<'_>

Bit 2 - DISFOLD

pub fn disfpca(&mut self) -> DISFPCA_W<'_>

Bit 8 - DISFPCA

pub fn disoofp(&mut self) -> DISOOFP_W<'_>

Bit 9 - DISOOFP

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn etr_rmp(&mut self) -> ETR_RMP_W<'_>

Bits 0:2 - Timer2 ETR remap

pub fn ti4_rmp(&mut self) -> TI4_RMP_W<'_>

Bits 3:4 - Internal trigger

impl W<u32, Reg<u32, _CR1>>

pub fn ckd(&mut self) -> CKD_W<'_>

Bits 8:9 - Clock division

pub fn arpe(&mut self) -> ARPE_W<'_>

Bit 7 - Auto-reload preload enable

pub fn cms(&mut self) -> CMS_W<'_>

Bits 5:6 - Center-aligned mode selection

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Direction

pub fn opm(&mut self) -> OPM_W<'_>

Bit 3 - One-pulse mode

pub fn urs(&mut self) -> URS_W<'_>

Bit 2 - Update request source

pub fn udis(&mut self) -> UDIS_W<'_>

Bit 1 - Update disable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 0 - Counter enable

impl W<u32, Reg<u32, _CR2>>

pub fn ti1s(&mut self) -> TI1S_W<'_>

Bit 7 - TI1 selection

pub fn mms(&mut self) -> MMS_W<'_>

Bits 4:6 - Master mode selection

pub fn ccds(&mut self) -> CCDS_W<'_>

Bit 3 - Capture/compare DMA selection

impl W<u32, Reg<u32, _SMCR>>

pub fn etp(&mut self) -> ETP_W<'_>

Bit 15 - External trigger polarity

pub fn ece(&mut self) -> ECE_W<'_>

Bit 14 - External clock enable

pub fn etps(&mut self) -> ETPS_W<'_>

Bits 12:13 - External trigger prescaler

pub fn etf(&mut self) -> ETF_W<'_>

Bits 8:11 - External trigger filter

pub fn msm(&mut self) -> MSM_W<'_>

Bit 7 - Master/Slave mode

pub fn ts(&mut self) -> TS_W<'_>

Bits 4:6 - Trigger selection

pub fn sms(&mut self) -> SMS_W<'_>

Bits 0:2 - Slave mode selection

impl W<u32, Reg<u32, _DIER>>

pub fn tde(&mut self) -> TDE_W<'_>

Bit 14 - Trigger DMA request enable

pub fn comde(&mut self) -> COMDE_W<'_>

Bit 13 - COM DMA request enable

pub fn cc4de(&mut self) -> CC4DE_W<'_>

Bit 12 - Capture/Compare 4 DMA request enable

pub fn cc3de(&mut self) -> CC3DE_W<'_>

Bit 11 - Capture/Compare 3 DMA request enable

pub fn cc2de(&mut self) -> CC2DE_W<'_>

Bit 10 - Capture/Compare 2 DMA request enable

pub fn cc1de(&mut self) -> CC1DE_W<'_>

Bit 9 - Capture/Compare 1 DMA request enable

pub fn ude(&mut self) -> UDE_W<'_>

Bit 8 - Update DMA request enable

pub fn tie(&mut self) -> TIE_W<'_>

Bit 6 - Trigger interrupt enable

pub fn cc4ie(&mut self) -> CC4IE_W<'_>

Bit 4 - Capture/Compare 4 interrupt enable

pub fn cc3ie(&mut self) -> CC3IE_W<'_>

Bit 3 - Capture/Compare 3 interrupt enable

pub fn cc2ie(&mut self) -> CC2IE_W<'_>

Bit 2 - Capture/Compare 2 interrupt enable

pub fn cc1ie(&mut self) -> CC1IE_W<'_>

Bit 1 - Capture/Compare 1 interrupt enable

pub fn uie(&mut self) -> UIE_W<'_>

Bit 0 - Update interrupt enable

impl W<u32, Reg<u32, _SR>>

pub fn cc4of(&mut self) -> CC4OF_W<'_>

Bit 12 - Capture/Compare 4 overcapture flag

pub fn cc3of(&mut self) -> CC3OF_W<'_>

Bit 11 - Capture/Compare 3 overcapture flag

pub fn cc2of(&mut self) -> CC2OF_W<'_>

Bit 10 - Capture/compare 2 overcapture flag

pub fn cc1of(&mut self) -> CC1OF_W<'_>

Bit 9 - Capture/Compare 1 overcapture flag

pub fn tif(&mut self) -> TIF_W<'_>

Bit 6 - Trigger interrupt flag

pub fn cc4if(&mut self) -> CC4IF_W<'_>

Bit 4 - Capture/Compare 4 interrupt flag

pub fn cc3if(&mut self) -> CC3IF_W<'_>

Bit 3 - Capture/Compare 3 interrupt flag

pub fn cc2if(&mut self) -> CC2IF_W<'_>

Bit 2 - Capture/Compare 2 interrupt flag

pub fn cc1if(&mut self) -> CC1IF_W<'_>

Bit 1 - Capture/compare 1 interrupt flag

pub fn uif(&mut self) -> UIF_W<'_>

Bit 0 - Update interrupt flag

impl W<u32, Reg<u32, _EGR>>

pub fn tg(&mut self) -> TG_W<'_>

Bit 6 - Trigger generation

pub fn cc4g(&mut self) -> CC4G_W<'_>

Bit 4 - Capture/compare 4 generation

pub fn cc3g(&mut self) -> CC3G_W<'_>

Bit 3 - Capture/compare 3 generation

pub fn cc2g(&mut self) -> CC2G_W<'_>

Bit 2 - Capture/compare 2 generation

pub fn cc1g(&mut self) -> CC1G_W<'_>

Bit 1 - Capture/compare 1 generation

pub fn ug(&mut self) -> UG_W<'_>

Bit 0 - Update generation

impl W<u32, Reg<u32, _CCMR1_OUTPUT>>

pub fn oc2ce(&mut self) -> OC2CE_W<'_>

Bit 15 - Output compare 2 clear enable

pub fn oc2m(&mut self) -> OC2M_W<'_>

Bits 12:14 - Output compare 2 mode

pub fn oc2pe(&mut self) -> OC2PE_W<'_>

Bit 11 - Output compare 2 preload enable

pub fn oc2fe(&mut self) -> OC2FE_W<'_>

Bit 10 - Output compare 2 fast enable

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/Compare 2 selection

pub fn oc1ce(&mut self) -> OC1CE_W<'_>

Bit 7 - Output compare 1 clear enable

pub fn oc1m(&mut self) -> OC1M_W<'_>

Bits 4:6 - Output compare 1 mode

pub fn oc1pe(&mut self) -> OC1PE_W<'_>

Bit 3 - Output compare 1 preload enable

pub fn oc1fe(&mut self) -> OC1FE_W<'_>

Bit 2 - Output compare 1 fast enable

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR1_INPUT>>

pub fn ic2f(&mut self) -> IC2F_W<'_>

Bits 12:15 - Input capture 2 filter

pub fn ic2psc(&mut self) -> IC2PSC_W<'_>

Bits 10:11 - Input capture 2 prescaler

pub fn cc2s(&mut self) -> CC2S_W<'_>

Bits 8:9 - Capture/compare 2 selection

pub fn ic1f(&mut self) -> IC1F_W<'_>

Bits 4:7 - Input capture 1 filter

pub fn ic1psc(&mut self) -> IC1PSC_W<'_>

Bits 2:3 - Input capture 1 prescaler

pub fn cc1s(&mut self) -> CC1S_W<'_>

Bits 0:1 - Capture/Compare 1 selection

impl W<u32, Reg<u32, _CCMR2_OUTPUT>>

pub fn oc4ce(&mut self) -> OC4CE_W<'_>

Bit 15 - Output compare 4 clear enable

pub fn oc4m(&mut self) -> OC4M_W<'_>

Bits 12:14 - Output compare 4 mode

pub fn oc4pe(&mut self) -> OC4PE_W<'_>

Bit 11 - Output compare 4 preload enable

pub fn oc4fe(&mut self) -> OC4FE_W<'_>

Bit 10 - Output compare 4 fast enable

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn oc3ce(&mut self) -> OC3CE_W<'_>

Bit 7 - Output compare 3 clear enable

pub fn oc3m(&mut self) -> OC3M_W<'_>

Bits 4:6 - Output compare 3 mode

pub fn oc3pe(&mut self) -> OC3PE_W<'_>

Bit 3 - Output compare 3 preload enable

pub fn oc3fe(&mut self) -> OC3FE_W<'_>

Bit 2 - Output compare 3 fast enable

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCMR2_INPUT>>

pub fn ic4f(&mut self) -> IC4F_W<'_>

Bits 12:15 - Input capture 4 filter

pub fn ic4psc(&mut self) -> IC4PSC_W<'_>

Bits 10:11 - Input capture 4 prescaler

pub fn cc4s(&mut self) -> CC4S_W<'_>

Bits 8:9 - Capture/Compare 4 selection

pub fn ic3f(&mut self) -> IC3F_W<'_>

Bits 4:7 - Input capture 3 filter

pub fn ic3psc(&mut self) -> IC3PSC_W<'_>

Bits 2:3 - Input capture 3 prescaler

pub fn cc3s(&mut self) -> CC3S_W<'_>

Bits 0:1 - Capture/Compare 3 selection

impl W<u32, Reg<u32, _CCER>>

pub fn cc4np(&mut self) -> CC4NP_W<'_>

Bit 15 - Capture/Compare 4 output Polarity

pub fn cc4p(&mut self) -> CC4P_W<'_>

Bit 13 - Capture/Compare 3 output Polarity

pub fn cc4e(&mut self) -> CC4E_W<'_>

Bit 12 - Capture/Compare 4 output enable

pub fn cc3np(&mut self) -> CC3NP_W<'_>

Bit 11 - Capture/Compare 3 output Polarity

pub fn cc3p(&mut self) -> CC3P_W<'_>

Bit 9 - Capture/Compare 3 output Polarity

pub fn cc3e(&mut self) -> CC3E_W<'_>

Bit 8 - Capture/Compare 3 output enable

pub fn cc2np(&mut self) -> CC2NP_W<'_>

Bit 7 - Capture/Compare 2 output Polarity

pub fn cc2p(&mut self) -> CC2P_W<'_>

Bit 5 - Capture/Compare 2 output Polarity

pub fn cc2e(&mut self) -> CC2E_W<'_>

Bit 4 - Capture/Compare 2 output enable

pub fn cc1np(&mut self) -> CC1NP_W<'_>

Bit 3 - Capture/Compare 1 output Polarity

pub fn cc1p(&mut self) -> CC1P_W<'_>

Bit 1 - Capture/Compare 1 output Polarity

pub fn cc1e(&mut self) -> CC1E_W<'_>

Bit 0 - Capture/Compare 1 output enable

impl W<u32, Reg<u32, _CNT>>

pub fn cnt_h(&mut self) -> CNT_H_W<'_>

Bits 16:31 - High counter value (TIM2 only)

pub fn cnt(&mut self) -> CNT_W<'_>

Bits 0:15 - Counter value

impl W<u32, Reg<u32, _PSC>>

pub fn psc(&mut self) -> PSC_W<'_>

Bits 0:15 - Prescaler value

impl W<u32, Reg<u32, _ARR>>

pub fn arr_h(&mut self) -> ARR_H_W<'_>

Bits 16:31 - High Auto-reload value (TIM2 only)

pub fn arr(&mut self) -> ARR_W<'_>

Bits 0:15 - Auto-reload value

impl W<u32, Reg<u32, _CCR>>

pub fn ccr1_h(&mut self) -> CCR1_H_W<'_>

Bits 16:31 - High Capture/Compare 1 value (TIM2 only)

pub fn ccr(&mut self) -> CCR_W<'_>

Bits 0:15 - Capture/Compare 1 value

impl W<u32, Reg<u32, _DCR>>

pub fn dbl(&mut self) -> DBL_W<'_>

Bits 8:12 - DMA burst length

pub fn dba(&mut self) -> DBA_W<'_>

Bits 0:4 - DMA base address

impl W<u32, Reg<u32, _DMAR>>

pub fn dmab(&mut self) -> DMAB_W<'_>

Bits 0:15 - DMA register for burst accesses

impl W<u32, Reg<u32, _OR>>

pub fn etr_rmp(&mut self) -> ETR_RMP_W<'_>

Bits 0:2 - Timer2 ETR remap

pub fn ti4_rmp(&mut self) -> TI4_RMP_W<'_>

Bits 3:4 - Internal trigger