pub struct W<U, REG> { /* fields omitted */ }
Expand description
Register writer
Used as an argument to the closures in the write
and modify
methods of the register
pub unsafe fn bits(&mut self, bits: U) -> &mut Self
Writes raw bits to the register
impl W<u32, Reg<u32, _CR>>
Bit 0 - DAC channel1 enable
Bit 2 - DAC channel1 trigger enable
Bits 3:5 - DAC channel1 trigger selection
Bits 6:7 - DAC channel1 noise/triangle wave generation enable
Bits 8:11 - DAC channel1 mask/amplitude selector
Bit 12 - DAC channel1 DMA enable
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
Bit 14 - DAC Channel 1 calibration enable
Bit 16 - DAC channel2 enable
Bit 18 - DAC channel2 trigger enable
Bits 19:21 - DAC channel2 trigger selection
Bits 22:23 - DAC channel2 noise/triangle wave generation enable
Bits 24:27 - DAC channel2 mask/amplitude selector
Bit 28 - DAC channel2 DMA enable
Bit 29 - DAC channel2 DMA underrun interrupt enable
Bit 30 - DAC Channel 2 calibration enable
impl W<u32, Reg<u32, _SWTRIGR>>
Bit 0 - DAC channel1 software trigger
Bit 1 - DAC channel2 software trigger
impl W<u32, Reg<u32, _DHR12R1>>
Bits 0:11 - DAC channel1 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12L1>>
Bits 4:15 - DAC channel1 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8R1>>
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl W<u32, Reg<u32, _DHR12R2>>
Bits 0:11 - DAC channel2 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12L2>>
Bits 4:15 - DAC channel2 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8R2>>
Bits 0:7 - DAC channel2 8-bit right-aligned data
impl W<u32, Reg<u32, _DHR12RD>>
Bits 0:11 - DAC channel1 12-bit right-aligned data
Bits 16:27 - DAC channel2 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12LD>>
Bits 4:15 - DAC channel1 12-bit left-aligned data
Bits 20:31 - DAC channel2 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8RD>>
Bits 0:7 - DAC channel1 8-bit right-aligned data
Bits 8:15 - DAC channel2 8-bit right-aligned data
impl W<u32, Reg<u32, _SR>>
Bit 13 - DAC channel1 DMA underrun flag
Bit 29 - DAC channel2 DMA underrun flag
impl W<u32, Reg<u32, _CCR>>
Bits 0:4 - DAC Channel 1 offset trimming value
Bits 16:20 - DAC Channel 2 offset trimming value
impl W<u32, Reg<u32, _MCR>>
Bits 0:2 - DAC Channel 1 mode
Bits 16:18 - DAC Channel 2 mode
impl W<u32, Reg<u32, _SHSR1>>
Bits 0:9 - DAC Channel 1 sample Time
impl W<u32, Reg<u32, _SHSR2>>
Bits 0:9 - DAC Channel 2 sample Time
impl W<u32, Reg<u32, _SHHR>>
Bits 0:9 - DAC Channel 1 hold Time
Bits 16:25 - DAC Channel 2 hold time
impl W<u32, Reg<u32, _SHRR>>
Bits 0:7 - DAC Channel 1 refresh Time
Bits 16:23 - DAC Channel 2 refresh Time
impl W<u32, Reg<u32, _IFCR>>
Bit 27 - Channel x transfer error clear (x = 1 ..7)
Bit 26 - Channel x half transfer clear (x = 1 ..7)
Bit 25 - Channel x transfer complete clear (x = 1 ..7)
Bit 24 - Channel x global interrupt clear (x = 1 ..7)
Bit 23 - Channel x transfer error clear (x = 1 ..7)
Bit 22 - Channel x half transfer clear (x = 1 ..7)
Bit 21 - Channel x transfer complete clear (x = 1 ..7)
Bit 20 - Channel x global interrupt clear (x = 1 ..7)
Bit 19 - Channel x transfer error clear (x = 1 ..7)
Bit 18 - Channel x half transfer clear (x = 1 ..7)
Bit 17 - Channel x transfer complete clear (x = 1 ..7)
Bit 16 - Channel x global interrupt clear (x = 1 ..7)
Bit 15 - Channel x transfer error clear (x = 1 ..7)
Bit 14 - Channel x half transfer clear (x = 1 ..7)
Bit 13 - Channel x transfer complete clear (x = 1 ..7)
Bit 12 - Channel x global interrupt clear (x = 1 ..7)
Bit 11 - Channel x transfer error clear (x = 1 ..7)
Bit 10 - Channel x half transfer clear (x = 1 ..7)
Bit 9 - Channel x transfer complete clear (x = 1 ..7)
Bit 8 - Channel x global interrupt clear (x = 1 ..7)
Bit 7 - Channel x transfer error clear (x = 1 ..7)
Bit 6 - Channel x half transfer clear (x = 1 ..7)
Bit 5 - Channel x transfer complete clear (x = 1 ..7)
Bit 4 - Channel x global interrupt clear (x = 1 ..7)
Bit 3 - Channel x transfer error clear (x = 1 ..7)
Bit 2 - Channel x half transfer clear (x = 1 ..7)
Bit 1 - Channel x transfer complete clear (x = 1 ..7)
Bit 0 - Channel x global interrupt clear (x = 1 ..7)
impl W<u32, Reg<u32, _CCR1>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR1>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR1>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR1>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR2>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR2>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR2>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR2>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR3>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR3>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR3>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR3>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR4>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR4>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR4>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR4>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR5>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR5>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR5>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR5>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR6>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR6>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR6>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR6>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR7>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR7>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR7>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR7>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CSELR>>
Bits 24:27 - DMA channel 7 selection
Bits 20:23 - DMA channel 6 selection
Bits 16:19 - DMA channel 5 selection
Bits 12:15 - DMA channel 4 selection
Bits 8:11 - DMA channel 3 selection
Bits 4:7 - DMA channel 2 selection
Bits 0:3 - DMA channel 1 selection
impl W<u32, Reg<u32, _DR>>
pub fn dr(&mut self) -> DR_W<'_>
Bits 0:31 - Data register bits
impl W<u32, Reg<u32, _IDR>>
Bits 0:7 - General-purpose 8-bit data register bits
impl W<u32, Reg<u32, _CR>>
Bit 7 - Reverse output data
Bits 5:6 - Reverse input data
Bits 3:4 - Polynomial size
impl W<u32, Reg<u32, _INIT>>
Bits 0:31 - Programmable initial CRC value
impl W<u32, Reg<u32, _POL>>
Bits 0:31 - Programmable polynomial
impl W<u8, Reg<u8, _DR8>>
Bits 0:7 - Data register bits
impl W<u16, Reg<u16, _DR16>>
Bits 0:15 - Data register bits
impl W<u32, Reg<u32, _CR>>
Bits 2:4 - Duty selection
Bit 1 - Voltage source selection
Bit 0 - LCD controller enable
Bit 7 - Mux segment enable
Bit 8 - Voltage output buffer enable
impl W<u32, Reg<u32, _FCR>>
pub fn ps(&mut self) -> PS_W<'_>
Bits 22:25 - PS 16-bit prescaler
Bits 18:21 - DIV clock divider
Bits 16:17 - Blink mode selection
Bits 13:15 - Blink frequency selection
pub fn cc(&mut self) -> CC_W<'_>
Bits 10:12 - Contrast control
Bits 7:9 - Dead time duration
Bits 4:6 - Pulse ON duration
Bit 3 - Update display done interrupt enable
Bit 1 - Start of frame interrupt enable
pub fn hd(&mut self) -> HD_W<'_>
Bit 0 - High drive enable
impl W<u32, Reg<u32, _SR>>
Bit 2 - Update display request
impl W<u32, Reg<u32, _CLR>>
Bit 3 - Update display done clear
Bit 1 - Start of frame flag clear
impl W<u32, Reg<u32, _RAM_COM0>>
impl W<u32, Reg<u32, _RAM_COM1>>
impl W<u32, Reg<u32, _RAM_COM2>>
impl W<u32, Reg<u32, _RAM_COM3>>
impl W<u32, Reg<u32, _RAM_COM4>>
impl W<u32, Reg<u32, _RAM_COM5>>
impl W<u32, Reg<u32, _RAM_COM6>>
impl W<u32, Reg<u32, _RAM_COM7>>
impl W<u32, Reg<u32, _CR>>
Bits 28:31 - Charge transfer pulse high
Bits 24:27 - Charge transfer pulse low
Bits 17:23 - Spread spectrum deviation
Bit 16 - Spread spectrum enable
Bit 15 - Spread spectrum prescaler
Bits 12:14 - pulse generator prescaler
Bits 5:7 - Max count value
Bit 3 - Synchronization pin polarity
pub fn am(&mut self) -> AM_W<'_>
Bit 1 - Start a new acquisition
Bit 0 - Touch sensing controller enable
impl W<u32, Reg<u32, _IER>>
Bit 1 - Max count error interrupt enable
Bit 0 - End of acquisition interrupt enable
impl W<u32, Reg<u32, _ICR>>
Bit 1 - Max count error interrupt clear
Bit 0 - End of acquisition interrupt clear
impl W<u32, Reg<u32, _ISR>>
Bit 1 - Max count error flag
Bit 0 - End of acquisition flag
impl W<u32, Reg<u32, _IOHCR>>
impl W<u32, Reg<u32, _IOASCR>>
impl W<u32, Reg<u32, _IOSCR>>
impl W<u32, Reg<u32, _IOCCR>>
impl W<u32, Reg<u32, _IOGCSR>>
Bit 7 - Analog I/O group x enable
Bit 6 - Analog I/O group x enable
Bit 5 - Analog I/O group x enable
Bit 4 - Analog I/O group x enable
Bit 3 - Analog I/O group x enable
Bit 2 - Analog I/O group x enable
Bit 1 - Analog I/O group x enable
Bit 0 - Analog I/O group x enable
impl W<u32, Reg<u32, _KR>>
Bits 0:15 - Key value (write only, read 0x0000)
impl W<u32, Reg<u32, _PR>>
pub fn pr(&mut self) -> PR_W<'_>
Bits 0:2 - Prescaler divider
impl W<u32, Reg<u32, _RLR>>
pub fn rl(&mut self) -> RL_W<'_>
Bits 0:11 - Watchdog counter reload value
impl W<u32, Reg<u32, _WINR>>
Bits 0:11 - Watchdog counter window value
impl W<u32, Reg<u32, _CR>>
pub fn t(&mut self) -> T_W<'_>
Bits 0:6 - 7-bit counter (MSB to LSB)
impl W<u32, Reg<u32, _CFR>>
Bit 9 - Early wakeup interrupt
pub fn w(&mut self) -> W_W<'_>
Bits 0:6 - 7-bit window value
impl W<u32, Reg<u32, _SR>>
Bit 0 - Early wakeup interrupt flag
impl W<u32, Reg<u32, _COMP1_CSR>>
Bit 0 - Comparator 1 enable bit
Bits 2:3 - Power Mode of the comparator 1
Bits 4:6 - Comparator 1 Input Minus connection configuration bit
Bits 7:8 - Comparator1 input plus selection bit
Bit 15 - Comparator 1 polarity selection bit
Bits 16:17 - Comparator 1 hysteresis selection bits
Bits 18:20 - Comparator 1 blanking source selection bits
Bit 22 - Scaler bridge enable
Bit 23 - Voltage scaler enable bit
Bits 25:26 - comparator 1 input minus extended selection bits
Bit 31 - COMP1_CSR register lock bit
impl W<u32, Reg<u32, _COMP2_CSR>>
Bit 0 - Comparator 2 enable bit
Bits 2:3 - Power Mode of the comparator 2
Bits 4:6 - Comparator 2 Input Minus connection configuration bit
Bits 7:8 - Comparator 2 Input Plus connection configuration bit
Bit 9 - Windows mode selection bit
Bit 15 - Comparator 2 polarity selection bit
Bits 16:17 - Comparator 2 hysteresis selection bits
Bits 18:20 - Comparator 2 blanking source selection bits
Bit 22 - Scaler bridge enable
Bit 23 - Voltage scaler enable bit
Bits 25:26 - comparator 2 input minus extended selection bits
Bit 31 - COMP2_CSR register lock bit
impl W<u32, Reg<u32, _CSSA>>
Bits 8:23 - code segment start address
impl W<u32, Reg<u32, _CSL>>
Bits 8:21 - code segment length
impl W<u32, Reg<u32, _NVDSSA>>
Bits 8:23 - Non-volatile data segment start address
impl W<u32, Reg<u32, _NVDSL>>
Bits 8:21 - Non-volatile data segment length
impl W<u32, Reg<u32, _VDSSA>>
Bits 6:15 - Volatile data segment start address
impl W<u32, Reg<u32, _VDSL>>
Bits 6:15 - Non-volatile data segment length
impl W<u32, Reg<u32, _CR>>
Bit 2 - Volatile data execution
Bit 1 - Volatile data shared
Bit 0 - Firewall pre alarm
impl W<u32, Reg<u32, _CR1>>
pub fn pe(&mut self) -> PE_W<'_>
Bit 0 - Peripheral enable
Bit 1 - TX Interrupt enable
Bit 2 - RX Interrupt enable
Bit 3 - Address match interrupt enable (slave only)
Bit 4 - Not acknowledge received interrupt enable
Bit 5 - STOP detection Interrupt enable
Bit 6 - Transfer Complete interrupt enable
Bit 7 - Error interrupts enable
Bits 8:11 - Digital noise filter
Bit 12 - Analog noise filter OFF
Bit 14 - DMA transmission requests enable
Bit 15 - DMA reception requests enable
Bit 16 - Slave byte control
Bit 17 - Clock stretching disable
Bit 18 - Wakeup from STOP enable
Bit 19 - General call enable
Bit 20 - SMBus Host address enable
Bit 21 - SMBus Device Default address enable
Bit 22 - SMBUS alert enable
impl W<u32, Reg<u32, _CR2>>
Bit 26 - Packet error checking byte
Bit 25 - Automatic end mode (master mode)
Bit 24 - NBYTES reload mode
Bits 16:23 - Number of bytes
Bit 15 - NACK generation (slave mode)
Bit 14 - Stop generation (master mode)
Bit 13 - Start generation
Bit 12 - 10-bit address header only read direction (master receiver mode)
Bit 11 - 10-bit addressing mode (master mode)
Bit 10 - Transfer direction (master mode)
Bits 0:9 - Slave address bit (master mode)
impl W<u32, Reg<u32, _OAR1>>
Bits 0:9 - Interface address
Bit 10 - Own Address 1 10-bit mode
Bit 15 - Own Address 1 enable
impl W<u32, Reg<u32, _OAR2>>
Bits 1:7 - Interface address
Bits 8:10 - Own Address 2 masks
Bit 15 - Own Address 2 enable
impl W<u32, Reg<u32, _TIMINGR>>
Bits 0:7 - SCL low period (master mode)
Bits 8:15 - SCL high period (master mode)
Bits 16:19 - Data hold time
Bits 20:23 - Data setup time
Bits 28:31 - Timing prescaler
impl W<u32, Reg<u32, _TIMEOUTR>>
Bits 0:11 - Bus timeout A
Bit 12 - Idle clock timeout detection
Bit 15 - Clock timeout enable
Bits 16:27 - Bus timeout B
pub fn texten(&mut self) -> TEXTEN_W<'_>
Bit 31 - Extended clock timeout enable
impl W<u32, Reg<u32, _ISR>>
Bit 1 - Transmit interrupt status (transmitters)
Bit 0 - Transmit data register empty (transmitters)
impl W<u32, Reg<u32, _ICR>>
Bit 13 - Alert flag clear
Bit 12 - Timeout detection flag clear
Bit 11 - PEC Error flag clear
Bit 10 - Overrun/Underrun flag clear
Bit 9 - Arbitration lost flag clear
Bit 8 - Bus error flag clear
Bit 5 - Stop detection flag clear
Bit 4 - Not Acknowledge flag clear
Bit 3 - Address Matched flag clear
impl W<u32, Reg<u32, _TXDR>>
Bits 0:7 - 8-bit transmit data
impl W<u32, Reg<u32, _ACR>>
Bit 9 - Instruction cache enable
Bit 10 - Data cache enable
Bit 11 - Instruction cache reset
Bit 12 - Data cache reset
Bit 13 - Flash Power-down mode during Low-power run mode
Bit 14 - Flash Power-down mode during Low-power sleep mode
impl W<u32, Reg<u32, _PDKEYR>>
Bits 0:31 - RUN_PD in FLASH_ACR key
impl W<u32, Reg<u32, _KEYR>>
impl W<u32, Reg<u32, _OPTKEYR>>
Bits 0:31 - Option byte key
impl W<u32, Reg<u32, _SR>>
Bit 3 - Programming error
Bit 4 - Write protected error
Bit 5 - Programming alignment error
Bit 7 - Programming sequence error
Bit 8 - Fast programming data miss error
Bit 9 - Fast programming error
Bit 14 - PCROP read error
Bit 15 - Option validity error
impl W<u32, Reg<u32, _CR>>
pub fn pg(&mut self) -> PG_W<'_>
Bit 2 - Bank 1 Mass erase
Bit 15 - Bank 2 Mass erase
Bit 17 - Options modification start
Bit 18 - Fast programming
Bit 24 - End of operation interrupt enable
Bit 25 - Error interrupt enable
Bit 26 - PCROP read error interrupt enable
Bit 27 - Force the option byte loading
impl W<u32, Reg<u32, _ECCR>>
Bit 24 - ECC correction interrupt enable
impl W<u32, Reg<u32, _OPTR>>
Bits 0:7 - Read protection level
Bits 8:10 - BOR reset Level
Bit 16 - Independent watchdog selection
Bit 17 - Independent watchdog counter freeze in Stop mode
Bit 18 - Independent watchdog counter freeze in Standby mode
Bit 19 - Window watchdog selection
Bit 21 - Dual-Bank on 512 KB or 256 KB Flash memory devices
Bit 23 - Boot configuration
Bit 24 - SRAM2 parity check enable
Bit 25 - SRAM2 Erase when system reset
Bit 27 - nBOOT0 option bit
impl W<u32, Reg<u32, _PCROP1SR>>
Bits 0:15 - Bank 1 PCROP area start offset
impl W<u32, Reg<u32, _PCROP1ER>>
Bits 0:15 - Bank 1 PCROP area end offset
Bit 31 - PCROP area preserved when RDP level decreased
impl W<u32, Reg<u32, _WRP1AR>>
Bits 0:7 - Bank 1 WRP first area tart offset
Bits 16:23 - Bank 1 WRP first area A end offset
impl W<u32, Reg<u32, _WRP1BR>>
Bits 16:23 - Bank 1 WRP second area B end offset
Bits 0:7 - Bank 1 WRP second area B start offset
impl W<u32, Reg<u32, _PCROP2SR>>
Bits 0:15 - Bank 2 PCROP area start offset
impl W<u32, Reg<u32, _PCROP2ER>>
Bits 0:15 - Bank 2 PCROP area end offset
impl W<u32, Reg<u32, _WRP2AR>>
Bits 0:7 - Bank 2 WRP first area A start offset
Bits 16:23 - Bank 2 WRP first area A end offset
impl W<u32, Reg<u32, _WRP2BR>>
Bits 0:7 - Bank 2 WRP second area B start offset
Bits 16:23 - Bank 2 WRP second area B end offset
impl W<u32, Reg<u32, _CR>>
Bit 19 - Clock security system enable
Bit 18 - HSE crystal oscillator bypass
Bit 16 - HSE clock enable
Bit 11 - HSI automatic start from Stop
Bit 9 - HSI always enable for peripheral kernels
Bits 4:7 - MSI clock ranges
Bit 3 - MSI clock range selection
Bit 2 - MSI clock PLL enable
impl W<u32, Reg<u32, _ICSCR>>
Bits 24:28 - HSI clock trimming
Bits 8:15 - MSI clock trimming
impl W<u32, Reg<u32, _CFGR>>
Bits 24:26 - Microcontroller clock output
Bit 15 - Wakeup from Stop and CSS backup clock selection
Bits 11:13 - APB high-speed prescaler (APB2)
Bits 8:10 - PB low-speed prescaler (APB1)
pub fn sw(&mut self) -> SW_W<'_>
Bits 0:1 - System clock switch
impl W<u32, Reg<u32, _PLLCFGR>>
Bits 25:26 - Main PLL division factor for PLLCLK (system clock)
Bit 24 - Main PLL PLLCLK output enable
Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)
Bit 20 - Main PLL PLLUSB1CLK output enable
Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
Bit 16 - Main PLL PLLSAI3CLK output enable
Bits 8:14 - Main PLL multiplication factor for VCO
Bits 4:6 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source
Bits 27:31 - Main PLL division factor for PLLSAI2CLK
impl W<u32, Reg<u32, _PLLSAI1CFGR>>
Bits 25:26 - PLLSAI1 division factor for PLLADC1CLK (ADC clock)
Bit 24 - PLLSAI1 PLLADC1CLK output enable
Bits 21:22 - SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)
Bit 20 - SAI1PLL PLLUSB2CLK output enable
Bit 17 - SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)
Bit 16 - SAI1PLL PLLSAI1CLK output enable
Bits 8:14 - SAI1PLL multiplication factor for VCO
Bits 27:31 - PLLSAI1 division factor for PLLSAI1CLK
impl W<u32, Reg<u32, _CIER>>
Bit 9 - LSE clock security system interrupt enable
Bit 6 - PLLSAI1 ready interrupt enable
Bit 5 - PLL ready interrupt enable
Bit 4 - HSE ready interrupt enable
Bit 3 - HSI ready interrupt enable
Bit 2 - MSI ready interrupt enable
Bit 1 - LSE ready interrupt enable
Bit 0 - LSI ready interrupt enable
Bit 10 - HSI48 ready interrupt enable
impl W<u32, Reg<u32, _CICR>>
Bit 9 - LSE Clock security system interrupt clear
Bit 8 - Clock security system interrupt clear
Bit 6 - PLLSAI1 ready interrupt clear
Bit 5 - PLL ready interrupt clear
Bit 4 - HSE ready interrupt clear
Bit 3 - HSI ready interrupt clear
Bit 2 - MSI ready interrupt clear
Bit 1 - LSE ready interrupt clear
Bit 0 - LSI ready interrupt clear
Bit 10 - HSI48 oscillator ready interrupt clear
impl W<u32, Reg<u32, _AHB1RSTR>>
Bit 16 - Touch Sensing Controller reset
Bit 8 - Flash memory interface reset
impl W<u32, Reg<u32, _AHB2RSTR>>
Bit 18 - Random number generator reset
Bit 16 - AES hardware accelerator reset
impl W<u32, Reg<u32, _AHB3RSTR>>
Bit 8 - Quad SPI memory interface reset
impl W<u32, Reg<u32, _APB1RSTR1>>
Bit 31 - Low Power Timer 1 reset
Bit 30 - OPAMP interface reset
Bit 29 - DAC1 interface reset
Bit 28 - Power interface reset
Bit 9 - LCD interface reset
impl W<u32, Reg<u32, _APB1RSTR2>>
Bit 5 - Low-power timer 2 reset
Bit 2 - Single wire protocol reset
Bit 0 - Low-power UART 1 reset
impl W<u32, Reg<u32, _APB2RSTR>>
Bit 21 - Serial audio interface 1 (SAI1) reset
Bit 17 - TIM16 timer reset
Bit 16 - TIM15 timer reset
Bit 11 - TIM1 timer reset
Bit 0 - System configuration (SYSCFG) reset
Bit 24 - DFSDM filter reset
impl W<u32, Reg<u32, _AHB1ENR>>
Bit 16 - Touch Sensing Controller clock enable
Bit 12 - CRC clock enable
Bit 8 - Flash memory interface clock enable
Bit 1 - DMA2 clock enable
Bit 0 - DMA1 clock enable
impl W<u32, Reg<u32, _AHB2ENR>>
Bit 18 - Random Number Generator clock enable
Bit 16 - AES accelerator clock enable
Bit 13 - ADC clock enable
Bit 7 - IO port H clock enable
Bit 4 - IO port E clock enable
Bit 3 - IO port D clock enable
Bit 2 - IO port C clock enable
Bit 1 - IO port B clock enable
Bit 0 - IO port A clock enable
impl W<u32, Reg<u32, _AHB3ENR>>
impl W<u32, Reg<u32, _APB1ENR1>>
Bit 31 - Low power timer 1 clock enable
Bit 30 - OPAMP interface clock enable
Bit 29 - DAC1 interface clock enable
Bit 28 - Power interface clock enable
Bit 25 - CAN1 clock enable
Bit 23 - I2C3 clock enable
Bit 21 - I2C1 clock enable
Bit 18 - USART1 clock enable
Bit 17 - USART2 clock enable
Bit 15 - SPI3 clock enable
Bit 14 - SPI peripheral 2 clock enable
Bit 11 - Window watchdog clock enable
Bit 5 - TIM7 timer clock enable
Bit 4 - TIM6 timer clock enable
Bit 0 - TIM2 timer clock enable
Bit 10 - RTC APB clock enable
Bit 24 - CRS clock enable
Bit 26 - USB FS clock enable
Bit 1 - TIM3 timer clock enable
Bit 19 - UART4 clock enable
Bit 22 - I2C2 clock enable
impl W<u32, Reg<u32, _APB1ENR2>>
Bit 2 - Single wire protocol clock enable
Bit 0 - Low power UART 1 clock enable
Bit 1 - I2C4 clock enable
impl W<u32, Reg<u32, _APB2ENR>>
Bit 21 - SAI1 clock enable
Bit 17 - TIM16 timer clock enable
Bit 16 - TIM15 timer clock enable
Bit 14 - USART1clock enable
Bit 12 - SPI1 clock enable
Bit 11 - TIM1 timer clock enable
Bit 10 - SDMMC clock enable
Bit 7 - Firewall clock enable
Bit 0 - SYSCFG clock enable
impl W<u32, Reg<u32, _AHB1SMENR>>
Bit 16 - Touch Sensing Controller clocks enable during Sleep and Stop modes
Bit 9 - SRAM1 interface clocks enable during Sleep and Stop modes
Bit 8 - Flash memory interface clocks enable during Sleep and Stop modes
Bit 1 - DMA2 clocks enable during Sleep and Stop modes
Bit 0 - DMA1 clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _AHB2SMENR>>
Bit 18 - Random Number Generator clocks enable during Sleep and Stop modes
Bit 16 - AES accelerator clocks enable during Sleep and Stop modes
Bit 13 - ADC clocks enable during Sleep and Stop modes
Bit 9 - SRAM2 interface clocks enable during Sleep and Stop modes
Bit 7 - IO port H clocks enable during Sleep and Stop modes
Bit 4 - IO port E clocks enable during Sleep and Stop modes
Bit 3 - IO port D clocks enable during Sleep and Stop modes
Bit 2 - IO port C clocks enable during Sleep and Stop modes
Bit 1 - IO port B clocks enable during Sleep and Stop modes
Bit 0 - IO port A clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _AHB3SMENR>>
impl W<u32, Reg<u32, _APB1SMENR1>>
Bit 31 - Low power timer 1 clocks enable during Sleep and Stop modes
Bit 30 - OPAMP interface clocks enable during Sleep and Stop modes
Bit 29 - DAC1 interface clocks enable during Sleep and Stop modes
Bit 28 - Power interface clocks enable during Sleep and Stop modes
Bit 25 - CAN1 clocks enable during Sleep and Stop modes
Bit 23 - I2C3 clocks enable during Sleep and Stop modes
Bit 21 - I2C1 clocks enable during Sleep and Stop modes
Bit 18 - USART2 clocks enable during Sleep and Stop modes
Bit 17 - USART1 clocks enable during Sleep and Stop modes
Bit 15 - SPI3 clocks enable during Sleep and Stop modes
Bit 14 - SPI2 clocks enable during Sleep and Stop modes
Bit 11 - Window watchdog clocks enable during Sleep and Stop modes
Bit 9 - LCD clocks enable during Sleep and Stop modes
Bit 5 - TIM7 timer clocks enable during Sleep and Stop modes
Bit 4 - TIM6 timer clocks enable during Sleep and Stop modes
Bit 0 - TIM2 timer clocks enable during Sleep and Stop modes
Bit 10 - RTC APB clock enable during Sleep and Stop modes
Bit 26 - USB FS clock enable during Sleep and Stop modes
Bit 22 - I2C2 clocks enable during Sleep and Stop modes
Bit 24 - CRS clock enable during Sleep and Stop modes
impl W<u32, Reg<u32, _APB1SMENR2>>
Bit 2 - Single wire protocol clocks enable during Sleep and Stop modes
Bit 0 - Low power UART 1 clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _APB2SMENR>>
Bit 21 - SAI1 clocks enable during Sleep and Stop modes
Bit 17 - TIM16 timer clocks enable during Sleep and Stop modes
Bit 16 - TIM15 timer clocks enable during Sleep and Stop modes
Bit 14 - USART1clocks enable during Sleep and Stop modes
Bit 12 - SPI1 clocks enable during Sleep and Stop modes
Bit 11 - TIM1 timer clocks enable during Sleep and Stop modes
Bit 10 - SDMMC clocks enable during Sleep and Stop modes
Bit 0 - SYSCFG clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _CCIPR>>
Bit 30 - SWPMI1 clock source selection
Bits 28:29 - ADCs clock source selection
Bits 26:27 - 48 MHz clock source selection
Bits 22:23 - SAI1 clock source selection
Bits 20:21 - Low power timer 2 clock source selection
Bits 18:19 - Low power timer 1 clock source selection
Bits 16:17 - I2C3 clock source selection
Bits 12:13 - I2C1 clock source selection
Bits 10:11 - LPUART1 clock source selection
Bits 2:3 - USART2 clock source selection
Bits 0:1 - USART1 clock source selection
Bits 6:7 - USART4 clock source selection
Bits 4:5 - USART3 clock source selection
Bits 14:15 - I2C2 clock source selection
impl W<u32, Reg<u32, _BDCR>>
Bit 25 - Low speed clock output selection
Bit 24 - Low speed clock output enable
Bit 16 - Backup domain software reset
Bit 15 - RTC clock enable
Bits 8:9 - RTC clock source selection
Bits 3:4 - SE oscillator drive capability
Bit 2 - LSE oscillator bypass
Bit 0 - LSE oscillator enable
impl W<u32, Reg<u32, _CSR>>
Bit 23 - Remove reset flag
Bits 8:11 - SI range after Standby mode
Bit 0 - LSI oscillator enable
impl W<u32, Reg<u32, _CRRCR>>
Bit 0 - HSI48 clock enable
impl W<u32, Reg<u32, _CR1>>
Bits 9:10 - Voltage scaling range selection
Bit 8 - Disable backup domain write protection
Bits 0:2 - Low-power mode selection
impl W<u32, Reg<u32, _CR2>>
Bit 10 - VDDUSB USB supply valid
Bit 9 - VDDIO2 Independent I/Os supply valid
Bit 7 - Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V
Bit 6 - Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V
Bit 5 - Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V
Bit 4 - Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V
Bits 1:3 - Power voltage detector level selection
Bit 0 - Power voltage detector enable
impl W<u32, Reg<u32, _CR3>>
Bit 15 - Enable internal wakeup line
Bit 10 - Apply pull-up and pull-down configuration
Bit 8 - SRAM2 retention in Standby mode
Bit 4 - Enable Wakeup pin WKUP5
Bit 3 - Enable Wakeup pin WKUP4
Bit 2 - Enable Wakeup pin WKUP3
Bit 1 - Enable Wakeup pin WKUP2
Bit 0 - Enable Wakeup pin WKUP1
impl W<u32, Reg<u32, _CR4>>
Bit 9 - VBAT battery charging resistor selection
Bit 8 - VBAT battery charging enable
Bit 4 - Wakeup pin WKUP5 polarity
Bit 3 - Wakeup pin WKUP4 polarity
Bit 2 - Wakeup pin WKUP3 polarity
Bit 1 - Wakeup pin WKUP2 polarity
Bit 0 - Wakeup pin WKUP1 polarity
impl W<u32, Reg<u32, _SCR>>
Bit 8 - Clear standby flag
Bit 4 - Clear wakeup flag 5
Bit 3 - Clear wakeup flag 4
Bit 2 - Clear wakeup flag 3
Bit 1 - Clear wakeup flag 2
Bit 0 - Clear wakeup flag 1
impl W<u32, Reg<u32, _PUCRA>>
Bit 15 - Port A pull-up bit y (y=0..15)
Bit 14 - Port A pull-up bit y (y=0..15)
Bit 13 - Port A pull-up bit y (y=0..15)
Bit 12 - Port A pull-up bit y (y=0..15)
Bit 11 - Port A pull-up bit y (y=0..15)
Bit 10 - Port A pull-up bit y (y=0..15)
Bit 9 - Port A pull-up bit y (y=0..15)
Bit 8 - Port A pull-up bit y (y=0..15)
Bit 7 - Port A pull-up bit y (y=0..15)
Bit 6 - Port A pull-up bit y (y=0..15)
Bit 5 - Port A pull-up bit y (y=0..15)
Bit 4 - Port A pull-up bit y (y=0..15)
Bit 3 - Port A pull-up bit y (y=0..15)
Bit 2 - Port A pull-up bit y (y=0..15)
Bit 1 - Port A pull-up bit y (y=0..15)
Bit 0 - Port A pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRA>>
Bit 15 - Port A pull-down bit y (y=0..15)
Bit 14 - Port A pull-down bit y (y=0..15)
Bit 13 - Port A pull-down bit y (y=0..15)
Bit 12 - Port A pull-down bit y (y=0..15)
Bit 11 - Port A pull-down bit y (y=0..15)
Bit 10 - Port A pull-down bit y (y=0..15)
Bit 9 - Port A pull-down bit y (y=0..15)
Bit 8 - Port A pull-down bit y (y=0..15)
Bit 7 - Port A pull-down bit y (y=0..15)
Bit 6 - Port A pull-down bit y (y=0..15)
Bit 5 - Port A pull-down bit y (y=0..15)
Bit 4 - Port A pull-down bit y (y=0..15)
Bit 3 - Port A pull-down bit y (y=0..15)
Bit 2 - Port A pull-down bit y (y=0..15)
Bit 1 - Port A pull-down bit y (y=0..15)
Bit 0 - Port A pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRB>>
Bit 15 - Port B pull-up bit y (y=0..15)
Bit 14 - Port B pull-up bit y (y=0..15)
Bit 13 - Port B pull-up bit y (y=0..15)
Bit 12 - Port B pull-up bit y (y=0..15)
Bit 11 - Port B pull-up bit y (y=0..15)
Bit 10 - Port B pull-up bit y (y=0..15)
Bit 9 - Port B pull-up bit y (y=0..15)
Bit 8 - Port B pull-up bit y (y=0..15)
Bit 7 - Port B pull-up bit y (y=0..15)
Bit 6 - Port B pull-up bit y (y=0..15)
Bit 5 - Port B pull-up bit y (y=0..15)
Bit 4 - Port B pull-up bit y (y=0..15)
Bit 3 - Port B pull-up bit y (y=0..15)
Bit 2 - Port B pull-up bit y (y=0..15)
Bit 1 - Port B pull-up bit y (y=0..15)
Bit 0 - Port B pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRB>>
Bit 15 - Port B pull-down bit y (y=0..15)
Bit 14 - Port B pull-down bit y (y=0..15)
Bit 13 - Port B pull-down bit y (y=0..15)
Bit 12 - Port B pull-down bit y (y=0..15)
Bit 11 - Port B pull-down bit y (y=0..15)
Bit 10 - Port B pull-down bit y (y=0..15)
Bit 9 - Port B pull-down bit y (y=0..15)
Bit 8 - Port B pull-down bit y (y=0..15)
Bit 7 - Port B pull-down bit y (y=0..15)
Bit 6 - Port B pull-down bit y (y=0..15)
Bit 5 - Port B pull-down bit y (y=0..15)
Bit 4 - Port B pull-down bit y (y=0..15)
Bit 3 - Port B pull-down bit y (y=0..15)
Bit 2 - Port B pull-down bit y (y=0..15)
Bit 1 - Port B pull-down bit y (y=0..15)
Bit 0 - Port B pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRC>>
Bit 15 - Port C pull-up bit y (y=0..15)
Bit 14 - Port C pull-up bit y (y=0..15)
Bit 13 - Port C pull-up bit y (y=0..15)
Bit 12 - Port C pull-up bit y (y=0..15)
Bit 11 - Port C pull-up bit y (y=0..15)
Bit 10 - Port C pull-up bit y (y=0..15)
Bit 9 - Port C pull-up bit y (y=0..15)
Bit 8 - Port C pull-up bit y (y=0..15)
Bit 7 - Port C pull-up bit y (y=0..15)
Bit 6 - Port C pull-up bit y (y=0..15)
Bit 5 - Port C pull-up bit y (y=0..15)
Bit 4 - Port C pull-up bit y (y=0..15)
Bit 3 - Port C pull-up bit y (y=0..15)
Bit 2 - Port C pull-up bit y (y=0..15)
Bit 1 - Port C pull-up bit y (y=0..15)
Bit 0 - Port C pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRC>>
Bit 15 - Port C pull-down bit y (y=0..15)
Bit 14 - Port C pull-down bit y (y=0..15)
Bit 13 - Port C pull-down bit y (y=0..15)
Bit 12 - Port C pull-down bit y (y=0..15)
Bit 11 - Port C pull-down bit y (y=0..15)
Bit 10 - Port C pull-down bit y (y=0..15)
Bit 9 - Port C pull-down bit y (y=0..15)
Bit 8 - Port C pull-down bit y (y=0..15)
Bit 7 - Port C pull-down bit y (y=0..15)
Bit 6 - Port C pull-down bit y (y=0..15)
Bit 5 - Port C pull-down bit y (y=0..15)
Bit 4 - Port C pull-down bit y (y=0..15)
Bit 3 - Port C pull-down bit y (y=0..15)
Bit 2 - Port C pull-down bit y (y=0..15)
Bit 1 - Port C pull-down bit y (y=0..15)
Bit 0 - Port C pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRD>>
Bit 15 - Port D pull-up bit y (y=0..15)
Bit 14 - Port D pull-up bit y (y=0..15)
Bit 13 - Port D pull-up bit y (y=0..15)
Bit 12 - Port D pull-up bit y (y=0..15)
Bit 11 - Port D pull-up bit y (y=0..15)
Bit 10 - Port D pull-up bit y (y=0..15)
Bit 9 - Port D pull-up bit y (y=0..15)
Bit 8 - Port D pull-up bit y (y=0..15)
Bit 7 - Port D pull-up bit y (y=0..15)
Bit 6 - Port D pull-up bit y (y=0..15)
Bit 5 - Port D pull-up bit y (y=0..15)
Bit 4 - Port D pull-up bit y (y=0..15)
Bit 3 - Port D pull-up bit y (y=0..15)
Bit 2 - Port D pull-up bit y (y=0..15)
Bit 1 - Port D pull-up bit y (y=0..15)
Bit 0 - Port D pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRD>>
Bit 15 - Port D pull-down bit y (y=0..15)
Bit 14 - Port D pull-down bit y (y=0..15)
Bit 13 - Port D pull-down bit y (y=0..15)
Bit 12 - Port D pull-down bit y (y=0..15)
Bit 11 - Port D pull-down bit y (y=0..15)
Bit 10 - Port D pull-down bit y (y=0..15)
Bit 9 - Port D pull-down bit y (y=0..15)
Bit 8 - Port D pull-down bit y (y=0..15)
Bit 7 - Port D pull-down bit y (y=0..15)
Bit 6 - Port D pull-down bit y (y=0..15)
Bit 5 - Port D pull-down bit y (y=0..15)
Bit 4 - Port D pull-down bit y (y=0..15)
Bit 3 - Port D pull-down bit y (y=0..15)
Bit 2 - Port D pull-down bit y (y=0..15)
Bit 1 - Port D pull-down bit y (y=0..15)
Bit 0 - Port D pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRE>>
Bit 15 - Port E pull-up bit y (y=0..15)
Bit 14 - Port E pull-up bit y (y=0..15)
Bit 13 - Port E pull-up bit y (y=0..15)
Bit 12 - Port E pull-up bit y (y=0..15)
Bit 11 - Port E pull-up bit y (y=0..15)
Bit 10 - Port E pull-up bit y (y=0..15)
Bit 9 - Port E pull-up bit y (y=0..15)
Bit 8 - Port E pull-up bit y (y=0..15)
Bit 7 - Port E pull-up bit y (y=0..15)
Bit 6 - Port E pull-up bit y (y=0..15)
Bit 5 - Port E pull-up bit y (y=0..15)
Bit 4 - Port E pull-up bit y (y=0..15)
Bit 3 - Port E pull-up bit y (y=0..15)
Bit 2 - Port E pull-up bit y (y=0..15)
Bit 1 - Port E pull-up bit y (y=0..15)
Bit 0 - Port E pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRE>>
Bit 15 - Port E pull-down bit y (y=0..15)
Bit 14 - Port E pull-down bit y (y=0..15)
Bit 13 - Port E pull-down bit y (y=0..15)
Bit 12 - Port E pull-down bit y (y=0..15)
Bit 11 - Port E pull-down bit y (y=0..15)
Bit 10 - Port E pull-down bit y (y=0..15)
Bit 9 - Port E pull-down bit y (y=0..15)
Bit 8 - Port E pull-down bit y (y=0..15)
Bit 7 - Port E pull-down bit y (y=0..15)
Bit 6 - Port E pull-down bit y (y=0..15)
Bit 5 - Port E pull-down bit y (y=0..15)
Bit 4 - Port E pull-down bit y (y=0..15)
Bit 3 - Port E pull-down bit y (y=0..15)
Bit 2 - Port E pull-down bit y (y=0..15)
Bit 1 - Port E pull-down bit y (y=0..15)
Bit 0 - Port E pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRF>>
Bit 15 - Port F pull-up bit y (y=0..15)
Bit 14 - Port F pull-up bit y (y=0..15)
Bit 13 - Port F pull-up bit y (y=0..15)
Bit 12 - Port F pull-up bit y (y=0..15)
Bit 11 - Port F pull-up bit y (y=0..15)
Bit 10 - Port F pull-up bit y (y=0..15)
Bit 9 - Port F pull-up bit y (y=0..15)
Bit 8 - Port F pull-up bit y (y=0..15)
Bit 7 - Port F pull-up bit y (y=0..15)
Bit 6 - Port F pull-up bit y (y=0..15)
Bit 5 - Port F pull-up bit y (y=0..15)
Bit 4 - Port F pull-up bit y (y=0..15)
Bit 3 - Port F pull-up bit y (y=0..15)
Bit 2 - Port F pull-up bit y (y=0..15)
Bit 1 - Port F pull-up bit y (y=0..15)
Bit 0 - Port F pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRF>>
Bit 15 - Port F pull-down bit y (y=0..15)
Bit 14 - Port F pull-down bit y (y=0..15)
Bit 13 - Port F pull-down bit y (y=0..15)
Bit 12 - Port F pull-down bit y (y=0..15)
Bit 11 - Port F pull-down bit y (y=0..15)
Bit 10 - Port F pull-down bit y (y=0..15)
Bit 9 - Port F pull-down bit y (y=0..15)
Bit 8 - Port F pull-down bit y (y=0..15)
Bit 7 - Port F pull-down bit y (y=0..15)
Bit 6 - Port F pull-down bit y (y=0..15)
Bit 5 - Port F pull-down bit y (y=0..15)
Bit 4 - Port F pull-down bit y (y=0..15)
Bit 3 - Port F pull-down bit y (y=0..15)
Bit 2 - Port F pull-down bit y (y=0..15)
Bit 1 - Port F pull-down bit y (y=0..15)
Bit 0 - Port F pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRG>>
Bit 15 - Port G pull-up bit y (y=0..15)
Bit 14 - Port G pull-up bit y (y=0..15)
Bit 13 - Port G pull-up bit y (y=0..15)
Bit 12 - Port G pull-up bit y (y=0..15)
Bit 11 - Port G pull-up bit y (y=0..15)
Bit 10 - Port G pull-up bit y (y=0..15)
Bit 9 - Port G pull-up bit y (y=0..15)
Bit 8 - Port G pull-up bit y (y=0..15)
Bit 7 - Port G pull-up bit y (y=0..15)
Bit 6 - Port G pull-up bit y (y=0..15)
Bit 5 - Port G pull-up bit y (y=0..15)
Bit 4 - Port G pull-up bit y (y=0..15)
Bit 3 - Port G pull-up bit y (y=0..15)
Bit 2 - Port G pull-up bit y (y=0..15)
Bit 1 - Port G pull-up bit y (y=0..15)
Bit 0 - Port G pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRG>>
Bit 15 - Port G pull-down bit y (y=0..15)
Bit 14 - Port G pull-down bit y (y=0..15)
Bit 13 - Port G pull-down bit y (y=0..15)
Bit 12 - Port G pull-down bit y (y=0..15)
Bit 11 - Port G pull-down bit y (y=0..15)
Bit 10 - Port G pull-down bit y (y=0..15)
Bit 9 - Port G pull-down bit y (y=0..15)
Bit 8 - Port G pull-down bit y (y=0..15)
Bit 7 - Port G pull-down bit y (y=0..15)
Bit 6 - Port G pull-down bit y (y=0..15)
Bit 5 - Port G pull-down bit y (y=0..15)
Bit 4 - Port G pull-down bit y (y=0..15)
Bit 3 - Port G pull-down bit y (y=0..15)
Bit 2 - Port G pull-down bit y (y=0..15)
Bit 1 - Port G pull-down bit y (y=0..15)
Bit 0 - Port G pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRH>>
Bit 1 - Port H pull-up bit y (y=0..1)
Bit 0 - Port H pull-up bit y (y=0..1)
impl W<u32, Reg<u32, _PDCRH>>
Bit 1 - Port H pull-down bit y (y=0..1)
Bit 0 - Port H pull-down bit y (y=0..1)
impl W<u32, Reg<u32, _MEMRMP>>
Bit 8 - Flash Bank mode selection
Bit 3 - QUADSPI memory mapping swap
Bits 0:2 - Memory mapping selection
impl W<u32, Reg<u32, _CFGR1>>
Bits 26:31 - Floating Point Unit interrupts enable bits
Bit 22 - I2C3 Fast-mode Plus driving capability activation
Bit 21 - I2C2 Fast-mode Plus driving capability activation
Bit 20 - I2C1 Fast-mode Plus driving capability activation
Bit 19 - Fast-mode Plus (Fm+) driving capability activation on PB9
Bit 18 - Fast-mode Plus (Fm+) driving capability activation on PB8
Bit 17 - Fast-mode Plus (Fm+) driving capability activation on PB7
Bit 16 - Fast-mode Plus (Fm+) driving capability activation on PB6
Bit 8 - I/O analog switch voltage booster enable
impl W<u32, Reg<u32, _EXTICR1>>
Bits 12:14 - EXTI 3 configuration bits
Bits 8:10 - EXTI 2 configuration bits
Bits 4:6 - EXTI 1 configuration bits
Bits 0:2 - EXTI 0 configuration bits
impl W<u32, Reg<u32, _EXTICR2>>
Bits 12:14 - EXTI 7 configuration bits
Bits 8:10 - EXTI 6 configuration bits
Bits 4:6 - EXTI 5 configuration bits
Bits 0:2 - EXTI 4 configuration bits
impl W<u32, Reg<u32, _EXTICR3>>
Bits 12:14 - EXTI 11 configuration bits
Bits 8:10 - EXTI 10 configuration bits
Bits 4:6 - EXTI 9 configuration bits
Bits 0:2 - EXTI 8 configuration bits
impl W<u32, Reg<u32, _EXTICR4>>
Bits 12:14 - EXTI15 configuration bits
Bits 8:10 - EXTI14 configuration bits
Bits 4:6 - EXTI13 configuration bits
Bits 0:2 - EXTI12 configuration bits
impl W<u32, Reg<u32, _SCSR>>
impl W<u32, Reg<u32, _CFGR2>>
Bit 8 - SRAM2 parity error flag
Bit 2 - PVD lock enable bit
Bit 1 - SRAM2 parity lock bit
Bit 0 - OCKUP (Hardfault) output enable bit
impl W<u32, Reg<u32, _SWPR>>
Bit 31 - SRAM2 page 31 write protection
impl W<u32, Reg<u32, _SKR>>
Bits 0:7 - SRAM2 write protection key for software erase
impl W<u32, Reg<u32, _CR>>
pub fn ie(&mut self) -> IE_W<'_>
Bit 2 - Random number generator enable
impl W<u32, Reg<u32, _SR>>
Bit 6 - Seed error interrupt status
Bit 5 - Clock error interrupt status
impl W<u32, Reg<u32, _CR>>
Bit 12 - Enable DMA management of data output phase
pub fn dmainen(&mut self) -> DMAINEN_W<'_>
Bit 11 - Enable DMA management of data input phase
Bit 10 - Error interrupt enable
Bit 9 - CCF flag interrupt enable
Bit 7 - Computation Complete Flag Clear
Bits 5:6 - AES chaining mode
Bits 3:4 - AES operating mode
Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _DINR>>
Bits 0:31 - Data Input Register
impl W<u32, Reg<u32, _KEYR0>>
Bits 0:31 - Data Output Register (LSB key [31:0])
impl W<u32, Reg<u32, _KEYR1>>
Bits 0:31 - AES key register (key [63:32])
impl W<u32, Reg<u32, _KEYR2>>
Bits 0:31 - AES key register (key [95:64])
impl W<u32, Reg<u32, _KEYR3>>
Bits 0:31 - AES key register (MSB key [127:96])
impl W<u32, Reg<u32, _IVR0>>
Bits 0:31 - initialization vector register (LSB IVR [31:0])
impl W<u32, Reg<u32, _IVR1>>
Bits 0:31 - Initialization Vector Register (IVR [63:32])
impl W<u32, Reg<u32, _IVR2>>
Bits 0:31 - Initialization Vector Register (IVR [95:64])
impl W<u32, Reg<u32, _IVR3>>
Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])
impl W<u32, Reg<u32, _ISR>>
impl W<u32, Reg<u32, _IER>>
impl W<u32, Reg<u32, _CR>>
impl W<u32, Reg<u32, _CFGR>>
impl W<u32, Reg<u32, _CFGR2>>
impl W<u32, Reg<u32, _SMPR1>>
Bits 27:29 - Channel 9 sampling time selection
Bits 24:26 - Channel 8 sampling time selection
Bits 21:23 - Channel 7 sampling time selection
Bits 18:20 - Channel 6 sampling time selection
Bits 15:17 - Channel 5 sampling time selection
Bits 12:14 - Channel 4 sampling time selection
Bits 9:11 - Channel 3 sampling time selection
Bits 6:8 - Channel 2 sampling time selection
Bits 3:5 - Channel 1 sampling time selection
Bits 0:2 - Channel 0 sampling time selection
impl W<u32, Reg<u32, _SMPR2>>
Bits 24:26 - Channel 18 sampling time selection
Bits 21:23 - Channel 17 sampling time selection
Bits 18:20 - Channel 16 sampling time selection
Bits 15:17 - Channel 15 sampling time selection
Bits 12:14 - Channel 14 sampling time selection
Bits 9:11 - Channel 13 sampling time selection
Bits 6:8 - Channel 12 sampling time selection
Bits 3:5 - Channel 11 sampling time selection
Bits 0:2 - Channel 10 sampling time selection
impl W<u32, Reg<u32, _TR1>>
impl W<u32, Reg<u32, _TR2>>
impl W<u32, Reg<u32, _TR3>>
impl W<u32, Reg<u32, _SQR1>>
pub fn l(&mut self) -> L_W<'_>
Bits 0:3 - Regular channel sequence length
impl W<u32, Reg<u32, _SQR2>>
impl W<u32, Reg<u32, _SQR3>>
impl W<u32, Reg<u32, _SQR4>>
impl W<u32, Reg<u32, _JSQR>>
pub fn jl(&mut self) -> JL_W<'_>
impl W<u32, Reg<u32, _OFR1>>
impl W<u32, Reg<u32, _OFR2>>
impl W<u32, Reg<u32, _OFR3>>
impl W<u32, Reg<u32, _OFR4>>
impl W<u32, Reg<u32, _AWD2CR>>
impl W<u32, Reg<u32, _AWD3CR>>
impl W<u32, Reg<u32, _DIFSEL>>
Bits 1:15 - Differential mode for channels 15 to 1
impl W<u32, Reg<u32, _CALFACT>>
impl W<u32, Reg<u32, _MODER>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
Bit 16 - Port x lock bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _MODER>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
Bit 16 - Port x lock bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _MODER>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
Bit 16 - Port x lock bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _CR1>>
Bits 20:23 - Master clock divider
Bit 16 - Audio block A enable
Bits 10:11 - Synchronization enable
Bit 9 - Clock strobing edge
Bit 8 - Least significant bit first
pub fn ds(&mut self) -> DS_W<'_>
Bits 2:3 - Protocol configuration
Bits 0:1 - Audio block mode
impl W<u32, Reg<u32, _CR2>>
Bits 14:15 - Companding mode
Bit 4 - Tristate management on data line
Bits 0:2 - FIFO threshold
impl W<u32, Reg<u32, _FRCR>>
Bit 18 - Frame synchronization offset
Bit 17 - Frame synchronization polarity
Bit 16 - Frame synchronization definition
Bits 8:14 - Frame synchronization active level length
impl W<u32, Reg<u32, _SLOTR>>
Bits 8:11 - Number of slots in an audio frame
Bits 0:4 - First bit offset
impl W<u32, Reg<u32, _IM>>
Bit 6 - Late frame synchronization detection interrupt enable
Bit 5 - Anticipated frame synchronization detection interrupt enable
Bit 4 - Codec not ready interrupt enable
Bit 3 - FIFO request interrupt enable
Bit 2 - Wrong clock configuration interrupt enable
Bit 1 - Mute detection interrupt enable
Bit 0 - Overrun/underrun interrupt enable
impl W<u32, Reg<u32, _SR>>
Bits 16:18 - FIFO level threshold
Bit 6 - Late frame synchronization detection
Bit 5 - Anticipated frame synchronization detection
Bit 2 - Wrong clock configuration flag. This bit is read only
Bit 0 - Overrun / underrun
impl W<u32, Reg<u32, _CLRFR>>
Bit 6 - Clear late frame synchronization detection flag
Bit 5 - Clear anticipated frame synchronization detection flag
Bit 4 - Clear codec not ready flag
Bit 2 - Clear wrong clock configuration flag
Bit 1 - Mute detection flag
Bit 0 - Clear overrun / underrun
impl W<u32, Reg<u32, _DR>>
impl W<u32, Reg<u32, _CR1>>
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
impl W<u32, Reg<u32, _CR2>>
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 15 - Output compare 2 clear enable
Bits 12:14 - Output compare 2 mode
Bit 11 - Output compare 2 preload enable
Bit 10 - Output compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output compare 1 clear enable
Bits 4:6 - Output compare 1 mode
Bit 3 - Output compare 1 preload enable
Bit 2 - Output compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
Bit 15 - Capture/Compare 4 output Polarity
Bit 13 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 9 - Capture/Compare 3 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 0:31 - Counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:31 - Auto-reload value
impl W<u32, Reg<u32, _CCR>>
Bits 0:31 - Capture/Compare 1 value
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR>>
Bits 0:2 - Timer2 ETR remap
Bits 3:4 - Internal trigger
impl W<u32, Reg<u32, _CR1>>
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
impl W<u32, Reg<u32, _CR2>>
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 7 - Break interrupt enable
Bit 6 - Trigger interrupt enable
Bit 5 - COM interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn bg(&mut self) -> BG_W<'_>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 16 - Output Compare 1 mode
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _RCR>>
Bits 0:7 - Repetition counter value
impl W<u32, Reg<u32, _CCR1>>
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _BDTR>>
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _CR1>>
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
impl W<u32, Reg<u32, _CR2>>
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 7 - Break interrupt enable
Bit 6 - Trigger interrupt enable
Bit 5 - COM interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn bg(&mut self) -> BG_W<'_>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 16 - Output Compare 1 mode
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _RCR>>
Bits 0:7 - Repetition counter value
impl W<u32, Reg<u32, _CCR1>>
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _BDTR>>
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR1>>
Bits 0:1 - Input capture 1 remap
impl W<u32, Reg<u32, _OR2>>
Bit 0 - BRK BKIN input enable
Bit 8 - BRK DFSDM_BREAK1 enable
Bit 9 - BRK BKIN input polarity
Bit 10 - BRK COMP1 input polarity
Bit 11 - BRK COMP2 input polarit
impl W<u32, Reg<u32, _CR1>>
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
impl W<u32, Reg<u32, _CR2>>
Bit 14 - Output Idle state 4
Bit 13 - Output Idle state 3
Bit 12 - Output Idle state 3
Bit 11 - Output Idle state 2
Bit 10 - Output Idle state 2
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 7 - Break interrupt enable
Bit 5 - COM interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn bg(&mut self) -> BG_W<'_>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 15 - Output Compare 2 clear enable
Bits 12:14 - Output Compare 2 mode
Bit 11 - Output Compare 2 preload enable
Bit 10 - Output Compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output Compare 1 clear enable
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/Compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/compare 3 selection
impl W<u32, Reg<u32, _CCER>>
Bit 13 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 10 - Capture/Compare 3 complementary output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 6 - Capture/Compare 2 complementary output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _RCR>>
Bits 0:7 - Repetition counter value
impl W<u32, Reg<u32, _CCR>>
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _BDTR>>
Bit 15 - Main output enable
Bit 14 - Automatic output enable
Bit 11 - Off-state selection for Run mode
Bit 10 - Off-state selection for Idle mode
Bits 8:9 - Lock configuration
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR1>>
Bits 0:1 - External trigger remap on ADC1 analog watchdog
Bits 2:3 - External trigger remap on ADC3 analog watchdog
Bit 4 - Input Capture 1 remap
impl W<u32, Reg<u32, _CCMR3_OUTPUT>>
Bit 24 - Output Compare 6 mode bit 3
Bits 16:18 - Output Compare 5 mode bit 3
Bit 15 - Output compare 6 clear enable
Bits 12:14 - Output compare 6 mode
Bit 11 - Output compare 6 preload enable
Bit 10 - Output compare 6 fast enable
Bit 7 - Output compare 5 clear enable
Bits 4:6 - Output compare 5 mode
Bit 3 - Output compare 5 preload enable
Bit 2 - Output compare 5 fast enable
impl W<u32, Reg<u32, _CCR5>>
Bits 0:15 - Capture/Compare value
Bit 29 - Group Channel 5 and Channel 1
Bit 30 - Group Channel 5 and Channel 2
Bit 31 - Group Channel 5 and Channel 3
impl W<u32, Reg<u32, _CCR6>>
Bits 0:15 - Capture/Compare value
impl W<u32, Reg<u32, _OR2>>
Bit 0 - BRK BKIN input enable
Bit 8 - BRK DFSDM_BREAK0 enable
Bit 9 - BRK BKIN input polarity
Bit 10 - BRK COMP1 input polarity
Bit 11 - BRK COMP2 input polarity
Bits 14:16 - ETR source selection
impl W<u32, Reg<u32, _OR3>>
Bit 0 - BRK2 BKIN input enable
Bit 1 - BRK2 COMP1 enable
Bit 2 - BRK2 COMP2 enable
Bit 8 - BRK2 DFSDM_BREAK0 enable
Bit 9 - BRK2 BKIN input polarity
Bit 10 - BRK2 COMP1 input polarity
Bit 11 - BRK2 COMP2 input polarity
impl W<u32, Reg<u32, _CR1>>
Bit 7 - Auto-reload preload enable
Bit 2 - Update request source
impl W<u32, Reg<u32, _CR2>>
Bits 4:6 - Master mode selection
impl W<u32, Reg<u32, _DIER>>
Bit 8 - Update DMA request enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - Low counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Low Auto-reload value
impl W<u32, Reg<u32, _ICR>>
Bit 6 - Direction change to down Clear Flag
Bit 5 - Direction change to UP Clear Flag
Bit 4 - Autoreload register update OK Clear Flag
Bit 3 - Compare register update OK Clear Flag
Bit 2 - External trigger valid edge Clear Flag
Bit 1 - Autoreload match Clear Flag
Bit 0 - compare match Clear Flag
impl W<u32, Reg<u32, _IER>>
Bit 6 - Direction change to down Interrupt Enable
Bit 5 - Direction change to UP Interrupt Enable
Bit 4 - Autoreload register update OK Interrupt Enable
Bit 3 - Compare register update OK Interrupt Enable
Bit 2 - External trigger valid edge Interrupt Enable
Bit 1 - Autoreload match Interrupt Enable
Bit 0 - Compare match Interrupt Enable
impl W<u32, Reg<u32, _CFGR>>
Bit 24 - Encoder mode enable
Bit 23 - counter mode enabled
Bit 22 - Registers update mode
Bit 21 - Waveform shape polarity
Bits 17:18 - Trigger enable and polarity
Bits 13:15 - Trigger selector
Bits 9:11 - Clock prescaler
Bits 6:7 - Configurable digital filter for trigger
Bits 3:4 - Configurable digital filter for external clock
Bits 1:2 - Clock Polarity
impl W<u32, Reg<u32, _CR>>
Bit 2 - Timer start in continuous mode
Bit 1 - LPTIM start in single mode
impl W<u32, Reg<u32, _CMP>>
Bits 0:15 - Compare value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto reload value
impl W<u32, Reg<u32, _CR1>>
pub fn m1(&mut self) -> M1_W<'_>
Bit 27 - End of Block interrupt enable
Bit 26 - Receiver timeout interrupt enable
Bit 15 - Oversampling mode
Bit 14 - Character match interrupt enable
Bit 13 - Mute mode enable
pub fn m0(&mut self) -> M0_W<'_>
Bit 11 - Receiver wakeup method
Bit 10 - Parity control enable
pub fn ps(&mut self) -> PS_W<'_>
Bit 8 - PE interrupt enable
Bit 6 - Transmission complete interrupt enable
Bit 5 - RXNE interrupt enable
Bit 4 - IDLE interrupt enable
pub fn te(&mut self) -> TE_W<'_>
Bit 3 - Transmitter enable
pub fn re(&mut self) -> RE_W<'_>
Bit 1 - USART enable in Stop mode
pub fn ue(&mut self) -> UE_W<'_>
Bits 16:20 - Driver Enable de-assertion time
Bits 21:25 - Driver Enable assertion time
impl W<u32, Reg<u32, _CR2>>
Bit 23 - Receiver timeout enable
Bit 20 - Auto baud rate enable
Bit 19 - Most significant bit first
Bit 18 - Binary data inversion
Bit 17 - TX pin active level inversion
Bit 16 - RX pin active level inversion
Bit 8 - Last bit clock pulse
Bit 6 - LIN break detection interrupt enable
Bit 5 - LIN break detection length
Bit 4 - 7-bit Address Detection/4-bit Address Detection
Bits 24:31 - Address of the USART node
Bits 21:22 - Auto baud rate mode
impl W<u32, Reg<u32, _CR3>>
Bit 22 - Wakeup from Stop mode interrupt enable
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
Bits 17:19 - Smartcard auto-retry count
Bit 15 - Driver enable polarity selection
Bit 14 - Driver enable mode
Bit 13 - DMA Disable on Reception Error
Bit 11 - One sample bit method enable
Bit 10 - CTS interrupt enable
Bit 7 - DMA enable transmitter
Bit 6 - DMA enable receiver
Bit 5 - Smartcard mode enable
Bit 4 - Smartcard NACK enable
Bit 3 - Half-duplex selection
Bit 0 - Error interrupt enable
impl W<u32, Reg<u32, _BRR>>
impl W<u32, Reg<u32, _GTPR>>
pub fn gt(&mut self) -> GT_W<'_>
Bits 8:15 - Guard time value
Bits 0:7 - Prescaler value
impl W<u32, Reg<u32, _RTOR>>
Bits 24:31 - Block Length
Bits 0:23 - Receiver timeout value
impl W<u32, Reg<u32, _RQR>>
Bit 4 - Transmit data flush request
Bit 3 - Receive data flush request
Bit 2 - Mute mode request
Bit 1 - Send break request
Bit 0 - Auto baud rate request
impl W<u32, Reg<u32, _ICR>>
Bit 20 - Wakeup from Stop mode clear flag
Bit 17 - Character match clear flag
Bit 12 - End of block clear flag
Bit 11 - Receiver timeout clear flag
Bit 8 - LIN break detection clear flag
Bit 6 - Transmission complete clear flag
Bit 4 - Idle line detected clear flag
Bit 3 - Overrun error clear flag
Bit 2 - Noise detected clear flag
Bit 1 - Framing error clear flag
Bit 0 - Parity error clear flag
impl W<u32, Reg<u32, _TDR>>
Bits 0:8 - Transmit data value
impl W<u32, Reg<u32, _CR1>>
pub fn m1(&mut self) -> M1_W<'_>
Bit 27 - End of Block interrupt enable
Bit 26 - Receiver timeout interrupt enable
Bit 15 - Oversampling mode
Bit 14 - Character match interrupt enable
Bit 13 - Mute mode enable
pub fn m0(&mut self) -> M0_W<'_>
Bit 11 - Receiver wakeup method
Bit 10 - Parity control enable
pub fn ps(&mut self) -> PS_W<'_>
Bit 8 - PE interrupt enable
Bit 6 - Transmission complete interrupt enable
Bit 5 - RXNE interrupt enable
Bit 4 - IDLE interrupt enable
pub fn te(&mut self) -> TE_W<'_>
Bit 3 - Transmitter enable
pub fn re(&mut self) -> RE_W<'_>
Bit 1 - USART enable in Stop mode
pub fn ue(&mut self) -> UE_W<'_>
Bits 16:20 - Driver Enable de-assertion time
Bits 21:25 - Driver Enable assertion time
impl W<u32, Reg<u32, _CR2>>
Bit 23 - Receiver timeout enable
Bit 20 - Auto baud rate enable
Bit 19 - Most significant bit first
Bit 18 - Binary data inversion
Bit 17 - TX pin active level inversion
Bit 16 - RX pin active level inversion
Bit 8 - Last bit clock pulse
Bit 6 - LIN break detection interrupt enable
Bit 5 - LIN break detection length
Bit 4 - 7-bit Address Detection/4-bit Address Detection
Bits 24:31 - Address of the USART node
Bits 21:22 - Auto baud rate mode
impl W<u32, Reg<u32, _CR3>>
Bit 22 - Wakeup from Stop mode interrupt enable
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
Bits 17:19 - Smartcard auto-retry count
Bit 15 - Driver enable polarity selection
Bit 14 - Driver enable mode
Bit 13 - DMA Disable on Reception Error
Bit 11 - One sample bit method enable
Bit 10 - CTS interrupt enable
Bit 7 - DMA enable transmitter
Bit 6 - DMA enable receiver
Bit 5 - Smartcard mode enable
Bit 4 - Smartcard NACK enable
Bit 3 - Half-duplex selection
Bit 0 - Error interrupt enable
Bit 23 - USART Clock Enable in Stop mode
Bit 24 - Transmission complete before guard time interrupt enable
impl W<u32, Reg<u32, _BRR>>
impl W<u32, Reg<u32, _GTPR>>
pub fn gt(&mut self) -> GT_W<'_>
Bits 8:15 - Guard time value
Bits 0:7 - Prescaler value
impl W<u32, Reg<u32, _RTOR>>
Bits 24:31 - Block Length
Bits 0:23 - Receiver timeout value
impl W<u32, Reg<u32, _RQR>>
Bit 4 - Transmit data flush request
Bit 3 - Receive data flush request
Bit 2 - Mute mode request
Bit 1 - Send break request
Bit 0 - Auto baud rate request
impl W<u32, Reg<u32, _ICR>>
Bit 20 - Wakeup from Stop mode clear flag
Bit 17 - Character match clear flag
Bit 12 - End of block clear flag
Bit 11 - Receiver timeout clear flag
Bit 8 - LIN break detection clear flag
Bit 6 - Transmission complete clear flag
Bit 4 - Idle line detected clear flag
Bit 3 - Overrun error clear flag
Bit 2 - Noise detected clear flag
Bit 1 - Framing error clear flag
Bit 0 - Parity error clear flag
impl W<u32, Reg<u32, _TDR>>
Bits 0:8 - Transmit data value
impl W<u32, Reg<u32, _CR1>>
pub fn m1(&mut self) -> M1_W<'_>
Bit 14 - Character match interrupt enable
Bit 13 - Mute mode enable
pub fn m0(&mut self) -> M0_W<'_>
Bit 11 - Receiver wakeup method
Bit 10 - Parity control enable
pub fn ps(&mut self) -> PS_W<'_>
Bit 8 - PE interrupt enable
Bit 6 - Transmission complete interrupt enable
Bit 5 - RXNE interrupt enable
Bit 4 - IDLE interrupt enable
pub fn te(&mut self) -> TE_W<'_>
Bit 3 - Transmitter enable
pub fn re(&mut self) -> RE_W<'_>
Bit 1 - USART enable in Stop mode
pub fn ue(&mut self) -> UE_W<'_>
Bits 21:25 - Driver Enable assertion time
Bits 16:20 - Driver Enable de-assertion time
impl W<u32, Reg<u32, _CR2>>
Bit 19 - Most significant bit first
Bit 18 - Binary data inversion
Bit 17 - TX pin active level inversion
Bit 16 - RX pin active level inversion
Bit 4 - 7-bit Address Detection/4-bit Address Detection
Bits 24:31 - Address of the USART node
impl W<u32, Reg<u32, _CR3>>
Bit 22 - Wakeup from Stop mode interrupt enable
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
Bit 15 - Driver enable polarity selection
Bit 14 - Driver enable mode
Bit 13 - DMA Disable on Reception Error
Bit 10 - CTS interrupt enable
Bit 7 - DMA enable transmitter
Bit 6 - DMA enable receiver
Bit 3 - Half-duplex selection
Bit 0 - Error interrupt enable
impl W<u32, Reg<u32, _BRR>>
impl W<u32, Reg<u32, _RQR>>
Bit 3 - Receive data flush request
Bit 2 - Mute mode request
Bit 1 - Send break request
impl W<u32, Reg<u32, _ICR>>
Bit 20 - Wakeup from Stop mode clear flag
Bit 17 - Character match clear flag
Bit 6 - Transmission complete clear flag
Bit 4 - Idle line detected clear flag
Bit 3 - Overrun error clear flag
Bit 2 - Noise detected clear flag
Bit 1 - Framing error clear flag
Bit 0 - Parity error clear flag
impl W<u32, Reg<u32, _TDR>>
Bits 0:8 - Transmit data value
impl W<u32, Reg<u32, _CR1>>
Bit 15 - Bidirectional data mode enable
Bit 14 - Output enable in bidirectional mode
Bit 13 - Hardware CRC calculation enable
Bit 12 - CRC transfer next
Bit 9 - Software slave management
Bit 8 - Internal slave select
pub fn br(&mut self) -> BR_W<'_>
Bits 3:5 - Baud rate control
impl W<u32, Reg<u32, _CR2>>
Bit 0 - Rx buffer DMA enable
Bit 1 - Tx buffer DMA enable
Bit 3 - NSS pulse management
Bit 5 - Error interrupt enable
Bit 6 - RX buffer not empty interrupt enable
Bit 7 - Tx buffer empty interrupt enable
pub fn ds(&mut self) -> DS_W<'_>
Bit 12 - FIFO reception threshold
Bit 13 - Last DMA transfer for reception
Bit 14 - Last DMA transfer for transmission
impl W<u32, Reg<u32, _SR>>
impl W<u32, Reg<u32, _DR>>
pub fn dr(&mut self) -> DR_W<'_>
Bits 0:15 - Data register
impl W<u32, Reg<u32, _CRCPR>>
Bits 0:15 - CRC polynomial register
impl W<u32, Reg<u32, _POWER>>
impl W<u32, Reg<u32, _CLKCR>>
Bit 14 - HW Flow Control enable
Bit 13 - SDIO_CK dephasing selection bit
Bits 11:12 - Wide bus mode enable bit
Bit 10 - Clock divider bypass enable bit
Bit 9 - Power saving configuration bit
Bits 0:7 - Clock divide factor
impl W<u32, Reg<u32, _ARG>>
Bits 0:31 - Command argument
impl W<u32, Reg<u32, _CMD>>
Bit 13 - not Interrupt Enable
Bit 12 - Enable CMD completion
Bit 11 - SD I/O suspend command
Bit 10 - Command path state machine (CPSM) Enable bit
Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)
Bit 8 - CPSM waits for interrupt request
Bits 6:7 - Wait for response bits
impl W<u32, Reg<u32, _DTIMER>>
Bits 0:31 - Data timeout period
impl W<u32, Reg<u32, _DLEN>>
Bits 0:24 - Data length value
impl W<u32, Reg<u32, _DCTRL>>
Bit 11 - SD I/O enable functions
Bits 4:7 - Data block size
Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer
Bit 1 - Data transfer direction selection
impl W<u32, Reg<u32, _ICR>>
Bit 23 - CEATAEND flag clear bit
Bit 22 - SDIOIT flag clear bit
Bit 10 - DBCKEND flag clear bit
Bit 9 - STBITERR flag clear bit
Bit 8 - DATAEND flag clear bit
Bit 7 - CMDSENT flag clear bit
Bit 6 - CMDREND flag clear bit
Bit 5 - RXOVERR flag clear bit
Bit 4 - TXUNDERR flag clear bit
Bit 3 - DTIMEOUT flag clear bit
Bit 2 - CTIMEOUT flag clear bit
Bit 1 - DCRCFAIL flag clear bit
Bit 0 - CCRCFAIL flag clear bit
impl W<u32, Reg<u32, _MASK>>
Bit 23 - CE-ATA command completion signal received interrupt enable
Bit 22 - SDIO mode interrupt received interrupt enable
Bit 21 - Data available in Rx FIFO interrupt enable
Bit 20 - Data available in Tx FIFO interrupt enable
Bit 19 - Rx FIFO empty interrupt enable
Bit 18 - Tx FIFO empty interrupt enable
Bit 17 - Rx FIFO full interrupt enable
Bit 16 - Tx FIFO full interrupt enable
Bit 15 - Rx FIFO half full interrupt enable
Bit 14 - Tx FIFO half empty interrupt enable
Bit 13 - Data receive acting interrupt enable
Bit 12 - Data transmit acting interrupt enable
Bit 11 - Command acting interrupt enable
Bit 10 - Data block end interrupt enable
Bit 9 - Start bit error interrupt enable
Bit 8 - Data end interrupt enable
Bit 7 - Command sent interrupt enable
Bit 6 - Command response received interrupt enable
Bit 5 - Rx FIFO overrun error interrupt enable
Bit 4 - Tx FIFO underrun error interrupt enable
Bit 3 - Data timeout interrupt enable
Bit 2 - Command timeout interrupt enable
Bit 1 - Data CRC fail interrupt enable
Bit 0 - Command CRC fail interrupt enable
impl W<u32, Reg<u32, _FIFO>>
Bits 0:31 - Receive and transmit FIFO data
impl W<u32, Reg<u32, _IMR1>>
Bit 0 - Interrupt Mask on line 0
Bit 1 - Interrupt Mask on line 1
Bit 2 - Interrupt Mask on line 2
Bit 3 - Interrupt Mask on line 3
Bit 4 - Interrupt Mask on line 4
Bit 5 - Interrupt Mask on line 5
Bit 6 - Interrupt Mask on line 6
Bit 7 - Interrupt Mask on line 7
Bit 8 - Interrupt Mask on line 8
Bit 9 - Interrupt Mask on line 9
Bit 10 - Interrupt Mask on line 10
Bit 11 - Interrupt Mask on line 11
Bit 12 - Interrupt Mask on line 12
Bit 13 - Interrupt Mask on line 13
Bit 14 - Interrupt Mask on line 14
Bit 15 - Interrupt Mask on line 15
Bit 16 - Interrupt Mask on line 16
Bit 17 - Interrupt Mask on line 17
Bit 18 - Interrupt Mask on line 18
Bit 19 - Interrupt Mask on line 19
Bit 20 - Interrupt Mask on line 20
Bit 21 - Interrupt Mask on line 21
Bit 22 - Interrupt Mask on line 22
Bit 23 - Interrupt Mask on line 23
Bit 24 - Interrupt Mask on line 24
Bit 25 - Interrupt Mask on line 25
Bit 26 - Interrupt Mask on line 26
Bit 27 - Interrupt Mask on line 27
Bit 28 - Interrupt Mask on line 28
Bit 29 - Interrupt Mask on line 29
Bit 30 - Interrupt Mask on line 30
Bit 31 - Interrupt Mask on line 31
impl W<u32, Reg<u32, _EMR1>>
Bit 0 - Event Mask on line 0
Bit 1 - Event Mask on line 1
Bit 2 - Event Mask on line 2
Bit 3 - Event Mask on line 3
Bit 4 - Event Mask on line 4
Bit 5 - Event Mask on line 5
Bit 6 - Event Mask on line 6
Bit 7 - Event Mask on line 7
Bit 8 - Event Mask on line 8
Bit 9 - Event Mask on line 9
Bit 10 - Event Mask on line 10
Bit 11 - Event Mask on line 11
Bit 12 - Event Mask on line 12
Bit 13 - Event Mask on line 13
Bit 14 - Event Mask on line 14
Bit 15 - Event Mask on line 15
Bit 16 - Event Mask on line 16
Bit 17 - Event Mask on line 17
Bit 18 - Event Mask on line 18
Bit 19 - Event Mask on line 19
Bit 20 - Event Mask on line 20
Bit 21 - Event Mask on line 21
Bit 22 - Event Mask on line 22
Bit 23 - Event Mask on line 23
Bit 24 - Event Mask on line 24
Bit 25 - Event Mask on line 25
Bit 26 - Event Mask on line 26
Bit 27 - Event Mask on line 27
Bit 28 - Event Mask on line 28
Bit 29 - Event Mask on line 29
Bit 30 - Event Mask on line 30
Bit 31 - Event Mask on line 31
impl W<u32, Reg<u32, _RTSR1>>
Bit 0 - Rising trigger event configuration of line 0
Bit 1 - Rising trigger event configuration of line 1
Bit 2 - Rising trigger event configuration of line 2
Bit 3 - Rising trigger event configuration of line 3
Bit 4 - Rising trigger event configuration of line 4
Bit 5 - Rising trigger event configuration of line 5
Bit 6 - Rising trigger event configuration of line 6
Bit 7 - Rising trigger event configuration of line 7
Bit 8 - Rising trigger event configuration of line 8
Bit 9 - Rising trigger event configuration of line 9
Bit 10 - Rising trigger event configuration of line 10
Bit 11 - Rising trigger event configuration of line 11
Bit 12 - Rising trigger event configuration of line 12
Bit 13 - Rising trigger event configuration of line 13
Bit 14 - Rising trigger event configuration of line 14
Bit 15 - Rising trigger event configuration of line 15
Bit 16 - Rising trigger event configuration of line 16
Bit 18 - Rising trigger event configuration of line 18
Bit 19 - Rising trigger event configuration of line 19
Bit 20 - Rising trigger event configuration of line 20
Bit 21 - Rising trigger event configuration of line 21
Bit 22 - Rising trigger event configuration of line 22
impl W<u32, Reg<u32, _FTSR1>>
Bit 0 - Falling trigger event configuration of line 0
Bit 1 - Falling trigger event configuration of line 1
Bit 2 - Falling trigger event configuration of line 2
Bit 3 - Falling trigger event configuration of line 3
Bit 4 - Falling trigger event configuration of line 4
Bit 5 - Falling trigger event configuration of line 5
Bit 6 - Falling trigger event configuration of line 6
Bit 7 - Falling trigger event configuration of line 7
Bit 8 - Falling trigger event configuration of line 8
Bit 9 - Falling trigger event configuration of line 9
Bit 10 - Falling trigger event configuration of line 10
Bit 11 - Falling trigger event configuration of line 11
Bit 12 - Falling trigger event configuration of line 12
Bit 13 - Falling trigger event configuration of line 13
Bit 14 - Falling trigger event configuration of line 14
Bit 15 - Falling trigger event configuration of line 15
Bit 16 - Falling trigger event configuration of line 16
Bit 18 - Falling trigger event configuration of line 18
Bit 19 - Falling trigger event configuration of line 19
Bit 20 - Falling trigger event configuration of line 20
Bit 21 - Falling trigger event configuration of line 21
Bit 22 - Falling trigger event configuration of line 22
impl W<u32, Reg<u32, _SWIER1>>
Bit 0 - Software Interrupt on line 0
Bit 1 - Software Interrupt on line 1
Bit 2 - Software Interrupt on line 2
Bit 3 - Software Interrupt on line 3
Bit 4 - Software Interrupt on line 4
Bit 5 - Software Interrupt on line 5
Bit 6 - Software Interrupt on line 6
Bit 7 - Software Interrupt on line 7
Bit 8 - Software Interrupt on line 8
Bit 9 - Software Interrupt on line 9
Bit 10 - Software Interrupt on line 10
Bit 11 - Software Interrupt on line 11
Bit 12 - Software Interrupt on line 12
Bit 13 - Software Interrupt on line 13
Bit 14 - Software Interrupt on line 14
Bit 15 - Software Interrupt on line 15
Bit 16 - Software Interrupt on line 16
Bit 18 - Software Interrupt on line 18
Bit 19 - Software Interrupt on line 19
Bit 20 - Software Interrupt on line 20
Bit 21 - Software Interrupt on line 21
Bit 22 - Software Interrupt on line 22
impl W<u32, Reg<u32, _PR1>>
impl W<u32, Reg<u32, _IMR2>>
Bit 0 - Interrupt Mask on external/internal line 32
Bit 1 - Interrupt Mask on external/internal line 33
Bit 2 - Interrupt Mask on external/internal line 34
Bit 3 - Interrupt Mask on external/internal line 35
Bit 4 - Interrupt Mask on external/internal line 36
Bit 5 - Interrupt Mask on external/internal line 37
Bit 6 - Interrupt Mask on external/internal line 38
Bit 7 - Interrupt Mask on external/internal line 39
impl W<u32, Reg<u32, _EMR2>>
Bit 0 - Event mask on external/internal line 32
Bit 1 - Event mask on external/internal line 33
Bit 2 - Event mask on external/internal line 34
Bit 3 - Event mask on external/internal line 35
Bit 4 - Event mask on external/internal line 36
Bit 5 - Event mask on external/internal line 37
Bit 6 - Event mask on external/internal line 38
Bit 7 - Event mask on external/internal line 39
impl W<u32, Reg<u32, _RTSR2>>
Bit 3 - Rising trigger event configuration bit of line 35
Bit 4 - Rising trigger event configuration bit of line 36
Bit 5 - Rising trigger event configuration bit of line 37
Bit 6 - Rising trigger event configuration bit of line 38
impl W<u32, Reg<u32, _FTSR2>>
Bit 3 - Falling trigger event configuration bit of line 35
Bit 4 - Falling trigger event configuration bit of line 36
Bit 5 - Falling trigger event configuration bit of line 37
Bit 6 - Falling trigger event configuration bit of line 38
impl W<u32, Reg<u32, _SWIER2>>
Bit 3 - Software interrupt on line 35
Bit 4 - Software interrupt on line 36
Bit 5 - Software interrupt on line 37
Bit 6 - Software interrupt on line 38
impl W<u32, Reg<u32, _PR2>>
Bit 3 - Pending interrupt flag on line 35
Bit 4 - Pending interrupt flag on line 36
Bit 5 - Pending interrupt flag on line 37
Bit 6 - Pending interrupt flag on line 38
impl W<u32, Reg<u32, _CSR>>
Bit 0 - Voltage reference buffer enable
Bit 1 - High impedance mode
Bit 2 - Voltage reference scale
impl W<u32, Reg<u32, _CCR>>
impl W<u32, Reg<u32, _TIR>>
impl W<u32, Reg<u32, _TDTR>>
impl W<u32, Reg<u32, _TDLR>>
impl W<u32, Reg<u32, _TDHR>>
impl W<u32, Reg<u32, _FR1>>
pub fn fb(&mut self) -> FB_W<'_>
impl W<u32, Reg<u32, _FR2>>
pub fn fb(&mut self) -> FB_W<'_>
impl W<u32, Reg<u32, _MCR>>
impl W<u32, Reg<u32, _MSR>>
impl W<u32, Reg<u32, _TSR>>
impl W<u32, Reg<u32, _RFR>>
impl W<u32, Reg<u32, _IER>>
impl W<u32, Reg<u32, _ESR>>
impl W<u32, Reg<u32, _BTR>>
impl W<u32, Reg<u32, _FMR>>
Bit 0 - Filter initialization mode
impl W<u32, Reg<u32, _FM1R>>
impl W<u32, Reg<u32, _FS1R>>
Bit 0 - Filter scale configuration
Bit 1 - Filter scale configuration
Bit 2 - Filter scale configuration
Bit 3 - Filter scale configuration
Bit 4 - Filter scale configuration
Bit 5 - Filter scale configuration
Bit 6 - Filter scale configuration
Bit 7 - Filter scale configuration
Bit 8 - Filter scale configuration
Bit 9 - Filter scale configuration
Bit 10 - Filter scale configuration
Bit 11 - Filter scale configuration
Bit 12 - Filter scale configuration
Bit 13 - Filter scale configuration
impl W<u32, Reg<u32, _FFA1R>>
Bit 0 - Filter FIFO assignment for filter 0
Bit 1 - Filter FIFO assignment for filter 1
Bit 2 - Filter FIFO assignment for filter 2
Bit 3 - Filter FIFO assignment for filter 3
Bit 4 - Filter FIFO assignment for filter 4
Bit 5 - Filter FIFO assignment for filter 5
Bit 6 - Filter FIFO assignment for filter 6
Bit 7 - Filter FIFO assignment for filter 7
Bit 8 - Filter FIFO assignment for filter 8
Bit 9 - Filter FIFO assignment for filter 9
Bit 10 - Filter FIFO assignment for filter 10
Bit 11 - Filter FIFO assignment for filter 11
Bit 12 - Filter FIFO assignment for filter 12
Bit 13 - Filter FIFO assignment for filter 13
impl W<u32, Reg<u32, _FA1R>>
impl W<u32, Reg<u32, _TR>>
pub fn pm(&mut self) -> PM_W<'_>
pub fn ht(&mut self) -> HT_W<'_>
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
Bits 16:19 - Hour units in BCD format
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
pub fn st(&mut self) -> ST_W<'_>
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _DR>>
pub fn yt(&mut self) -> YT_W<'_>
Bits 20:23 - Year tens in BCD format
pub fn yu(&mut self) -> YU_W<'_>
Bits 16:19 - Year units in BCD format
Bits 13:15 - Week day units
pub fn mt(&mut self) -> MT_W<'_>
Bit 12 - Month tens in BCD format
pub fn mu(&mut self) -> MU_W<'_>
Bits 8:11 - Month units in BCD format
pub fn dt(&mut self) -> DT_W<'_>
Bits 4:5 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
Bits 0:3 - Date units in BCD format
impl W<u32, Reg<u32, _CR>>
Bits 0:2 - Wakeup clock selection
Bit 3 - Time-stamp event active edge
Bit 4 - Reference clock detection enable (50 or 60 Hz)
Bit 5 - Bypass the shadow registers
Bit 10 - Wakeup timer enable
Bit 11 - Time stamp enable
Bit 12 - Alarm A interrupt enable
Bit 13 - Alarm B interrupt enable
Bit 14 - Wakeup timer interrupt enable
Bit 15 - Time-stamp interrupt enable
Bit 16 - Add 1 hour (summer time change)
Bit 17 - Subtract 1 hour (winter time change)
Bit 19 - Calibration output selection
Bits 21:22 - Output selection
Bit 23 - Calibration output enable
Bit 24 - timestamp on internal event enable
impl W<u32, Reg<u32, _ISR>>
Bit 3 - Shift operation pending
Bit 5 - Registers synchronization flag
Bit 7 - Initialization mode
Bit 10 - Wakeup timer flag
Bit 12 - Time-stamp overflow flag
Bit 13 - Tamper detection flag
Bit 14 - RTC_TAMP2 detection flag
Bit 15 - RTC_TAMP3 detection flag
impl W<u32, Reg<u32, _PRER>>
Bits 16:22 - Asynchronous prescaler factor
Bits 0:14 - Synchronous prescaler factor
impl W<u32, Reg<u32, _WUTR>>
Bits 0:15 - Wakeup auto-reload value bits
impl W<u32, Reg<u32, _ALRMAR>>
Bit 31 - Alarm A date mask
Bit 30 - Week day selection
pub fn dt(&mut self) -> DT_W<'_>
Bits 28:29 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm A hours mask
pub fn pm(&mut self) -> PM_W<'_>
pub fn ht(&mut self) -> HT_W<'_>
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm A minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm A seconds mask
pub fn st(&mut self) -> ST_W<'_>
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _ALRMBR>>
Bit 31 - Alarm B date mask
Bit 30 - Week day selection
pub fn dt(&mut self) -> DT_W<'_>
Bits 28:29 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm B hours mask
pub fn pm(&mut self) -> PM_W<'_>
pub fn ht(&mut self) -> HT_W<'_>
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm B minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm B seconds mask
pub fn st(&mut self) -> ST_W<'_>
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _WPR>>
Bits 0:7 - Write protection key
impl W<u32, Reg<u32, _SHIFTR>>
Bits 0:14 - Subtract a fraction of a second
impl W<u32, Reg<u32, _CALR>>
Bit 15 - Increase frequency of RTC by 488.5 ppm
Bit 14 - Use an 8-second calibration cycle period
Bit 13 - Use a 16-second calibration cycle period
Bits 0:8 - Calibration minus
impl W<u32, Reg<u32, _TAMPCR>>
Bit 0 - Tamper 1 detection enable
Bit 1 - Active level for tamper 1
Bit 2 - Tamper interrupt enable
Bit 3 - Tamper 2 detection enable
Bit 4 - Active level for tamper 2
Bit 5 - Tamper 3 detection enable
Bit 6 - Active level for tamper 3
Bit 7 - Activate timestamp on tamper detection event
Bits 8:10 - Tamper sampling frequency
Bits 11:12 - Tamper filter count
Bits 13:14 - Tamper precharge duration
Bit 15 - TAMPER pull-up disable
Bit 16 - Tamper 1 interrupt enable
Bit 17 - Tamper 1 no erase
Bit 18 - Tamper 1 mask flag
Bit 19 - Tamper 2 interrupt enable
Bit 20 - Tamper 2 no erase
Bit 21 - Tamper 2 mask flag
Bit 22 - Tamper 3 interrupt enable
Bit 23 - Tamper 3 no erase
Bit 24 - Tamper 3 mask flag
impl W<u32, Reg<u32, _ALRMASSR>>
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&mut self) -> SS_W<'_>
Bits 0:14 - Sub seconds value
impl W<u32, Reg<u32, _ALRMBSSR>>
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&mut self) -> SS_W<'_>
Bits 0:14 - Sub seconds value
impl W<u32, Reg<u32, _OR>>
Bit 0 - RTC_ALARM on PC13 output type
impl W<u32, Reg<u32, _BKPR>>
impl W<u32, Reg<u32, _CR>>
Bit 0 - Reception DMA enable
Bit 1 - Transmission DMA enable
Bit 2 - Reception buffering mode
Bit 3 - Transmission buffering mode
Bit 4 - Loopback mode enable
Bit 5 - Single wire protocol master interface enable
Bit 10 - Single wire protocol master interface deactivate
impl W<u32, Reg<u32, _BRR>>
pub fn br(&mut self) -> BR_W<'_>
Bits 0:5 - Bitrate prescaler
impl W<u32, Reg<u32, _ICR>>
Bit 0 - Clear receive buffer full flag
Bit 1 - Clear transmit buffer empty flag
Bit 2 - Clear receive CRC error flag
Bit 3 - Clear receive overrun error flag
Bit 4 - Clear transmit underrun error flag
Bit 7 - Clear transfer complete flag
Bit 8 - Clear slave resume flag
impl W<u32, Reg<u32, _IER>>
Bit 0 - Receive buffer full interrupt enable
Bit 1 - Transmit buffer empty interrupt enable
Bit 2 - Receive CRC error interrupt enable
Bit 3 - Receive overrun error interrupt enable
Bit 4 - Transmit underrun error interrupt enable
Bit 5 - Receive interrupt enable
Bit 6 - Transmit interrupt enable
Bit 7 - Transmit complete interrupt enable
Bit 8 - Slave resume interrupt enable
impl W<u32, Reg<u32, _TDR>>
pub fn td(&mut self) -> TD_W<'_>
Bits 0:31 - Transmit data
impl W<u32, Reg<u32, _OPAMP1_CSR>>
Bit 0 - Operational amplifier Enable
Bit 1 - Operational amplifier Low Power Mode
Bits 2:3 - Operational amplifier PGA mode
Bits 4:5 - Operational amplifier Programmable amplifier gain value
Bits 8:9 - Inverting input selection
Bit 10 - Non inverted input selection
Bit 12 - Calibration mode enabled
Bit 13 - Calibration selection
Bit 14 - allows to switch from AOP offset trimmed values to AOP offset
Bit 15 - Operational amplifier calibration output
Bit 31 - Operational amplifier power supply range for stability
impl W<u32, Reg<u32, _OPAMP1_OTR>>
Bits 0:4 - Trim for NMOS differential pairs
Bits 8:12 - Trim for PMOS differential pairs
impl W<u32, Reg<u32, _OPAMP1_LPOTR>>
Bits 0:4 - Trim for NMOS differential pairs
Bits 8:12 - Trim for PMOS differential pairs
impl W<u32, Reg<u32, _OPAMP2_CSR>>
Bit 0 - Operational amplifier Enable
Bit 1 - Operational amplifier Low Power Mode
Bits 2:3 - Operational amplifier PGA mode
Bits 4:5 - Operational amplifier Programmable amplifier gain value
Bits 8:9 - Inverting input selection
Bit 10 - Non inverted input selection
Bit 12 - Calibration mode enabled
Bit 13 - Calibration selection
Bit 14 - allows to switch from AOP offset trimmed values to AOP offset
Bit 15 - Operational amplifier calibration output
impl W<u32, Reg<u32, _OPAMP2_OTR>>
Bits 0:4 - Trim for NMOS differential pairs
Bits 8:12 - Trim for PMOS differential pairs
impl W<u32, Reg<u32, _OPAMP2_LPOTR>>
Bits 0:4 - Trim for NMOS differential pairs
Bits 8:12 - Trim for PMOS differential pairs
impl W<u32, Reg<u32, _CR>>
Bits 8:13 - HSI48 oscillator smooth trimming
Bit 7 - Generate software SYNC event
Bit 6 - Automatic trimming enable
Bit 5 - Frequency error counter enable
Bit 3 - Expected SYNC interrupt enable
Bit 2 - Synchronization or trimming error interrupt enable
Bit 1 - SYNC warning interrupt enable
Bit 0 - SYNC event OK interrupt enable
impl W<u32, Reg<u32, _CFGR>>
Bit 31 - SYNC polarity selection
Bits 28:29 - SYNC signal source selection
Bits 24:26 - SYNC divider
Bits 16:23 - Frequency error limit
Bits 0:15 - Counter reload value
impl W<u32, Reg<u32, _ICR>>
Bit 3 - Expected SYNC clear flag
Bit 1 - SYNC warning clear flag
Bit 0 - SYNC event OK clear flag
impl W<u32, Reg<u32, _EP0R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP1R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP2R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP3R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP4R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP5R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP6R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP7R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _CNTR>>
Bit 5 - LPM L1 Resume request
Bit 7 - LPM L1 state request interrupt mask
Bit 8 - Expected start of frame interrupt mask
Bit 9 - Start of frame interrupt mask
Bit 10 - USB reset interrupt mask
Bit 11 - Suspend mode interrupt mask
Bit 12 - Wakeup interrupt mask
Bit 13 - Error interrupt mask
Bit 14 - Packet memory area over / underrun interrupt mask
Bit 15 - Correct transfer interrupt mask
impl W<u32, Reg<u32, _ISTR>>
Bit 7 - LPM L1 state request
Bit 8 - Expected start frame
Bit 11 - Suspend mode request
Bit 14 - Packet memory area over / underrun
impl W<u32, Reg<u32, _DADDR>>
Bits 0:6 - Device address
pub fn ef(&mut self) -> EF_W<'_>
impl W<u32, Reg<u32, _BTABLE>>
impl W<u32, Reg<u32, _LPMCSR>>
Bit 0 - LPM support enable
Bit 1 - LPM Token acknowledge enable
impl W<u32, Reg<u32, _BCDR>>
Bit 0 - Battery charging detector
Bit 1 - Data contact detection
Bit 2 - Primary detection
Bit 3 - Secondary detection
Bit 15 - DP pull-up control
impl W<u32, Reg<u32, _CFGR1>>
impl W<u32, Reg<u32, _CFGR2>>
impl W<u32, Reg<u32, _AWSCDR>>
impl W<u32, Reg<u32, _WDATR>>
impl W<u32, Reg<u32, _DATINR>>
impl W<u32, Reg<u32, _CR2>>
Bit 30 - Analog watchdog fast mode select
Bit 29 - Fast conversion mode selection for regular conversions
Bits 24:26 - Regular channel selection
Bit 21 - DMA channel enabled to read data for the regular conversion
Bit 19 - Launch regular conversion synchronously with DFSDM0
Bit 18 - Continuous mode selection for regular conversions
Bit 17 - Software start of a conversion on the regular channel
Bits 13:14 - Trigger enable and trigger edge selection for injected conversions
Bits 8:10 - Trigger signal selection for launching injected conversions
Bit 5 - DMA channel enabled to read data for the injected channel group
Bit 4 - Scanning conversion mode for injected conversions
Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
Bit 1 - Start a conversion of the injected group of channels
impl W<u32, Reg<u32, _ICR>>
Bits 24:31 - Clear the short-circuit detector flag
Bits 16:23 - Clear the clock absence flag
Bit 3 - Clear the regular conversion overrun flag
Bit 2 - Clear the injected conversion overrun flag
impl W<u32, Reg<u32, _JCHGR>>
Bits 0:7 - Injected channel group selection
impl W<u32, Reg<u32, _FCR>>
Bits 29:31 - Sinc filter order
Bits 16:25 - Sinc filter oversampling ratio (decimation rate)
Bits 0:7 - Integrator oversampling ratio (averaging length)
impl W<u32, Reg<u32, _AWHTR>>
Bits 8:31 - Analog watchdog high threshold
Bits 0:3 - Break signal assignment to analog watchdog high threshold event
impl W<u32, Reg<u32, _AWLTR>>
Bits 8:31 - Analog watchdog low threshold
Bits 0:3 - Break signal assignment to analog watchdog low threshold event
impl W<u32, Reg<u32, _AWCFR>>
Bits 8:15 - Clear the analog watchdog high threshold flag
Bits 0:7 - Clear the analog watchdog low threshold flag
impl W<u32, Reg<u32, _DFSDM0_CR2>>
Bits 16:23 - Analog watchdog channel selection
Bits 8:15 - Extremes detector channel selection
Bit 6 - Clock absence interrupt enable
Bit 5 - Short-circuit detector interrupt enable
Bit 4 - Analog watchdog interrupt enable
Bit 3 - Regular data overrun interrupt enable
Bit 2 - Injected data overrun interrupt enable
Bit 1 - Regular end of conversion interrupt enable
Bit 0 - Injected end of conversion interrupt enable
impl W<u32, Reg<u32, _DFSDM1_CR2>>
Bits 16:23 - Analog watchdog channel selection
Bits 8:15 - Extremes detector channel selection
Bit 6 - Clock absence interrupt enable
Bit 5 - Short-circuit detector interrupt enable
Bit 4 - Analog watchdog interrupt enable
Bit 3 - Regular data overrun interrupt enable
Bit 2 - Injected data overrun interrupt enable
Bit 1 - Regular end of conversion interrupt enable
Bit 0 - Injected end of conversion interrupt enable
impl W<u32, Reg<u32, _DFSDM2_CR2>>
Bits 16:23 - Analog watchdog channel selection
Bits 8:15 - Extremes detector channel selection
Bit 6 - Clock absence interrupt enable
Bit 5 - Short-circuit detector interrupt enable
Bit 4 - Analog watchdog interrupt enable
Bit 3 - Regular data overrun interrupt enable
Bit 2 - Injected data overrun interrupt enable
Bit 1 - Regular end of conversion interrupt enable
Bit 0 - Injected end of conversion interrupt enable
impl W<u32, Reg<u32, _DFSDM3_CR2>>
Bits 16:23 - Analog watchdog channel selection
Bits 8:15 - Extremes detector channel selection
Bit 6 - Clock absence interrupt enable
Bit 5 - Short-circuit detector interrupt enable
Bit 4 - Analog watchdog interrupt enable
Bit 3 - Regular data overrun interrupt enable
Bit 2 - Injected data overrun interrupt enable
Bit 1 - Regular end of conversion interrupt enable
Bit 0 - Injected end of conversion interrupt enable
impl W<u32, Reg<u32, _CR>>
Bits 24:31 - Clock prescaler
Bit 23 - Polling match mode
Bit 22 - Automatic poll mode stop
Bit 20 - TimeOut interrupt enable
Bit 19 - Status match interrupt enable
Bit 18 - FIFO threshold interrupt enable
Bit 17 - Transfer complete interrupt enable
Bit 16 - Transfer error interrupt enable
Bits 8:12 - IFO threshold level
Bit 7 - FLASH memory selection
Bit 3 - Timeout counter enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _DCR>>
Bits 16:20 - FLASH memory size
Bits 8:10 - Chip select high time
impl W<u32, Reg<u32, _FCR>>
Bit 4 - Clear timeout flag
Bit 3 - Clear status match flag
Bit 1 - Clear transfer complete flag
Bit 0 - Clear transfer error flag
impl W<u32, Reg<u32, _DLR>>
pub fn dl(&mut self) -> DL_W<'_>
impl W<u32, Reg<u32, _CCR>>
Bit 31 - Double data rate mode
Bit 30 - DDR hold half cycle
Bit 28 - Send instruction only once mode
Bits 26:27 - Functional mode
Bits 18:22 - Number of dummy cycles
Bits 16:17 - Alternate bytes size
Bits 14:15 - Alternate bytes mode
Bits 12:13 - Address size
Bits 10:11 - Address mode
Bits 8:9 - Instruction mode
impl W<u32, Reg<u32, _AR>>
impl W<u32, Reg<u32, _ABR>>
impl W<u32, Reg<u32, _DR>>
impl W<u32, Reg<u32, _PSMKR>>
impl W<u32, Reg<u32, _PSMAR>>
impl W<u32, Reg<u32, _PIR>>
Bits 0:15 - Polling interval
impl W<u32, Reg<u32, _LPTR>>
Bits 0:15 - Timeout period
impl W<u32, Reg<u32, _CR>>
Bit 2 - Debug Standby mode
Bit 5 - Trace pin assignment control
Bits 6:7 - Trace pin assignment control
impl W<u32, Reg<u32, _APB1FZR1>>
Bit 0 - TIM2 counter stopped when core is halted
Bit 4 - TIM6 counter stopped when core is halted
Bit 5 - TIM7 counter stopped when core is halted
Bit 10 - RTC counter stopped when core is halted
Bit 11 - Window watchdog counter stopped when core is halted
Bit 12 - Independent watchdog counter stopped when core is halted
Bit 21 - I2C1 SMBUS timeout counter stopped when core is halted
Bit 22 - I2C2 SMBUS timeout counter stopped when core is halted
Bit 23 - I2C3 SMBUS timeout counter stopped when core is halted
Bit 25 - bxCAN stopped when core is halted
Bit 31 - LPTIM1 counter stopped when core is halted
impl W<u32, Reg<u32, _APB1FZR2>>
Bit 5 - LPTIM2 counter stopped when core is halted
impl W<u32, Reg<u32, _APB2FZR>>
Bit 11 - TIM1 counter stopped when core is halted
Bit 16 - TIM15 counter stopped when core is halted
Bit 17 - TIM16 counter stopped when core is halted
impl W<u32, Reg<u32, _FPCCR>>
impl W<u32, Reg<u32, _FPCAR>>
Bits 3:31 - Location of unpopulated floating-point
impl W<u32, Reg<u32, _FPSCR>>
Bit 0 - Invalid operation cumulative exception bit
Bit 1 - Division by zero cumulative exception bit.
Bit 2 - Overflow cumulative exception bit
Bit 3 - Underflow cumulative exception bit
Bit 4 - Inexact cumulative exception bit
Bit 7 - Input denormal cumulative exception bit.
Bits 22:23 - Rounding Mode control field
pub fn fz(&mut self) -> FZ_W<'_>
Bit 24 - Flush-to-zero mode control bit:
pub fn dn(&mut self) -> DN_W<'_>
Bit 25 - Default NaN mode control bit
Bit 26 - Alternative half-precision control bit
pub fn v(&mut self) -> V_W<'_>
Bit 28 - Overflow condition code flag
pub fn c(&mut self) -> C_W<'_>
Bit 29 - Carry condition code flag
pub fn z(&mut self) -> Z_W<'_>
Bit 30 - Zero condition code flag
pub fn n(&mut self) -> N_W<'_>
Bit 31 - Negative condition code flag
impl W<u32, Reg<u32, _CTRL>>
Bit 1 - SysTick exception request enable
Bit 2 - Clock source selection
impl W<u32, Reg<u32, _LOAD>>
impl W<u32, Reg<u32, _VAL>>
Bits 0:23 - Current counter value
impl W<u32, Reg<u32, _CALIB>>
Bits 0:23 - Calibration value
Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
Bit 31 - NOREF flag. Reads as zero
impl W<u32, Reg<u32, _STIR>>
Bits 0:8 - Software generated interrupt ID
impl W<u32, Reg<u32, _CPACR>>
pub fn cp(&mut self) -> CP_W<'_>
impl W<u32, Reg<u32, _ACTRL>>
impl W<u32, Reg<u32, _CR1>>
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
impl W<u32, Reg<u32, _CR2>>
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 15 - Output compare 2 clear enable
Bits 12:14 - Output compare 2 mode
Bit 11 - Output compare 2 preload enable
Bit 10 - Output compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output compare 1 clear enable
Bits 4:6 - Output compare 1 mode
Bit 3 - Output compare 1 preload enable
Bit 2 - Output compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
Bit 15 - Capture/Compare 4 output Polarity
Bit 13 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 9 - Capture/Compare 3 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 16:31 - High counter value (TIM2 only)
Bits 0:15 - Counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 16:31 - High Auto-reload value (TIM2 only)
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _CCR>>
Bits 16:31 - High Capture/Compare 1 value (TIM2 only)
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR>>
Bits 0:2 - Timer2 ETR remap
Bits 3:4 - Internal trigger
impl W<u32, Reg<u32, _CCR>>
Bit 24 - CH18 selection (Vbat)
Bit 23 - CH17 selection (temperature)
Bits 18:21 - ADC prescaler
Bits 16:17 - ADC clock mode
Bits 14:15 - Direct memory access mode for dual ADC mode
Bit 13 - DMA configuration (for dual ADC mode)
Bits 8:11 - Delay between 2 sampling phases
Bits 0:4 - Dual ADC mode selection
impl W<u32, Reg<u32, _CR>>
Bit 0 - DAC channel1 enable
Bit 2 - DAC channel1 trigger enable
Bits 3:5 - DAC channel1 trigger selection
Bits 6:7 - DAC channel1 noise/triangle wave generation enable
Bits 8:11 - DAC channel1 mask/amplitude selector
Bit 12 - DAC channel1 DMA enable
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
Bit 14 - DAC Channel 1 calibration enable
Bit 16 - DAC channel2 enable
Bit 18 - DAC channel2 trigger enable
Bits 19:21 - DAC channel2 trigger selection
Bits 22:23 - DAC channel2 noise/triangle wave generation enable
Bits 24:27 - DAC channel2 mask/amplitude selector
Bit 28 - DAC channel2 DMA enable
Bit 29 - DAC channel2 DMA underrun interrupt enable
Bit 30 - DAC Channel 2 calibration enable
impl W<u32, Reg<u32, _SWTRIGR>>
Bit 0 - DAC channel1 software trigger
Bit 1 - DAC channel2 software trigger
impl W<u32, Reg<u32, _DHR12R1>>
Bits 0:11 - DAC channel1 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12L1>>
Bits 4:15 - DAC channel1 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8R1>>
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl W<u32, Reg<u32, _DHR12R2>>
Bits 0:11 - DAC channel2 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12L2>>
Bits 4:15 - DAC channel2 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8R2>>
Bits 0:7 - DAC channel2 8-bit right-aligned data
impl W<u32, Reg<u32, _DHR12RD>>
Bits 0:11 - DAC channel1 12-bit right-aligned data
Bits 16:27 - DAC channel2 12-bit right-aligned data
impl W<u32, Reg<u32, _DHR12LD>>
Bits 4:15 - DAC channel1 12-bit left-aligned data
Bits 20:31 - DAC channel2 12-bit left-aligned data
impl W<u32, Reg<u32, _DHR8RD>>
Bits 0:7 - DAC channel1 8-bit right-aligned data
Bits 8:15 - DAC channel2 8-bit right-aligned data
impl W<u32, Reg<u32, _SR>>
Bit 13 - DAC channel1 DMA underrun flag
Bit 29 - DAC channel2 DMA underrun flag
impl W<u32, Reg<u32, _CCR>>
Bits 0:4 - DAC Channel 1 offset trimming value
Bits 16:20 - DAC Channel 2 offset trimming value
impl W<u32, Reg<u32, _MCR>>
Bits 0:2 - DAC Channel 1 mode
Bits 16:18 - DAC Channel 2 mode
impl W<u32, Reg<u32, _SHSR1>>
Bits 0:9 - DAC Channel 1 sample Time
impl W<u32, Reg<u32, _SHSR2>>
Bits 0:9 - DAC Channel 2 sample Time
impl W<u32, Reg<u32, _SHHR>>
Bits 0:9 - DAC Channel 1 hold Time
Bits 16:25 - DAC Channel 2 hold time
impl W<u32, Reg<u32, _SHRR>>
Bits 0:7 - DAC Channel 1 refresh Time
Bits 16:23 - DAC Channel 2 refresh Time
impl W<u32, Reg<u32, _IFCR>>
Bit 27 - Channel x transfer error clear (x = 1 ..7)
Bit 26 - Channel x half transfer clear (x = 1 ..7)
Bit 25 - Channel x transfer complete clear (x = 1 ..7)
Bit 24 - Channel x global interrupt clear (x = 1 ..7)
Bit 23 - Channel x transfer error clear (x = 1 ..7)
Bit 22 - Channel x half transfer clear (x = 1 ..7)
Bit 21 - Channel x transfer complete clear (x = 1 ..7)
Bit 20 - Channel x global interrupt clear (x = 1 ..7)
Bit 19 - Channel x transfer error clear (x = 1 ..7)
Bit 18 - Channel x half transfer clear (x = 1 ..7)
Bit 17 - Channel x transfer complete clear (x = 1 ..7)
Bit 16 - Channel x global interrupt clear (x = 1 ..7)
Bit 15 - Channel x transfer error clear (x = 1 ..7)
Bit 14 - Channel x half transfer clear (x = 1 ..7)
Bit 13 - Channel x transfer complete clear (x = 1 ..7)
Bit 12 - Channel x global interrupt clear (x = 1 ..7)
Bit 11 - Channel x transfer error clear (x = 1 ..7)
Bit 10 - Channel x half transfer clear (x = 1 ..7)
Bit 9 - Channel x transfer complete clear (x = 1 ..7)
Bit 8 - Channel x global interrupt clear (x = 1 ..7)
Bit 7 - Channel x transfer error clear (x = 1 ..7)
Bit 6 - Channel x half transfer clear (x = 1 ..7)
Bit 5 - Channel x transfer complete clear (x = 1 ..7)
Bit 4 - Channel x global interrupt clear (x = 1 ..7)
Bit 3 - Channel x transfer error clear (x = 1 ..7)
Bit 2 - Channel x half transfer clear (x = 1 ..7)
Bit 1 - Channel x transfer complete clear (x = 1 ..7)
Bit 0 - Channel x global interrupt clear (x = 1 ..7)
impl W<u32, Reg<u32, _CCR1>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR1>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR1>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR1>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR2>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR2>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR2>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR2>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR3>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR3>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR3>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR3>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR4>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR4>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR4>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR4>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR5>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR5>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR5>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR5>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR6>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR6>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR6>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR6>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CCR7>>
Bit 14 - Memory to memory mode
pub fn pl(&mut self) -> PL_W<'_>
Bits 12:13 - Channel priority level
Bits 8:9 - Peripheral size
Bit 7 - Memory increment mode
Bit 6 - Peripheral increment mode
Bit 4 - Data transfer direction
Bit 3 - Transfer error interrupt enable
Bit 2 - Half transfer interrupt enable
Bit 1 - Transfer complete interrupt enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _CNDTR7>>
Bits 0:15 - Number of data to transfer
impl W<u32, Reg<u32, _CPAR7>>
pub fn pa(&mut self) -> PA_W<'_>
Bits 0:31 - Peripheral address
impl W<u32, Reg<u32, _CMAR7>>
pub fn ma(&mut self) -> MA_W<'_>
Bits 0:31 - Memory address
impl W<u32, Reg<u32, _CSELR>>
Bits 24:27 - DMA channel 7 selection
Bits 20:23 - DMA channel 6 selection
Bits 16:19 - DMA channel 5 selection
Bits 12:15 - DMA channel 4 selection
Bits 8:11 - DMA channel 3 selection
Bits 4:7 - DMA channel 2 selection
Bits 0:3 - DMA channel 1 selection
impl W<u32, Reg<u32, _DR>>
pub fn dr(&mut self) -> DR_W<'_>
Bits 0:31 - Data register bits
impl W<u32, Reg<u32, _IDR>>
Bits 0:7 - General-purpose 8-bit data register bits
impl W<u32, Reg<u32, _CR>>
Bit 7 - Reverse output data
Bits 5:6 - Reverse input data
Bits 3:4 - Polynomial size
impl W<u32, Reg<u32, _INIT>>
Bits 0:31 - Programmable initial CRC value
impl W<u32, Reg<u32, _POL>>
Bits 0:31 - Programmable polynomial
impl W<u8, Reg<u8, _DR8>>
Bits 0:7 - Data register bits
impl W<u16, Reg<u16, _DR16>>
Bits 0:15 - Data register bits
impl W<u32, Reg<u32, _CR>>
Bits 2:4 - Duty selection
Bit 1 - Voltage source selection
Bit 0 - LCD controller enable
Bit 7 - Mux segment enable
Bit 8 - Voltage output buffer enable
impl W<u32, Reg<u32, _FCR>>
pub fn ps(&mut self) -> PS_W<'_>
Bits 22:25 - PS 16-bit prescaler
Bits 18:21 - DIV clock divider
Bits 16:17 - Blink mode selection
Bits 13:15 - Blink frequency selection
pub fn cc(&mut self) -> CC_W<'_>
Bits 10:12 - Contrast control
Bits 7:9 - Dead time duration
Bits 4:6 - Pulse ON duration
Bit 3 - Update display done interrupt enable
Bit 1 - Start of frame interrupt enable
pub fn hd(&mut self) -> HD_W<'_>
Bit 0 - High drive enable
impl W<u32, Reg<u32, _SR>>
Bit 2 - Update display request
impl W<u32, Reg<u32, _CLR>>
Bit 3 - Update display done clear
Bit 1 - Start of frame flag clear
impl W<u32, Reg<u32, _RAM_COM0>>
impl W<u32, Reg<u32, _RAM_COM1>>
impl W<u32, Reg<u32, _RAM_COM2>>
impl W<u32, Reg<u32, _RAM_COM3>>
impl W<u32, Reg<u32, _RAM_COM4>>
impl W<u32, Reg<u32, _RAM_COM5>>
impl W<u32, Reg<u32, _RAM_COM6>>
impl W<u32, Reg<u32, _RAM_COM7>>
impl W<u32, Reg<u32, _CR>>
Bits 28:31 - Charge transfer pulse high
Bits 24:27 - Charge transfer pulse low
Bits 17:23 - Spread spectrum deviation
Bit 16 - Spread spectrum enable
Bit 15 - Spread spectrum prescaler
Bits 12:14 - pulse generator prescaler
Bits 5:7 - Max count value
Bit 3 - Synchronization pin polarity
pub fn am(&mut self) -> AM_W<'_>
Bit 1 - Start a new acquisition
Bit 0 - Touch sensing controller enable
impl W<u32, Reg<u32, _IER>>
Bit 1 - Max count error interrupt enable
Bit 0 - End of acquisition interrupt enable
impl W<u32, Reg<u32, _ICR>>
Bit 1 - Max count error interrupt clear
Bit 0 - End of acquisition interrupt clear
impl W<u32, Reg<u32, _ISR>>
Bit 1 - Max count error flag
Bit 0 - End of acquisition flag
impl W<u32, Reg<u32, _IOHCR>>
impl W<u32, Reg<u32, _IOASCR>>
impl W<u32, Reg<u32, _IOSCR>>
impl W<u32, Reg<u32, _IOCCR>>
impl W<u32, Reg<u32, _IOGCSR>>
Bit 7 - Analog I/O group x enable
Bit 6 - Analog I/O group x enable
Bit 5 - Analog I/O group x enable
Bit 4 - Analog I/O group x enable
Bit 3 - Analog I/O group x enable
Bit 2 - Analog I/O group x enable
Bit 1 - Analog I/O group x enable
Bit 0 - Analog I/O group x enable
impl W<u32, Reg<u32, _KR>>
Bits 0:15 - Key value (write only, read 0x0000)
impl W<u32, Reg<u32, _PR>>
pub fn pr(&mut self) -> PR_W<'_>
Bits 0:2 - Prescaler divider
impl W<u32, Reg<u32, _RLR>>
pub fn rl(&mut self) -> RL_W<'_>
Bits 0:11 - Watchdog counter reload value
impl W<u32, Reg<u32, _WINR>>
Bits 0:11 - Watchdog counter window value
impl W<u32, Reg<u32, _CR>>
pub fn t(&mut self) -> T_W<'_>
Bits 0:6 - 7-bit counter (MSB to LSB)
impl W<u32, Reg<u32, _CFR>>
Bit 9 - Early wakeup interrupt
pub fn w(&mut self) -> W_W<'_>
Bits 0:6 - 7-bit window value
impl W<u32, Reg<u32, _SR>>
Bit 0 - Early wakeup interrupt flag
impl W<u32, Reg<u32, _COMP1_CSR>>
Bit 0 - Comparator 1 enable bit
Bits 2:3 - Power Mode of the comparator 1
Bits 4:6 - Comparator 1 Input Minus connection configuration bit
Bit 7 - Comparator1 input plus selection bit
Bit 15 - Comparator 1 polarity selection bit
Bits 16:17 - Comparator 1 hysteresis selection bits
Bits 18:20 - Comparator 1 blanking source selection bits
Bit 22 - Scaler bridge enable
Bit 23 - Voltage scaler enable bit
Bit 31 - COMP1_CSR register lock bit
impl W<u32, Reg<u32, _COMP2_CSR>>
Bit 0 - Comparator 2 enable bit
Bits 2:3 - Power Mode of the comparator 2
Bits 4:6 - Comparator 2 Input Minus connection configuration bit
Bit 7 - Comparator 2 Input Plus connection configuration bit
Bit 9 - Windows mode selection bit
Bit 15 - Comparator 2 polarity selection bit
Bits 16:17 - Comparator 2 hysteresis selection bits
Bits 18:20 - Comparator 2 blanking source selection bits
Bit 22 - Scaler bridge enable
Bit 23 - Voltage scaler enable bit
Bit 31 - COMP2_CSR register lock bit
impl W<u32, Reg<u32, _CSSA>>
Bits 8:23 - code segment start address
impl W<u32, Reg<u32, _CSL>>
Bits 8:21 - code segment length
impl W<u32, Reg<u32, _NVDSSA>>
Bits 8:23 - Non-volatile data segment start address
impl W<u32, Reg<u32, _NVDSL>>
Bits 8:21 - Non-volatile data segment length
impl W<u32, Reg<u32, _VDSSA>>
Bits 6:15 - Volatile data segment start address
impl W<u32, Reg<u32, _VDSL>>
Bits 6:15 - Non-volatile data segment length
impl W<u32, Reg<u32, _CR>>
Bit 2 - Volatile data execution
Bit 1 - Volatile data shared
Bit 0 - Firewall pre alarm
impl W<u32, Reg<u32, _CR1>>
pub fn pe(&mut self) -> PE_W<'_>
Bit 0 - Peripheral enable
Bit 1 - TX Interrupt enable
Bit 2 - RX Interrupt enable
Bit 3 - Address match interrupt enable (slave only)
Bit 4 - Not acknowledge received interrupt enable
Bit 5 - STOP detection Interrupt enable
Bit 6 - Transfer Complete interrupt enable
Bit 7 - Error interrupts enable
Bits 8:11 - Digital noise filter
Bit 12 - Analog noise filter OFF
Bit 14 - DMA transmission requests enable
Bit 15 - DMA reception requests enable
Bit 16 - Slave byte control
Bit 17 - Clock stretching disable
Bit 18 - Wakeup from STOP enable
Bit 19 - General call enable
Bit 20 - SMBus Host address enable
Bit 21 - SMBus Device Default address enable
Bit 22 - SMBUS alert enable
impl W<u32, Reg<u32, _CR2>>
Bit 26 - Packet error checking byte
Bit 25 - Automatic end mode (master mode)
Bit 24 - NBYTES reload mode
Bits 16:23 - Number of bytes
Bit 15 - NACK generation (slave mode)
Bit 14 - Stop generation (master mode)
Bit 13 - Start generation
Bit 12 - 10-bit address header only read direction (master receiver mode)
Bit 11 - 10-bit addressing mode (master mode)
Bit 10 - Transfer direction (master mode)
Bits 0:9 - Slave address bit (master mode)
impl W<u32, Reg<u32, _OAR1>>
Bits 0:9 - Interface address
Bit 10 - Own Address 1 10-bit mode
Bit 15 - Own Address 1 enable
impl W<u32, Reg<u32, _OAR2>>
Bits 1:7 - Interface address
Bits 8:10 - Own Address 2 masks
Bit 15 - Own Address 2 enable
impl W<u32, Reg<u32, _TIMINGR>>
Bits 0:7 - SCL low period (master mode)
Bits 8:15 - SCL high period (master mode)
Bits 16:19 - Data hold time
Bits 20:23 - Data setup time
Bits 28:31 - Timing prescaler
impl W<u32, Reg<u32, _TIMEOUTR>>
Bits 0:11 - Bus timeout A
Bit 12 - Idle clock timeout detection
Bit 15 - Clock timeout enable
Bits 16:27 - Bus timeout B
pub fn texten(&mut self) -> TEXTEN_W<'_>
Bit 31 - Extended clock timeout enable
impl W<u32, Reg<u32, _ISR>>
Bit 1 - Transmit interrupt status (transmitters)
Bit 0 - Transmit data register empty (transmitters)
impl W<u32, Reg<u32, _ICR>>
Bit 13 - Alert flag clear
Bit 12 - Timeout detection flag clear
Bit 11 - PEC Error flag clear
Bit 10 - Overrun/Underrun flag clear
Bit 9 - Arbitration lost flag clear
Bit 8 - Bus error flag clear
Bit 5 - Stop detection flag clear
Bit 4 - Not Acknowledge flag clear
Bit 3 - Address Matched flag clear
impl W<u32, Reg<u32, _TXDR>>
Bits 0:7 - 8-bit transmit data
impl W<u32, Reg<u32, _ACR>>
Bit 9 - Instruction cache enable
Bit 10 - Data cache enable
Bit 11 - Instruction cache reset
Bit 12 - Data cache reset
Bit 13 - Flash Power-down mode during Low-power run mode
Bit 14 - Flash Power-down mode during Low-power sleep mode
impl W<u32, Reg<u32, _PDKEYR>>
Bits 0:31 - RUN_PD in FLASH_ACR key
impl W<u32, Reg<u32, _KEYR>>
impl W<u32, Reg<u32, _OPTKEYR>>
Bits 0:31 - Option byte key
impl W<u32, Reg<u32, _SR>>
Bit 3 - Programming error
Bit 4 - Write protected error
Bit 5 - Programming alignment error
Bit 7 - Programming sequence error
Bit 8 - Fast programming data miss error
Bit 9 - Fast programming error
Bit 14 - PCROP read error
Bit 15 - Option validity error
impl W<u32, Reg<u32, _CR>>
pub fn pg(&mut self) -> PG_W<'_>
Bit 2 - Bank 1 Mass erase
Bit 15 - Bank 2 Mass erase
Bit 17 - Options modification start
Bit 18 - Fast programming
Bit 24 - End of operation interrupt enable
Bit 25 - Error interrupt enable
Bit 26 - PCROP read error interrupt enable
Bit 27 - Force the option byte loading
impl W<u32, Reg<u32, _ECCR>>
Bit 24 - ECC correction interrupt enable
impl W<u32, Reg<u32, _OPTR>>
Bits 0:7 - Read protection level
Bits 8:10 - BOR reset Level
Bit 16 - Independent watchdog selection
Bit 17 - Independent watchdog counter freeze in Stop mode
Bit 18 - Independent watchdog counter freeze in Standby mode
Bit 19 - Window watchdog selection
Bit 21 - Dual-Bank on 512 KB or 256 KB Flash memory devices
Bit 23 - Boot configuration
Bit 24 - SRAM2 parity check enable
Bit 25 - SRAM2 Erase when system reset
Bit 27 - nBOOT0 option bit
impl W<u32, Reg<u32, _PCROP1SR>>
Bits 0:15 - Bank 1 PCROP area start offset
impl W<u32, Reg<u32, _PCROP1ER>>
Bits 0:15 - Bank 1 PCROP area end offset
Bit 31 - PCROP area preserved when RDP level decreased
impl W<u32, Reg<u32, _WRP1AR>>
Bits 0:7 - Bank 1 WRP first area start offset
Bits 16:23 - Bank 1 WRP first area A end offset
impl W<u32, Reg<u32, _WRP1BR>>
Bits 16:23 - Bank 1 WRP second area B end offset
Bits 0:7 - Bank 1 WRP second area B start offset
impl W<u32, Reg<u32, _PCROP2SR>>
Bits 0:15 - Bank 2 PCROP area start offset
impl W<u32, Reg<u32, _PCROP2ER>>
Bits 0:15 - Bank 2 PCROP area end offset
impl W<u32, Reg<u32, _WRP2AR>>
Bits 0:7 - Bank 2 WRP first area A start offset
Bits 16:23 - Bank 2 WRP first area A end offset
impl W<u32, Reg<u32, _WRP2BR>>
Bits 0:7 - Bank 2 WRP second area B start offset
Bits 16:23 - Bank 2 WRP second area B end offset
impl W<u32, Reg<u32, _CR1>>
Bits 9:10 - Voltage scaling range selection
Bit 8 - Disable backup domain write protection
Bits 0:2 - Low-power mode selection
impl W<u32, Reg<u32, _CR2>>
Bit 10 - VDDUSB USB supply valid
Bit 9 - VDDIO2 Independent I/Os supply valid
Bit 7 - Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V
Bit 6 - Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V
Bit 5 - Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V
Bit 4 - Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V
Bits 1:3 - Power voltage detector level selection
Bit 0 - Power voltage detector enable
impl W<u32, Reg<u32, _CR3>>
Bit 15 - Enable internal wakeup line
Bit 10 - Apply pull-up and pull-down configuration
Bit 8 - SRAM2 retention in Standby mode
Bit 4 - Enable Wakeup pin WKUP5
Bit 3 - Enable Wakeup pin WKUP4
Bit 2 - Enable Wakeup pin WKUP3
Bit 1 - Enable Wakeup pin WKUP2
Bit 0 - Enable Wakeup pin WKUP1
impl W<u32, Reg<u32, _CR4>>
Bit 9 - VBAT battery charging resistor selection
Bit 8 - VBAT battery charging enable
Bit 4 - Wakeup pin WKUP5 polarity
Bit 3 - Wakeup pin WKUP4 polarity
Bit 2 - Wakeup pin WKUP3 polarity
Bit 1 - Wakeup pin WKUP2 polarity
Bit 0 - Wakeup pin WKUP1 polarity
impl W<u32, Reg<u32, _SCR>>
Bit 8 - Clear standby flag
Bit 4 - Clear wakeup flag 5
Bit 3 - Clear wakeup flag 4
Bit 2 - Clear wakeup flag 3
Bit 1 - Clear wakeup flag 2
Bit 0 - Clear wakeup flag 1
impl W<u32, Reg<u32, _PUCRA>>
Bit 15 - Port A pull-up bit y (y=0..15)
Bit 14 - Port A pull-up bit y (y=0..15)
Bit 13 - Port A pull-up bit y (y=0..15)
Bit 12 - Port A pull-up bit y (y=0..15)
Bit 11 - Port A pull-up bit y (y=0..15)
Bit 10 - Port A pull-up bit y (y=0..15)
Bit 9 - Port A pull-up bit y (y=0..15)
Bit 8 - Port A pull-up bit y (y=0..15)
Bit 7 - Port A pull-up bit y (y=0..15)
Bit 6 - Port A pull-up bit y (y=0..15)
Bit 5 - Port A pull-up bit y (y=0..15)
Bit 4 - Port A pull-up bit y (y=0..15)
Bit 3 - Port A pull-up bit y (y=0..15)
Bit 2 - Port A pull-up bit y (y=0..15)
Bit 1 - Port A pull-up bit y (y=0..15)
Bit 0 - Port A pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRA>>
Bit 15 - Port A pull-down bit y (y=0..15)
Bit 14 - Port A pull-down bit y (y=0..15)
Bit 13 - Port A pull-down bit y (y=0..15)
Bit 12 - Port A pull-down bit y (y=0..15)
Bit 11 - Port A pull-down bit y (y=0..15)
Bit 10 - Port A pull-down bit y (y=0..15)
Bit 9 - Port A pull-down bit y (y=0..15)
Bit 8 - Port A pull-down bit y (y=0..15)
Bit 7 - Port A pull-down bit y (y=0..15)
Bit 6 - Port A pull-down bit y (y=0..15)
Bit 5 - Port A pull-down bit y (y=0..15)
Bit 4 - Port A pull-down bit y (y=0..15)
Bit 3 - Port A pull-down bit y (y=0..15)
Bit 2 - Port A pull-down bit y (y=0..15)
Bit 1 - Port A pull-down bit y (y=0..15)
Bit 0 - Port A pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRB>>
Bit 15 - Port B pull-up bit y (y=0..15)
Bit 14 - Port B pull-up bit y (y=0..15)
Bit 13 - Port B pull-up bit y (y=0..15)
Bit 12 - Port B pull-up bit y (y=0..15)
Bit 11 - Port B pull-up bit y (y=0..15)
Bit 10 - Port B pull-up bit y (y=0..15)
Bit 9 - Port B pull-up bit y (y=0..15)
Bit 8 - Port B pull-up bit y (y=0..15)
Bit 7 - Port B pull-up bit y (y=0..15)
Bit 6 - Port B pull-up bit y (y=0..15)
Bit 5 - Port B pull-up bit y (y=0..15)
Bit 4 - Port B pull-up bit y (y=0..15)
Bit 3 - Port B pull-up bit y (y=0..15)
Bit 2 - Port B pull-up bit y (y=0..15)
Bit 1 - Port B pull-up bit y (y=0..15)
Bit 0 - Port B pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRB>>
Bit 15 - Port B pull-down bit y (y=0..15)
Bit 14 - Port B pull-down bit y (y=0..15)
Bit 13 - Port B pull-down bit y (y=0..15)
Bit 12 - Port B pull-down bit y (y=0..15)
Bit 11 - Port B pull-down bit y (y=0..15)
Bit 10 - Port B pull-down bit y (y=0..15)
Bit 9 - Port B pull-down bit y (y=0..15)
Bit 8 - Port B pull-down bit y (y=0..15)
Bit 7 - Port B pull-down bit y (y=0..15)
Bit 6 - Port B pull-down bit y (y=0..15)
Bit 5 - Port B pull-down bit y (y=0..15)
Bit 4 - Port B pull-down bit y (y=0..15)
Bit 3 - Port B pull-down bit y (y=0..15)
Bit 2 - Port B pull-down bit y (y=0..15)
Bit 1 - Port B pull-down bit y (y=0..15)
Bit 0 - Port B pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRC>>
Bit 15 - Port C pull-up bit y (y=0..15)
Bit 14 - Port C pull-up bit y (y=0..15)
Bit 13 - Port C pull-up bit y (y=0..15)
Bit 12 - Port C pull-up bit y (y=0..15)
Bit 11 - Port C pull-up bit y (y=0..15)
Bit 10 - Port C pull-up bit y (y=0..15)
Bit 9 - Port C pull-up bit y (y=0..15)
Bit 8 - Port C pull-up bit y (y=0..15)
Bit 7 - Port C pull-up bit y (y=0..15)
Bit 6 - Port C pull-up bit y (y=0..15)
Bit 5 - Port C pull-up bit y (y=0..15)
Bit 4 - Port C pull-up bit y (y=0..15)
Bit 3 - Port C pull-up bit y (y=0..15)
Bit 2 - Port C pull-up bit y (y=0..15)
Bit 1 - Port C pull-up bit y (y=0..15)
Bit 0 - Port C pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRC>>
Bit 15 - Port C pull-down bit y (y=0..15)
Bit 14 - Port C pull-down bit y (y=0..15)
Bit 13 - Port C pull-down bit y (y=0..15)
Bit 12 - Port C pull-down bit y (y=0..15)
Bit 11 - Port C pull-down bit y (y=0..15)
Bit 10 - Port C pull-down bit y (y=0..15)
Bit 9 - Port C pull-down bit y (y=0..15)
Bit 8 - Port C pull-down bit y (y=0..15)
Bit 7 - Port C pull-down bit y (y=0..15)
Bit 6 - Port C pull-down bit y (y=0..15)
Bit 5 - Port C pull-down bit y (y=0..15)
Bit 4 - Port C pull-down bit y (y=0..15)
Bit 3 - Port C pull-down bit y (y=0..15)
Bit 2 - Port C pull-down bit y (y=0..15)
Bit 1 - Port C pull-down bit y (y=0..15)
Bit 0 - Port C pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRD>>
Bit 15 - Port D pull-up bit y (y=0..15)
Bit 14 - Port D pull-up bit y (y=0..15)
Bit 13 - Port D pull-up bit y (y=0..15)
Bit 12 - Port D pull-up bit y (y=0..15)
Bit 11 - Port D pull-up bit y (y=0..15)
Bit 10 - Port D pull-up bit y (y=0..15)
Bit 9 - Port D pull-up bit y (y=0..15)
Bit 8 - Port D pull-up bit y (y=0..15)
Bit 7 - Port D pull-up bit y (y=0..15)
Bit 6 - Port D pull-up bit y (y=0..15)
Bit 5 - Port D pull-up bit y (y=0..15)
Bit 4 - Port D pull-up bit y (y=0..15)
Bit 3 - Port D pull-up bit y (y=0..15)
Bit 2 - Port D pull-up bit y (y=0..15)
Bit 1 - Port D pull-up bit y (y=0..15)
Bit 0 - Port D pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRD>>
Bit 15 - Port D pull-down bit y (y=0..15)
Bit 14 - Port D pull-down bit y (y=0..15)
Bit 13 - Port D pull-down bit y (y=0..15)
Bit 12 - Port D pull-down bit y (y=0..15)
Bit 11 - Port D pull-down bit y (y=0..15)
Bit 10 - Port D pull-down bit y (y=0..15)
Bit 9 - Port D pull-down bit y (y=0..15)
Bit 8 - Port D pull-down bit y (y=0..15)
Bit 7 - Port D pull-down bit y (y=0..15)
Bit 6 - Port D pull-down bit y (y=0..15)
Bit 5 - Port D pull-down bit y (y=0..15)
Bit 4 - Port D pull-down bit y (y=0..15)
Bit 3 - Port D pull-down bit y (y=0..15)
Bit 2 - Port D pull-down bit y (y=0..15)
Bit 1 - Port D pull-down bit y (y=0..15)
Bit 0 - Port D pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRE>>
Bit 15 - Port E pull-up bit y (y=0..15)
Bit 14 - Port E pull-up bit y (y=0..15)
Bit 13 - Port E pull-up bit y (y=0..15)
Bit 12 - Port E pull-up bit y (y=0..15)
Bit 11 - Port E pull-up bit y (y=0..15)
Bit 10 - Port E pull-up bit y (y=0..15)
Bit 9 - Port E pull-up bit y (y=0..15)
Bit 8 - Port E pull-up bit y (y=0..15)
Bit 7 - Port E pull-up bit y (y=0..15)
Bit 6 - Port E pull-up bit y (y=0..15)
Bit 5 - Port E pull-up bit y (y=0..15)
Bit 4 - Port E pull-up bit y (y=0..15)
Bit 3 - Port E pull-up bit y (y=0..15)
Bit 2 - Port E pull-up bit y (y=0..15)
Bit 1 - Port E pull-up bit y (y=0..15)
Bit 0 - Port E pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRE>>
Bit 15 - Port E pull-down bit y (y=0..15)
Bit 14 - Port E pull-down bit y (y=0..15)
Bit 13 - Port E pull-down bit y (y=0..15)
Bit 12 - Port E pull-down bit y (y=0..15)
Bit 11 - Port E pull-down bit y (y=0..15)
Bit 10 - Port E pull-down bit y (y=0..15)
Bit 9 - Port E pull-down bit y (y=0..15)
Bit 8 - Port E pull-down bit y (y=0..15)
Bit 7 - Port E pull-down bit y (y=0..15)
Bit 6 - Port E pull-down bit y (y=0..15)
Bit 5 - Port E pull-down bit y (y=0..15)
Bit 4 - Port E pull-down bit y (y=0..15)
Bit 3 - Port E pull-down bit y (y=0..15)
Bit 2 - Port E pull-down bit y (y=0..15)
Bit 1 - Port E pull-down bit y (y=0..15)
Bit 0 - Port E pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRF>>
Bit 15 - Port F pull-up bit y (y=0..15)
Bit 14 - Port F pull-up bit y (y=0..15)
Bit 13 - Port F pull-up bit y (y=0..15)
Bit 12 - Port F pull-up bit y (y=0..15)
Bit 11 - Port F pull-up bit y (y=0..15)
Bit 10 - Port F pull-up bit y (y=0..15)
Bit 9 - Port F pull-up bit y (y=0..15)
Bit 8 - Port F pull-up bit y (y=0..15)
Bit 7 - Port F pull-up bit y (y=0..15)
Bit 6 - Port F pull-up bit y (y=0..15)
Bit 5 - Port F pull-up bit y (y=0..15)
Bit 4 - Port F pull-up bit y (y=0..15)
Bit 3 - Port F pull-up bit y (y=0..15)
Bit 2 - Port F pull-up bit y (y=0..15)
Bit 1 - Port F pull-up bit y (y=0..15)
Bit 0 - Port F pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRF>>
Bit 15 - Port F pull-down bit y (y=0..15)
Bit 14 - Port F pull-down bit y (y=0..15)
Bit 13 - Port F pull-down bit y (y=0..15)
Bit 12 - Port F pull-down bit y (y=0..15)
Bit 11 - Port F pull-down bit y (y=0..15)
Bit 10 - Port F pull-down bit y (y=0..15)
Bit 9 - Port F pull-down bit y (y=0..15)
Bit 8 - Port F pull-down bit y (y=0..15)
Bit 7 - Port F pull-down bit y (y=0..15)
Bit 6 - Port F pull-down bit y (y=0..15)
Bit 5 - Port F pull-down bit y (y=0..15)
Bit 4 - Port F pull-down bit y (y=0..15)
Bit 3 - Port F pull-down bit y (y=0..15)
Bit 2 - Port F pull-down bit y (y=0..15)
Bit 1 - Port F pull-down bit y (y=0..15)
Bit 0 - Port F pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRG>>
Bit 15 - Port G pull-up bit y (y=0..15)
Bit 14 - Port G pull-up bit y (y=0..15)
Bit 13 - Port G pull-up bit y (y=0..15)
Bit 12 - Port G pull-up bit y (y=0..15)
Bit 11 - Port G pull-up bit y (y=0..15)
Bit 10 - Port G pull-up bit y (y=0..15)
Bit 9 - Port G pull-up bit y (y=0..15)
Bit 8 - Port G pull-up bit y (y=0..15)
Bit 7 - Port G pull-up bit y (y=0..15)
Bit 6 - Port G pull-up bit y (y=0..15)
Bit 5 - Port G pull-up bit y (y=0..15)
Bit 4 - Port G pull-up bit y (y=0..15)
Bit 3 - Port G pull-up bit y (y=0..15)
Bit 2 - Port G pull-up bit y (y=0..15)
Bit 1 - Port G pull-up bit y (y=0..15)
Bit 0 - Port G pull-up bit y (y=0..15)
impl W<u32, Reg<u32, _PDCRG>>
Bit 15 - Port G pull-down bit y (y=0..15)
Bit 14 - Port G pull-down bit y (y=0..15)
Bit 13 - Port G pull-down bit y (y=0..15)
Bit 12 - Port G pull-down bit y (y=0..15)
Bit 11 - Port G pull-down bit y (y=0..15)
Bit 10 - Port G pull-down bit y (y=0..15)
Bit 9 - Port G pull-down bit y (y=0..15)
Bit 8 - Port G pull-down bit y (y=0..15)
Bit 7 - Port G pull-down bit y (y=0..15)
Bit 6 - Port G pull-down bit y (y=0..15)
Bit 5 - Port G pull-down bit y (y=0..15)
Bit 4 - Port G pull-down bit y (y=0..15)
Bit 3 - Port G pull-down bit y (y=0..15)
Bit 2 - Port G pull-down bit y (y=0..15)
Bit 1 - Port G pull-down bit y (y=0..15)
Bit 0 - Port G pull-down bit y (y=0..15)
impl W<u32, Reg<u32, _PUCRH>>
Bit 1 - Port H pull-up bit y (y=0..1)
Bit 0 - Port H pull-up bit y (y=0..1)
impl W<u32, Reg<u32, _PDCRH>>
Bit 1 - Port H pull-down bit y (y=0..1)
Bit 0 - Port H pull-down bit y (y=0..1)
impl W<u32, Reg<u32, _MEMRMP>>
Bit 8 - Flash Bank mode selection
Bit 3 - QUADSPI memory mapping swap
Bits 0:2 - Memory mapping selection
impl W<u32, Reg<u32, _CFGR1>>
Bits 26:31 - Floating Point Unit interrupts enable bits
Bit 22 - I2C3 Fast-mode Plus driving capability activation
Bit 21 - I2C2 Fast-mode Plus driving capability activation
Bit 20 - I2C1 Fast-mode Plus driving capability activation
Bit 19 - Fast-mode Plus (Fm+) driving capability activation on PB9
Bit 18 - Fast-mode Plus (Fm+) driving capability activation on PB8
Bit 17 - Fast-mode Plus (Fm+) driving capability activation on PB7
Bit 16 - Fast-mode Plus (Fm+) driving capability activation on PB6
Bit 8 - I/O analog switch voltage booster enable
impl W<u32, Reg<u32, _EXTICR1>>
Bits 12:14 - EXTI 3 configuration bits
Bits 8:10 - EXTI 2 configuration bits
Bits 4:6 - EXTI 1 configuration bits
Bits 0:2 - EXTI 0 configuration bits
impl W<u32, Reg<u32, _EXTICR2>>
Bits 12:14 - EXTI 7 configuration bits
Bits 8:10 - EXTI 6 configuration bits
Bits 4:6 - EXTI 5 configuration bits
Bits 0:2 - EXTI 4 configuration bits
impl W<u32, Reg<u32, _EXTICR3>>
Bits 12:14 - EXTI 11 configuration bits
Bits 8:10 - EXTI 10 configuration bits
Bits 4:6 - EXTI 9 configuration bits
Bits 0:2 - EXTI 8 configuration bits
impl W<u32, Reg<u32, _EXTICR4>>
Bits 12:14 - EXTI15 configuration bits
Bits 8:10 - EXTI14 configuration bits
Bits 4:6 - EXTI13 configuration bits
Bits 0:2 - EXTI12 configuration bits
impl W<u32, Reg<u32, _SCSR>>
impl W<u32, Reg<u32, _CFGR2>>
Bit 8 - SRAM2 parity error flag
Bit 2 - PVD lock enable bit
Bit 1 - SRAM2 parity lock bit
Bit 0 - Cortex LOCKUP (Hardfault) output enable bit
impl W<u32, Reg<u32, _SWPR>>
Bit 31 - SRAM2 page 31 write protection
impl W<u32, Reg<u32, _SKR>>
Bits 0:7 - SRAM2 write protection key for software erase
impl W<u32, Reg<u32, _CR>>
pub fn ie(&mut self) -> IE_W<'_>
Bit 2 - Random number generator enable
impl W<u32, Reg<u32, _SR>>
Bit 6 - Seed error interrupt status
Bit 5 - Clock error interrupt status
impl W<u32, Reg<u32, _CR>>
Bit 12 - Enable DMA management of data output phase
pub fn dmainen(&mut self) -> DMAINEN_W<'_>
Bit 11 - Enable DMA management of data input phase
Bit 10 - Error interrupt enable
Bit 9 - CCF flag interrupt enable
Bit 7 - Computation Complete Flag Clear
Bits 5:6 - AES chaining mode
Bits 3:4 - AES operating mode
Bits 1:2 - Data type selection (for data in and data out to/from the cryptographic block)
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _DINR>>
Bits 0:31 - Data Input Register
impl W<u32, Reg<u32, _KEYR0>>
Bits 0:31 - Data Output Register (LSB key [31:0])
impl W<u32, Reg<u32, _KEYR1>>
Bits 0:31 - AES key register (key [63:32])
impl W<u32, Reg<u32, _KEYR2>>
Bits 0:31 - AES key register (key [95:64])
impl W<u32, Reg<u32, _KEYR3>>
Bits 0:31 - AES key register (MSB key [127:96])
impl W<u32, Reg<u32, _IVR0>>
Bits 0:31 - initialization vector register (LSB IVR [31:0])
impl W<u32, Reg<u32, _IVR1>>
Bits 0:31 - Initialization Vector Register (IVR [63:32])
impl W<u32, Reg<u32, _IVR2>>
Bits 0:31 - Initialization Vector Register (IVR [95:64])
impl W<u32, Reg<u32, _IVR3>>
Bits 0:31 - Initialization Vector Register (MSB IVR [127:96])
impl W<u32, Reg<u32, _ISR>>
impl W<u32, Reg<u32, _IER>>
impl W<u32, Reg<u32, _CR>>
impl W<u32, Reg<u32, _CFGR>>
impl W<u32, Reg<u32, _CFGR2>>
impl W<u32, Reg<u32, _SMPR1>>
Bits 27:29 - Channel 9 sampling time selection
Bits 24:26 - Channel 8 sampling time selection
Bits 21:23 - Channel 7 sampling time selection
Bits 18:20 - Channel 6 sampling time selection
Bits 15:17 - Channel 5 sampling time selection
Bits 12:14 - Channel 4 sampling time selection
Bits 9:11 - Channel 3 sampling time selection
Bits 6:8 - Channel 2 sampling time selection
Bits 3:5 - Channel 1 sampling time selection
Bits 0:2 - Channel 0 sampling time selection
impl W<u32, Reg<u32, _SMPR2>>
Bits 24:26 - Channel 18 sampling time selection
Bits 21:23 - Channel 17 sampling time selection
Bits 18:20 - Channel 16 sampling time selection
Bits 15:17 - Channel 15 sampling time selection
Bits 12:14 - Channel 14 sampling time selection
Bits 9:11 - Channel 13 sampling time selection
Bits 6:8 - Channel 12 sampling time selection
Bits 3:5 - Channel 11 sampling time selection
Bits 0:2 - Channel 10 sampling time selection
impl W<u32, Reg<u32, _TR1>>
impl W<u32, Reg<u32, _TR2>>
impl W<u32, Reg<u32, _TR3>>
impl W<u32, Reg<u32, _SQR1>>
pub fn l(&mut self) -> L_W<'_>
Bits 0:3 - Regular channel sequence length
impl W<u32, Reg<u32, _SQR2>>
impl W<u32, Reg<u32, _SQR3>>
impl W<u32, Reg<u32, _SQR4>>
impl W<u32, Reg<u32, _JSQR>>
pub fn jl(&mut self) -> JL_W<'_>
impl W<u32, Reg<u32, _OFR1>>
impl W<u32, Reg<u32, _OFR2>>
impl W<u32, Reg<u32, _OFR3>>
impl W<u32, Reg<u32, _OFR4>>
impl W<u32, Reg<u32, _AWD2CR>>
impl W<u32, Reg<u32, _AWD3CR>>
impl W<u32, Reg<u32, _DIFSEL>>
Bits 1:15 - Differential mode for channels 15 to 1
impl W<u32, Reg<u32, _CALFACT>>
impl W<u32, Reg<u32, _MODER>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
Bit 16 - Port x lock bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _MODER>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
Bit 16 - Port x lock bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _MODER>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OTYPER>>
Bit 15 - Port x configuration bits (y = 0..15)
Bit 14 - Port x configuration bits (y = 0..15)
Bit 13 - Port x configuration bits (y = 0..15)
Bit 12 - Port x configuration bits (y = 0..15)
Bit 11 - Port x configuration bits (y = 0..15)
Bit 10 - Port x configuration bits (y = 0..15)
Bit 9 - Port x configuration bits (y = 0..15)
Bit 8 - Port x configuration bits (y = 0..15)
Bit 7 - Port x configuration bits (y = 0..15)
Bit 6 - Port x configuration bits (y = 0..15)
Bit 5 - Port x configuration bits (y = 0..15)
Bit 4 - Port x configuration bits (y = 0..15)
Bit 3 - Port x configuration bits (y = 0..15)
Bit 2 - Port x configuration bits (y = 0..15)
Bit 1 - Port x configuration bits (y = 0..15)
Bit 0 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _OSPEEDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _PUPDR>>
Bits 30:31 - Port x configuration bits (y = 0..15)
Bits 28:29 - Port x configuration bits (y = 0..15)
Bits 26:27 - Port x configuration bits (y = 0..15)
Bits 24:25 - Port x configuration bits (y = 0..15)
Bits 22:23 - Port x configuration bits (y = 0..15)
Bits 20:21 - Port x configuration bits (y = 0..15)
Bits 18:19 - Port x configuration bits (y = 0..15)
Bits 16:17 - Port x configuration bits (y = 0..15)
Bits 14:15 - Port x configuration bits (y = 0..15)
Bits 12:13 - Port x configuration bits (y = 0..15)
Bits 10:11 - Port x configuration bits (y = 0..15)
Bits 8:9 - Port x configuration bits (y = 0..15)
Bits 6:7 - Port x configuration bits (y = 0..15)
Bits 4:5 - Port x configuration bits (y = 0..15)
Bits 2:3 - Port x configuration bits (y = 0..15)
Bits 0:1 - Port x configuration bits (y = 0..15)
impl W<u32, Reg<u32, _ODR>>
Bit 15 - Port output data (y = 0..15)
Bit 14 - Port output data (y = 0..15)
Bit 13 - Port output data (y = 0..15)
Bit 12 - Port output data (y = 0..15)
Bit 11 - Port output data (y = 0..15)
Bit 10 - Port output data (y = 0..15)
Bit 9 - Port output data (y = 0..15)
Bit 8 - Port output data (y = 0..15)
Bit 7 - Port output data (y = 0..15)
Bit 6 - Port output data (y = 0..15)
Bit 5 - Port output data (y = 0..15)
Bit 4 - Port output data (y = 0..15)
Bit 3 - Port output data (y = 0..15)
Bit 2 - Port output data (y = 0..15)
Bit 1 - Port output data (y = 0..15)
Bit 0 - Port output data (y = 0..15)
impl W<u32, Reg<u32, _BSRR>>
Bit 31 - Port x reset bit y (y = 0..15)
Bit 30 - Port x reset bit y (y = 0..15)
Bit 29 - Port x reset bit y (y = 0..15)
Bit 28 - Port x reset bit y (y = 0..15)
Bit 27 - Port x reset bit y (y = 0..15)
Bit 26 - Port x reset bit y (y = 0..15)
Bit 25 - Port x reset bit y (y = 0..15)
Bit 24 - Port x reset bit y (y = 0..15)
Bit 23 - Port x reset bit y (y = 0..15)
Bit 22 - Port x reset bit y (y = 0..15)
Bit 21 - Port x reset bit y (y = 0..15)
Bit 20 - Port x reset bit y (y = 0..15)
Bit 19 - Port x reset bit y (y = 0..15)
Bit 18 - Port x reset bit y (y = 0..15)
Bit 17 - Port x reset bit y (y = 0..15)
Bit 16 - Port x set bit y (y= 0..15)
Bit 15 - Port x set bit y (y= 0..15)
Bit 14 - Port x set bit y (y= 0..15)
Bit 13 - Port x set bit y (y= 0..15)
Bit 12 - Port x set bit y (y= 0..15)
Bit 11 - Port x set bit y (y= 0..15)
Bit 10 - Port x set bit y (y= 0..15)
Bit 9 - Port x set bit y (y= 0..15)
Bit 8 - Port x set bit y (y= 0..15)
Bit 7 - Port x set bit y (y= 0..15)
Bit 6 - Port x set bit y (y= 0..15)
Bit 5 - Port x set bit y (y= 0..15)
Bit 4 - Port x set bit y (y= 0..15)
Bit 3 - Port x set bit y (y= 0..15)
Bit 2 - Port x set bit y (y= 0..15)
Bit 1 - Port x set bit y (y= 0..15)
Bit 0 - Port x set bit y (y= 0..15)
impl W<u32, Reg<u32, _LCKR>>
Bit 16 - Port x lock bit y (y= 0..15)
Bit 15 - Port x lock bit y (y= 0..15)
Bit 14 - Port x lock bit y (y= 0..15)
Bit 13 - Port x lock bit y (y= 0..15)
Bit 12 - Port x lock bit y (y= 0..15)
Bit 11 - Port x lock bit y (y= 0..15)
Bit 10 - Port x lock bit y (y= 0..15)
Bit 9 - Port x lock bit y (y= 0..15)
Bit 8 - Port x lock bit y (y= 0..15)
Bit 7 - Port x lock bit y (y= 0..15)
Bit 6 - Port x lock bit y (y= 0..15)
Bit 5 - Port x lock bit y (y= 0..15)
Bit 4 - Port x lock bit y (y= 0..15)
Bit 3 - Port x lock bit y (y= 0..15)
Bit 2 - Port x lock bit y (y= 0..15)
Bit 1 - Port x lock bit y (y= 0..15)
Bit 0 - Port x lock bit y (y= 0..15)
impl W<u32, Reg<u32, _AFRL>>
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl W<u32, Reg<u32, _AFRH>>
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl W<u32, Reg<u32, _CR1>>
Bits 20:23 - Master clock divider
Bit 16 - Audio block A enable
Bits 10:11 - Synchronization enable
Bit 9 - Clock strobing edge
Bit 8 - Least significant bit first
pub fn ds(&mut self) -> DS_W<'_>
Bits 2:3 - Protocol configuration
Bits 0:1 - Audio block mode
impl W<u32, Reg<u32, _CR2>>
Bits 14:15 - Companding mode
Bit 4 - Tristate management on data line
Bits 0:2 - FIFO threshold
impl W<u32, Reg<u32, _FRCR>>
Bit 18 - Frame synchronization offset
Bit 17 - Frame synchronization polarity
Bit 16 - Frame synchronization definition
Bits 8:14 - Frame synchronization active level length
impl W<u32, Reg<u32, _SLOTR>>
Bits 8:11 - Number of slots in an audio frame
Bits 0:4 - First bit offset
impl W<u32, Reg<u32, _IM>>
Bit 6 - Late frame synchronization detection interrupt enable
Bit 5 - Anticipated frame synchronization detection interrupt enable
Bit 4 - Codec not ready interrupt enable
Bit 3 - FIFO request interrupt enable
Bit 2 - Wrong clock configuration interrupt enable
Bit 1 - Mute detection interrupt enable
Bit 0 - Overrun/underrun interrupt enable
impl W<u32, Reg<u32, _SR>>
Bits 16:18 - FIFO level threshold
Bit 6 - Late frame synchronization detection
Bit 5 - Anticipated frame synchronization detection
Bit 2 - Wrong clock configuration flag. This bit is read only
Bit 0 - Overrun / underrun
impl W<u32, Reg<u32, _CLRFR>>
Bit 6 - Clear late frame synchronization detection flag
Bit 5 - Clear anticipated frame synchronization detection flag
Bit 4 - Clear codec not ready flag
Bit 2 - Clear wrong clock configuration flag
Bit 1 - Mute detection flag
Bit 0 - Clear overrun / underrun
impl W<u32, Reg<u32, _DR>>
impl W<u32, Reg<u32, _CR1>>
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
impl W<u32, Reg<u32, _CR2>>
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 15 - Output compare 2 clear enable
Bits 12:14 - Output compare 2 mode
Bit 11 - Output compare 2 preload enable
Bit 10 - Output compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output compare 1 clear enable
Bits 4:6 - Output compare 1 mode
Bit 3 - Output compare 1 preload enable
Bit 2 - Output compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
Bit 15 - Capture/Compare 4 output Polarity
Bit 13 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 9 - Capture/Compare 3 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 0:31 - Counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:31 - Auto-reload value
impl W<u32, Reg<u32, _CCR>>
Bits 0:31 - Capture/Compare 1 value
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR>>
Bits 0:2 - Timer2 ETR remap
Bits 3:4 - Internal trigger
impl W<u32, Reg<u32, _CR1>>
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
impl W<u32, Reg<u32, _CR2>>
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 7 - Break interrupt enable
Bit 6 - Trigger interrupt enable
Bit 5 - COM interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn bg(&mut self) -> BG_W<'_>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 16 - Output Compare 1 mode
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _RCR>>
Bits 0:7 - Repetition counter value
impl W<u32, Reg<u32, _CCR1>>
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _BDTR>>
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _CR1>>
Bit 2 - Update request source
Bit 7 - Auto-reload preload enable
Bits 8:9 - Clock division
Bit 11 - UIF status bit remapping
impl W<u32, Reg<u32, _CR2>>
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 7 - Break interrupt enable
Bit 6 - Trigger interrupt enable
Bit 5 - COM interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn bg(&mut self) -> BG_W<'_>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 16 - Output Compare 1 mode
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCER>>
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _RCR>>
Bits 0:7 - Repetition counter value
impl W<u32, Reg<u32, _CCR1>>
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _BDTR>>
Bits 0:7 - Dead-time generator setup
Bits 8:9 - Lock configuration
Bit 10 - Off-state selection for Idle mode
Bit 11 - Off-state selection for Run mode
Bit 14 - Automatic output enable
Bit 15 - Main output enable
Bits 16:19 - Break filter
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR1>>
Bits 0:1 - Input capture 1 remap
impl W<u32, Reg<u32, _OR2>>
Bit 0 - BRK BKIN input enable
Bit 8 - BRK DFSDM_BREAK1 enable
Bit 9 - BRK BKIN input polarity
Bit 10 - BRK COMP1 input polarity
Bit 11 - BRK COMP2 input polarit
impl W<u32, Reg<u32, _CR1>>
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
impl W<u32, Reg<u32, _CR2>>
Bit 14 - Output Idle state 4
Bit 13 - Output Idle state 3
Bit 12 - Output Idle state 3
Bit 11 - Output Idle state 2
Bit 10 - Output Idle state 2
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 7 - Break interrupt enable
Bit 5 - COM interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn bg(&mut self) -> BG_W<'_>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 15 - Output Compare 2 clear enable
Bits 12:14 - Output Compare 2 mode
Bit 11 - Output Compare 2 preload enable
Bit 10 - Output Compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output Compare 1 clear enable
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/Compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/compare 3 selection
impl W<u32, Reg<u32, _CCER>>
Bit 13 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 10 - Capture/Compare 3 complementary output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 6 - Capture/Compare 2 complementary output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _RCR>>
Bits 0:7 - Repetition counter value
impl W<u32, Reg<u32, _CCR>>
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _BDTR>>
Bit 15 - Main output enable
Bit 14 - Automatic output enable
Bit 11 - Off-state selection for Run mode
Bit 10 - Off-state selection for Idle mode
Bits 8:9 - Lock configuration
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR1>>
Bits 0:1 - External trigger remap on ADC1 analog watchdog
Bits 2:3 - External trigger remap on ADC3 analog watchdog
Bit 4 - Input Capture 1 remap
impl W<u32, Reg<u32, _CCMR3_OUTPUT>>
Bit 24 - Output Compare 6 mode bit 3
Bits 16:18 - Output Compare 5 mode bit 3
Bit 15 - Output compare 6 clear enable
Bits 12:14 - Output compare 6 mode
Bit 11 - Output compare 6 preload enable
Bit 10 - Output compare 6 fast enable
Bit 7 - Output compare 5 clear enable
Bits 4:6 - Output compare 5 mode
Bit 3 - Output compare 5 preload enable
Bit 2 - Output compare 5 fast enable
impl W<u32, Reg<u32, _CCR5>>
Bits 0:15 - Capture/Compare value
Bit 29 - Group Channel 5 and Channel 1
Bit 30 - Group Channel 5 and Channel 2
Bit 31 - Group Channel 5 and Channel 3
impl W<u32, Reg<u32, _CCR6>>
Bits 0:15 - Capture/Compare value
impl W<u32, Reg<u32, _OR2>>
Bit 0 - BRK BKIN input enable
Bit 8 - BRK DFSDM_BREAK0 enable
Bit 9 - BRK BKIN input polarity
Bit 10 - BRK COMP1 input polarity
Bit 11 - BRK COMP2 input polarity
Bits 14:16 - ETR source selection
impl W<u32, Reg<u32, _OR3>>
Bit 0 - BRK2 BKIN input enable
Bit 1 - BRK2 COMP1 enable
Bit 2 - BRK2 COMP2 enable
Bit 8 - BRK2 DFSDM_BREAK0 enable
Bit 9 - BRK2 BKIN input polarity
Bit 10 - BRK2 COMP1 input polarity
Bit 11 - BRK2 COMP2 input polarity
impl W<u32, Reg<u32, _CR1>>
Bit 7 - Auto-reload preload enable
Bit 2 - Update request source
impl W<u32, Reg<u32, _CR2>>
Bits 4:6 - Master mode selection
impl W<u32, Reg<u32, _DIER>>
Bit 8 - Update DMA request enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - Low counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Low Auto-reload value
impl W<u32, Reg<u32, _ICR>>
Bit 6 - Direction change to down Clear Flag
Bit 5 - Direction change to UP Clear Flag
Bit 4 - Autoreload register update OK Clear Flag
Bit 3 - Compare register update OK Clear Flag
Bit 2 - External trigger valid edge Clear Flag
Bit 1 - Autoreload match Clear Flag
Bit 0 - compare match Clear Flag
impl W<u32, Reg<u32, _IER>>
Bit 6 - Direction change to down Interrupt Enable
Bit 5 - Direction change to UP Interrupt Enable
Bit 4 - Autoreload register update OK Interrupt Enable
Bit 3 - Compare register update OK Interrupt Enable
Bit 2 - External trigger valid edge Interrupt Enable
Bit 1 - Autoreload match Interrupt Enable
Bit 0 - Compare match Interrupt Enable
impl W<u32, Reg<u32, _CFGR>>
Bit 24 - Encoder mode enable
Bit 23 - counter mode enabled
Bit 22 - Registers update mode
Bit 21 - Waveform shape polarity
Bits 17:18 - Trigger enable and polarity
Bits 13:15 - Trigger selector
Bits 9:11 - Clock prescaler
Bits 6:7 - Configurable digital filter for trigger
Bits 3:4 - Configurable digital filter for external clock
Bits 1:2 - Clock Polarity
impl W<u32, Reg<u32, _CR>>
Bit 2 - Timer start in continuous mode
Bit 1 - LPTIM start in single mode
impl W<u32, Reg<u32, _CMP>>
Bits 0:15 - Compare value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto reload value
impl W<u32, Reg<u32, _CR1>>
pub fn m1(&mut self) -> M1_W<'_>
Bit 27 - End of Block interrupt enable
Bit 26 - Receiver timeout interrupt enable
Bit 15 - Oversampling mode
Bit 14 - Character match interrupt enable
Bit 13 - Mute mode enable
pub fn m0(&mut self) -> M0_W<'_>
Bit 11 - Receiver wakeup method
Bit 10 - Parity control enable
pub fn ps(&mut self) -> PS_W<'_>
Bit 8 - PE interrupt enable
Bit 6 - Transmission complete interrupt enable
Bit 5 - RXNE interrupt enable
Bit 4 - IDLE interrupt enable
pub fn te(&mut self) -> TE_W<'_>
Bit 3 - Transmitter enable
pub fn re(&mut self) -> RE_W<'_>
Bit 1 - USART enable in Stop mode
pub fn ue(&mut self) -> UE_W<'_>
Bits 16:20 - Driver Enable de-assertion time
Bits 21:25 - Driver Enable assertion time
impl W<u32, Reg<u32, _CR2>>
Bit 23 - Receiver timeout enable
Bit 20 - Auto baud rate enable
Bit 19 - Most significant bit first
Bit 18 - Binary data inversion
Bit 17 - TX pin active level inversion
Bit 16 - RX pin active level inversion
Bit 8 - Last bit clock pulse
Bit 6 - LIN break detection interrupt enable
Bit 5 - LIN break detection length
Bit 4 - 7-bit Address Detection/4-bit Address Detection
Bits 24:31 - Address of the USART node
Bits 21:22 - Auto baud rate mode
impl W<u32, Reg<u32, _CR3>>
Bit 22 - Wakeup from Stop mode interrupt enable
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
Bits 17:19 - Smartcard auto-retry count
Bit 15 - Driver enable polarity selection
Bit 14 - Driver enable mode
Bit 13 - DMA Disable on Reception Error
Bit 11 - One sample bit method enable
Bit 10 - CTS interrupt enable
Bit 7 - DMA enable transmitter
Bit 6 - DMA enable receiver
Bit 5 - Smartcard mode enable
Bit 4 - Smartcard NACK enable
Bit 3 - Half-duplex selection
Bit 0 - Error interrupt enable
impl W<u32, Reg<u32, _BRR>>
impl W<u32, Reg<u32, _GTPR>>
pub fn gt(&mut self) -> GT_W<'_>
Bits 8:15 - Guard time value
Bits 0:7 - Prescaler value
impl W<u32, Reg<u32, _RTOR>>
Bits 24:31 - Block Length
Bits 0:23 - Receiver timeout value
impl W<u32, Reg<u32, _RQR>>
Bit 4 - Transmit data flush request
Bit 3 - Receive data flush request
Bit 2 - Mute mode request
Bit 1 - Send break request
Bit 0 - Auto baud rate request
impl W<u32, Reg<u32, _ICR>>
Bit 20 - Wakeup from Stop mode clear flag
Bit 17 - Character match clear flag
Bit 12 - End of block clear flag
Bit 11 - Receiver timeout clear flag
Bit 8 - LIN break detection clear flag
Bit 6 - Transmission complete clear flag
Bit 4 - Idle line detected clear flag
Bit 3 - Overrun error clear flag
Bit 2 - Noise detected clear flag
Bit 1 - Framing error clear flag
Bit 0 - Parity error clear flag
impl W<u32, Reg<u32, _TDR>>
Bits 0:8 - Transmit data value
impl W<u32, Reg<u32, _CR1>>
pub fn m1(&mut self) -> M1_W<'_>
Bit 14 - Character match interrupt enable
Bit 13 - Mute mode enable
pub fn m0(&mut self) -> M0_W<'_>
Bit 11 - Receiver wakeup method
Bit 10 - Parity control enable
pub fn ps(&mut self) -> PS_W<'_>
Bit 8 - PE interrupt enable
Bit 6 - Transmission complete interrupt enable
Bit 5 - RXNE interrupt enable
Bit 4 - IDLE interrupt enable
pub fn te(&mut self) -> TE_W<'_>
Bit 3 - Transmitter enable
pub fn re(&mut self) -> RE_W<'_>
Bit 1 - USART enable in Stop mode
pub fn ue(&mut self) -> UE_W<'_>
Bits 21:25 - Driver Enable assertion time
Bits 16:20 - Driver Enable de-assertion time
impl W<u32, Reg<u32, _CR2>>
Bit 19 - Most significant bit first
Bit 18 - Binary data inversion
Bit 17 - TX pin active level inversion
Bit 16 - RX pin active level inversion
Bit 4 - 7-bit Address Detection/4-bit Address Detection
Bits 24:31 - Address of the USART node
impl W<u32, Reg<u32, _CR3>>
Bit 22 - Wakeup from Stop mode interrupt enable
Bits 20:21 - Wakeup from Stop mode interrupt flag selection
Bit 15 - Driver enable polarity selection
Bit 14 - Driver enable mode
Bit 13 - DMA Disable on Reception Error
Bit 10 - CTS interrupt enable
Bit 7 - DMA enable transmitter
Bit 6 - DMA enable receiver
Bit 3 - Half-duplex selection
Bit 0 - Error interrupt enable
impl W<u32, Reg<u32, _BRR>>
impl W<u32, Reg<u32, _RQR>>
Bit 3 - Receive data flush request
Bit 2 - Mute mode request
Bit 1 - Send break request
impl W<u32, Reg<u32, _ICR>>
Bit 20 - Wakeup from Stop mode clear flag
Bit 17 - Character match clear flag
Bit 6 - Transmission complete clear flag
Bit 4 - Idle line detected clear flag
Bit 3 - Overrun error clear flag
Bit 2 - Noise detected clear flag
Bit 1 - Framing error clear flag
Bit 0 - Parity error clear flag
impl W<u32, Reg<u32, _TDR>>
Bits 0:8 - Transmit data value
impl W<u32, Reg<u32, _CR1>>
Bit 15 - Bidirectional data mode enable
Bit 14 - Output enable in bidirectional mode
Bit 13 - Hardware CRC calculation enable
Bit 12 - CRC transfer next
Bit 9 - Software slave management
Bit 8 - Internal slave select
pub fn br(&mut self) -> BR_W<'_>
Bits 3:5 - Baud rate control
impl W<u32, Reg<u32, _CR2>>
Bit 0 - Rx buffer DMA enable
Bit 1 - Tx buffer DMA enable
Bit 3 - NSS pulse management
Bit 5 - Error interrupt enable
Bit 6 - RX buffer not empty interrupt enable
Bit 7 - Tx buffer empty interrupt enable
pub fn ds(&mut self) -> DS_W<'_>
Bit 12 - FIFO reception threshold
Bit 13 - Last DMA transfer for reception
Bit 14 - Last DMA transfer for transmission
impl W<u32, Reg<u32, _SR>>
impl W<u32, Reg<u32, _DR>>
pub fn dr(&mut self) -> DR_W<'_>
Bits 0:15 - Data register
impl W<u32, Reg<u32, _CRCPR>>
Bits 0:15 - CRC polynomial register
impl W<u32, Reg<u32, _POWER>>
impl W<u32, Reg<u32, _CLKCR>>
Bit 14 - HW Flow Control enable
Bit 13 - SDIO_CK dephasing selection bit
Bits 11:12 - Wide bus mode enable bit
Bit 10 - Clock divider bypass enable bit
Bit 9 - Power saving configuration bit
Bits 0:7 - Clock divide factor
impl W<u32, Reg<u32, _ARG>>
Bits 0:31 - Command argument
impl W<u32, Reg<u32, _CMD>>
Bit 13 - not Interrupt Enable
Bit 12 - Enable CMD completion
Bit 11 - SD I/O suspend command
Bit 10 - Command path state machine (CPSM) Enable bit
Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal)
Bit 8 - CPSM waits for interrupt request
Bits 6:7 - Wait for response bits
impl W<u32, Reg<u32, _DTIMER>>
Bits 0:31 - Data timeout period
impl W<u32, Reg<u32, _DLEN>>
Bits 0:24 - Data length value
impl W<u32, Reg<u32, _DCTRL>>
Bit 11 - SD I/O enable functions
Bits 4:7 - Data block size
Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer
Bit 1 - Data transfer direction selection
impl W<u32, Reg<u32, _ICR>>
Bit 23 - CEATAEND flag clear bit
Bit 22 - SDIOIT flag clear bit
Bit 10 - DBCKEND flag clear bit
Bit 9 - STBITERR flag clear bit
Bit 8 - DATAEND flag clear bit
Bit 7 - CMDSENT flag clear bit
Bit 6 - CMDREND flag clear bit
Bit 5 - RXOVERR flag clear bit
Bit 4 - TXUNDERR flag clear bit
Bit 3 - DTIMEOUT flag clear bit
Bit 2 - CTIMEOUT flag clear bit
Bit 1 - DCRCFAIL flag clear bit
Bit 0 - CCRCFAIL flag clear bit
impl W<u32, Reg<u32, _MASK>>
Bit 23 - CE-ATA command completion signal received interrupt enable
Bit 22 - SDIO mode interrupt received interrupt enable
Bit 21 - Data available in Rx FIFO interrupt enable
Bit 20 - Data available in Tx FIFO interrupt enable
Bit 19 - Rx FIFO empty interrupt enable
Bit 18 - Tx FIFO empty interrupt enable
Bit 17 - Rx FIFO full interrupt enable
Bit 16 - Tx FIFO full interrupt enable
Bit 15 - Rx FIFO half full interrupt enable
Bit 14 - Tx FIFO half empty interrupt enable
Bit 13 - Data receive acting interrupt enable
Bit 12 - Data transmit acting interrupt enable
Bit 11 - Command acting interrupt enable
Bit 10 - Data block end interrupt enable
Bit 9 - Start bit error interrupt enable
Bit 8 - Data end interrupt enable
Bit 7 - Command sent interrupt enable
Bit 6 - Command response received interrupt enable
Bit 5 - Rx FIFO overrun error interrupt enable
Bit 4 - Tx FIFO underrun error interrupt enable
Bit 3 - Data timeout interrupt enable
Bit 2 - Command timeout interrupt enable
Bit 1 - Data CRC fail interrupt enable
Bit 0 - Command CRC fail interrupt enable
impl W<u32, Reg<u32, _FIFO>>
Bits 0:31 - Receive and transmit FIFO data
impl W<u32, Reg<u32, _IMR1>>
Bit 0 - Interrupt Mask on line 0
Bit 1 - Interrupt Mask on line 1
Bit 2 - Interrupt Mask on line 2
Bit 3 - Interrupt Mask on line 3
Bit 4 - Interrupt Mask on line 4
Bit 5 - Interrupt Mask on line 5
Bit 6 - Interrupt Mask on line 6
Bit 7 - Interrupt Mask on line 7
Bit 8 - Interrupt Mask on line 8
Bit 9 - Interrupt Mask on line 9
Bit 10 - Interrupt Mask on line 10
Bit 11 - Interrupt Mask on line 11
Bit 12 - Interrupt Mask on line 12
Bit 13 - Interrupt Mask on line 13
Bit 14 - Interrupt Mask on line 14
Bit 15 - Interrupt Mask on line 15
Bit 16 - Interrupt Mask on line 16
Bit 17 - Interrupt Mask on line 17
Bit 18 - Interrupt Mask on line 18
Bit 19 - Interrupt Mask on line 19
Bit 20 - Interrupt Mask on line 20
Bit 21 - Interrupt Mask on line 21
Bit 22 - Interrupt Mask on line 22
Bit 23 - Interrupt Mask on line 23
Bit 24 - Interrupt Mask on line 24
Bit 25 - Interrupt Mask on line 25
Bit 26 - Interrupt Mask on line 26
Bit 27 - Interrupt Mask on line 27
Bit 28 - Interrupt Mask on line 28
Bit 29 - Interrupt Mask on line 29
Bit 30 - Interrupt Mask on line 30
Bit 31 - Interrupt Mask on line 31
impl W<u32, Reg<u32, _EMR1>>
Bit 0 - Event Mask on line 0
Bit 1 - Event Mask on line 1
Bit 2 - Event Mask on line 2
Bit 3 - Event Mask on line 3
Bit 4 - Event Mask on line 4
Bit 5 - Event Mask on line 5
Bit 6 - Event Mask on line 6
Bit 7 - Event Mask on line 7
Bit 8 - Event Mask on line 8
Bit 9 - Event Mask on line 9
Bit 10 - Event Mask on line 10
Bit 11 - Event Mask on line 11
Bit 12 - Event Mask on line 12
Bit 13 - Event Mask on line 13
Bit 14 - Event Mask on line 14
Bit 15 - Event Mask on line 15
Bit 16 - Event Mask on line 16
Bit 17 - Event Mask on line 17
Bit 18 - Event Mask on line 18
Bit 19 - Event Mask on line 19
Bit 20 - Event Mask on line 20
Bit 21 - Event Mask on line 21
Bit 22 - Event Mask on line 22
Bit 23 - Event Mask on line 23
Bit 24 - Event Mask on line 24
Bit 25 - Event Mask on line 25
Bit 26 - Event Mask on line 26
Bit 27 - Event Mask on line 27
Bit 28 - Event Mask on line 28
Bit 29 - Event Mask on line 29
Bit 30 - Event Mask on line 30
Bit 31 - Event Mask on line 31
impl W<u32, Reg<u32, _RTSR1>>
Bit 0 - Rising trigger event configuration of line 0
Bit 1 - Rising trigger event configuration of line 1
Bit 2 - Rising trigger event configuration of line 2
Bit 3 - Rising trigger event configuration of line 3
Bit 4 - Rising trigger event configuration of line 4
Bit 5 - Rising trigger event configuration of line 5
Bit 6 - Rising trigger event configuration of line 6
Bit 7 - Rising trigger event configuration of line 7
Bit 8 - Rising trigger event configuration of line 8
Bit 9 - Rising trigger event configuration of line 9
Bit 10 - Rising trigger event configuration of line 10
Bit 11 - Rising trigger event configuration of line 11
Bit 12 - Rising trigger event configuration of line 12
Bit 13 - Rising trigger event configuration of line 13
Bit 14 - Rising trigger event configuration of line 14
Bit 15 - Rising trigger event configuration of line 15
Bit 16 - Rising trigger event configuration of line 16
Bit 18 - Rising trigger event configuration of line 18
Bit 19 - Rising trigger event configuration of line 19
Bit 20 - Rising trigger event configuration of line 20
Bit 21 - Rising trigger event configuration of line 21
Bit 22 - Rising trigger event configuration of line 22
impl W<u32, Reg<u32, _FTSR1>>
Bit 0 - Falling trigger event configuration of line 0
Bit 1 - Falling trigger event configuration of line 1
Bit 2 - Falling trigger event configuration of line 2
Bit 3 - Falling trigger event configuration of line 3
Bit 4 - Falling trigger event configuration of line 4
Bit 5 - Falling trigger event configuration of line 5
Bit 6 - Falling trigger event configuration of line 6
Bit 7 - Falling trigger event configuration of line 7
Bit 8 - Falling trigger event configuration of line 8
Bit 9 - Falling trigger event configuration of line 9
Bit 10 - Falling trigger event configuration of line 10
Bit 11 - Falling trigger event configuration of line 11
Bit 12 - Falling trigger event configuration of line 12
Bit 13 - Falling trigger event configuration of line 13
Bit 14 - Falling trigger event configuration of line 14
Bit 15 - Falling trigger event configuration of line 15
Bit 16 - Falling trigger event configuration of line 16
Bit 18 - Falling trigger event configuration of line 18
Bit 19 - Falling trigger event configuration of line 19
Bit 20 - Falling trigger event configuration of line 20
Bit 21 - Falling trigger event configuration of line 21
Bit 22 - Falling trigger event configuration of line 22
impl W<u32, Reg<u32, _SWIER1>>
Bit 0 - Software Interrupt on line 0
Bit 1 - Software Interrupt on line 1
Bit 2 - Software Interrupt on line 2
Bit 3 - Software Interrupt on line 3
Bit 4 - Software Interrupt on line 4
Bit 5 - Software Interrupt on line 5
Bit 6 - Software Interrupt on line 6
Bit 7 - Software Interrupt on line 7
Bit 8 - Software Interrupt on line 8
Bit 9 - Software Interrupt on line 9
Bit 10 - Software Interrupt on line 10
Bit 11 - Software Interrupt on line 11
Bit 12 - Software Interrupt on line 12
Bit 13 - Software Interrupt on line 13
Bit 14 - Software Interrupt on line 14
Bit 15 - Software Interrupt on line 15
Bit 16 - Software Interrupt on line 16
Bit 18 - Software Interrupt on line 18
Bit 19 - Software Interrupt on line 19
Bit 20 - Software Interrupt on line 20
Bit 21 - Software Interrupt on line 21
Bit 22 - Software Interrupt on line 22
impl W<u32, Reg<u32, _PR1>>
impl W<u32, Reg<u32, _IMR2>>
Bit 0 - Interrupt Mask on external/internal line 32
Bit 1 - Interrupt Mask on external/internal line 33
Bit 2 - Interrupt Mask on external/internal line 34
Bit 3 - Interrupt Mask on external/internal line 35
Bit 4 - Interrupt Mask on external/internal line 36
Bit 5 - Interrupt Mask on external/internal line 37
Bit 6 - Interrupt Mask on external/internal line 38
Bit 7 - Interrupt Mask on external/internal line 39
impl W<u32, Reg<u32, _EMR2>>
Bit 0 - Event mask on external/internal line 32
Bit 1 - Event mask on external/internal line 33
Bit 2 - Event mask on external/internal line 34
Bit 3 - Event mask on external/internal line 35
Bit 4 - Event mask on external/internal line 36
Bit 5 - Event mask on external/internal line 37
Bit 6 - Event mask on external/internal line 38
Bit 7 - Event mask on external/internal line 39
impl W<u32, Reg<u32, _RTSR2>>
Bit 3 - Rising trigger event configuration bit of line 35
Bit 4 - Rising trigger event configuration bit of line 36
Bit 5 - Rising trigger event configuration bit of line 37
Bit 6 - Rising trigger event configuration bit of line 38
impl W<u32, Reg<u32, _FTSR2>>
Bit 3 - Falling trigger event configuration bit of line 35
Bit 4 - Falling trigger event configuration bit of line 36
Bit 5 - Falling trigger event configuration bit of line 37
Bit 6 - Falling trigger event configuration bit of line 38
impl W<u32, Reg<u32, _SWIER2>>
Bit 3 - Software interrupt on line 35
Bit 4 - Software interrupt on line 36
Bit 5 - Software interrupt on line 37
Bit 6 - Software interrupt on line 38
impl W<u32, Reg<u32, _PR2>>
Bit 3 - Pending interrupt flag on line 35
Bit 4 - Pending interrupt flag on line 36
Bit 5 - Pending interrupt flag on line 37
Bit 6 - Pending interrupt flag on line 38
impl W<u32, Reg<u32, _CSR>>
Bit 0 - Voltage reference buffer enable
Bit 1 - High impedance mode
Bit 2 - Voltage reference scale
impl W<u32, Reg<u32, _CCR>>
impl W<u32, Reg<u32, _TIR>>
impl W<u32, Reg<u32, _TDTR>>
impl W<u32, Reg<u32, _TDLR>>
impl W<u32, Reg<u32, _TDHR>>
impl W<u32, Reg<u32, _FR1>>
pub fn fb(&mut self) -> FB_W<'_>
impl W<u32, Reg<u32, _FR2>>
pub fn fb(&mut self) -> FB_W<'_>
impl W<u32, Reg<u32, _MCR>>
impl W<u32, Reg<u32, _MSR>>
impl W<u32, Reg<u32, _TSR>>
impl W<u32, Reg<u32, _RFR>>
impl W<u32, Reg<u32, _IER>>
impl W<u32, Reg<u32, _ESR>>
impl W<u32, Reg<u32, _BTR>>
impl W<u32, Reg<u32, _TR>>
pub fn pm(&mut self) -> PM_W<'_>
pub fn ht(&mut self) -> HT_W<'_>
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
Bits 16:19 - Hour units in BCD format
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
pub fn st(&mut self) -> ST_W<'_>
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _DR>>
pub fn yt(&mut self) -> YT_W<'_>
Bits 20:23 - Year tens in BCD format
pub fn yu(&mut self) -> YU_W<'_>
Bits 16:19 - Year units in BCD format
Bits 13:15 - Week day units
pub fn mt(&mut self) -> MT_W<'_>
Bit 12 - Month tens in BCD format
pub fn mu(&mut self) -> MU_W<'_>
Bits 8:11 - Month units in BCD format
pub fn dt(&mut self) -> DT_W<'_>
Bits 4:5 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
Bits 0:3 - Date units in BCD format
impl W<u32, Reg<u32, _CR>>
Bits 0:2 - Wakeup clock selection
Bit 3 - Time-stamp event active edge
Bit 4 - Reference clock detection enable (50 or 60 Hz)
Bit 5 - Bypass the shadow registers
Bit 10 - Wakeup timer enable
Bit 11 - Time stamp enable
Bit 12 - Alarm A interrupt enable
Bit 13 - Alarm B interrupt enable
Bit 14 - Wakeup timer interrupt enable
Bit 15 - Time-stamp interrupt enable
Bit 16 - Add 1 hour (summer time change)
Bit 17 - Subtract 1 hour (winter time change)
Bit 19 - Calibration output selection
Bits 21:22 - Output selection
Bit 23 - Calibration output enable
Bit 24 - timestamp on internal event enable
impl W<u32, Reg<u32, _ISR>>
Bit 3 - Shift operation pending
Bit 5 - Registers synchronization flag
Bit 7 - Initialization mode
Bit 10 - Wakeup timer flag
Bit 12 - Time-stamp overflow flag
Bit 13 - Tamper detection flag
Bit 14 - RTC_TAMP2 detection flag
Bit 15 - RTC_TAMP3 detection flag
impl W<u32, Reg<u32, _PRER>>
Bits 16:22 - Asynchronous prescaler factor
Bits 0:14 - Synchronous prescaler factor
impl W<u32, Reg<u32, _WUTR>>
Bits 0:15 - Wakeup auto-reload value bits
impl W<u32, Reg<u32, _ALRMAR>>
Bit 31 - Alarm A date mask
Bit 30 - Week day selection
pub fn dt(&mut self) -> DT_W<'_>
Bits 28:29 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm A hours mask
pub fn pm(&mut self) -> PM_W<'_>
pub fn ht(&mut self) -> HT_W<'_>
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm A minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm A seconds mask
pub fn st(&mut self) -> ST_W<'_>
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _ALRMBR>>
Bit 31 - Alarm B date mask
Bit 30 - Week day selection
pub fn dt(&mut self) -> DT_W<'_>
Bits 28:29 - Date tens in BCD format
pub fn du(&mut self) -> DU_W<'_>
Bits 24:27 - Date units or day in BCD format
Bit 23 - Alarm B hours mask
pub fn pm(&mut self) -> PM_W<'_>
pub fn ht(&mut self) -> HT_W<'_>
Bits 20:21 - Hour tens in BCD format
pub fn hu(&mut self) -> HU_W<'_>
Bits 16:19 - Hour units in BCD format
Bit 15 - Alarm B minutes mask
Bits 12:14 - Minute tens in BCD format
Bits 8:11 - Minute units in BCD format
Bit 7 - Alarm B seconds mask
pub fn st(&mut self) -> ST_W<'_>
Bits 4:6 - Second tens in BCD format
pub fn su(&mut self) -> SU_W<'_>
Bits 0:3 - Second units in BCD format
impl W<u32, Reg<u32, _WPR>>
Bits 0:7 - Write protection key
impl W<u32, Reg<u32, _SHIFTR>>
Bits 0:14 - Subtract a fraction of a second
impl W<u32, Reg<u32, _CALR>>
Bit 15 - Increase frequency of RTC by 488.5 ppm
Bit 14 - Use an 8-second calibration cycle period
Bit 13 - Use a 16-second calibration cycle period
Bits 0:8 - Calibration minus
impl W<u32, Reg<u32, _TAMPCR>>
Bit 0 - Tamper 1 detection enable
Bit 1 - Active level for tamper 1
Bit 2 - Tamper interrupt enable
Bit 3 - Tamper 2 detection enable
Bit 4 - Active level for tamper 2
Bit 5 - Tamper 3 detection enable
Bit 6 - Active level for tamper 3
Bit 7 - Activate timestamp on tamper detection event
Bits 8:10 - Tamper sampling frequency
Bits 11:12 - Tamper filter count
Bits 13:14 - Tamper precharge duration
Bit 15 - TAMPER pull-up disable
Bit 16 - Tamper 1 interrupt enable
Bit 17 - Tamper 1 no erase
Bit 18 - Tamper 1 mask flag
Bit 19 - Tamper 2 interrupt enable
Bit 20 - Tamper 2 no erase
Bit 21 - Tamper 2 mask flag
Bit 22 - Tamper 3 interrupt enable
Bit 23 - Tamper 3 no erase
Bit 24 - Tamper 3 mask flag
impl W<u32, Reg<u32, _ALRMASSR>>
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&mut self) -> SS_W<'_>
Bits 0:14 - Sub seconds value
impl W<u32, Reg<u32, _ALRMBSSR>>
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&mut self) -> SS_W<'_>
Bits 0:14 - Sub seconds value
impl W<u32, Reg<u32, _OR>>
Bit 0 - RTC_ALARM on PC13 output type
impl W<u32, Reg<u32, _BKPR>>
impl W<u32, Reg<u32, _CR>>
Bit 0 - Reception DMA enable
Bit 1 - Transmission DMA enable
Bit 2 - Reception buffering mode
Bit 3 - Transmission buffering mode
Bit 4 - Loopback mode enable
Bit 5 - Single wire protocol master interface enable
Bit 10 - Single wire protocol master interface deactivate
impl W<u32, Reg<u32, _BRR>>
pub fn br(&mut self) -> BR_W<'_>
Bits 0:5 - Bitrate prescaler
impl W<u32, Reg<u32, _ICR>>
Bit 0 - Clear receive buffer full flag
Bit 1 - Clear transmit buffer empty flag
Bit 2 - Clear receive CRC error flag
Bit 3 - Clear receive overrun error flag
Bit 4 - Clear transmit underrun error flag
Bit 7 - Clear transfer complete flag
Bit 8 - Clear slave resume flag
impl W<u32, Reg<u32, _IER>>
Bit 0 - Receive buffer full interrupt enable
Bit 1 - Transmit buffer empty interrupt enable
Bit 2 - Receive CRC error interrupt enable
Bit 3 - Receive overrun error interrupt enable
Bit 4 - Transmit underrun error interrupt enable
Bit 5 - Receive interrupt enable
Bit 6 - Transmit interrupt enable
Bit 7 - Transmit complete interrupt enable
Bit 8 - Slave resume interrupt enable
impl W<u32, Reg<u32, _TDR>>
pub fn td(&mut self) -> TD_W<'_>
Bits 0:31 - Transmit data
impl W<u32, Reg<u32, _OR>>
Bit 0 - SWP transceiver bypass
Bit 1 - SWP class selection
impl W<u32, Reg<u32, _OPAMP1_CSR>>
Bit 0 - Operational amplifier Enable
Bit 1 - Operational amplifier Low Power Mode
Bits 2:3 - Operational amplifier PGA mode
Bits 4:5 - Operational amplifier Programmable amplifier gain value
Bits 8:9 - Inverting input selection
Bit 10 - Non inverted input selection
Bit 12 - Calibration mode enabled
Bit 13 - Calibration selection
Bit 14 - allows to switch from AOP offset trimmed values to AOP offset
Bit 15 - Operational amplifier calibration output
Bit 31 - Operational amplifier power supply range for stability
impl W<u32, Reg<u32, _OPAMP1_OTR>>
Bits 0:4 - Trim for NMOS differential pairs
Bits 8:12 - Trim for PMOS differential pairs
impl W<u32, Reg<u32, _OPAMP1_LPOTR>>
Bits 0:4 - Trim for NMOS differential pairs
Bits 8:12 - Trim for PMOS differential pairs
impl W<u32, Reg<u32, _OPAMP2_CSR>>
Bit 0 - Operational amplifier Enable
Bit 1 - Operational amplifier Low Power Mode
Bits 2:3 - Operational amplifier PGA mode
Bits 4:5 - Operational amplifier Programmable amplifier gain value
Bits 8:9 - Inverting input selection
Bit 10 - Non inverted input selection
Bit 12 - Calibration mode enabled
Bit 13 - Calibration selection
Bit 14 - allows to switch from AOP offset trimmed values to AOP offset
Bit 15 - Operational amplifier calibration output
impl W<u32, Reg<u32, _OPAMP2_OTR>>
Bits 0:4 - Trim for NMOS differential pairs
Bits 8:12 - Trim for PMOS differential pairs
impl W<u32, Reg<u32, _OPAMP2_LPOTR>>
Bits 0:4 - Trim for NMOS differential pairs
Bits 8:12 - Trim for PMOS differential pairs
impl W<u32, Reg<u32, _CR>>
Bits 8:13 - HSI48 oscillator smooth trimming
Bit 7 - Generate software SYNC event
Bit 6 - Automatic trimming enable
Bit 5 - Frequency error counter enable
Bit 3 - Expected SYNC interrupt enable
Bit 2 - Synchronization or trimming error interrupt enable
Bit 1 - SYNC warning interrupt enable
Bit 0 - SYNC event OK interrupt enable
impl W<u32, Reg<u32, _CFGR>>
Bit 31 - SYNC polarity selection
Bits 28:29 - SYNC signal source selection
Bits 24:26 - SYNC divider
Bits 16:23 - Frequency error limit
Bits 0:15 - Counter reload value
impl W<u32, Reg<u32, _ICR>>
Bit 3 - Expected SYNC clear flag
Bit 1 - SYNC warning clear flag
Bit 0 - SYNC event OK clear flag
impl W<u32, Reg<u32, _EP0R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP1R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP2R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP3R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP4R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP5R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP6R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _EP7R>>
pub fn ea(&mut self) -> EA_W<'_>
Bits 0:3 - Endpoint address
Bits 4:5 - Status bits, for transmission transfers
Bit 6 - Data Toggle, for transmission transfers
Bit 7 - Correct Transfer for transmission
Bits 9:10 - Endpoint type
Bit 11 - Setup transaction completed
Bits 12:13 - Status bits, for reception transfers
Bit 14 - Data Toggle, for reception transfers
Bit 15 - Correct transfer for reception
impl W<u32, Reg<u32, _CNTR>>
Bit 5 - LPM L1 Resume request
Bit 7 - LPM L1 state request interrupt mask
Bit 8 - Expected start of frame interrupt mask
Bit 9 - Start of frame interrupt mask
Bit 10 - USB reset interrupt mask
Bit 11 - Suspend mode interrupt mask
Bit 12 - Wakeup interrupt mask
Bit 13 - Error interrupt mask
Bit 14 - Packet memory area over / underrun interrupt mask
Bit 15 - Correct transfer interrupt mask
impl W<u32, Reg<u32, _ISTR>>
Bit 7 - LPM L1 state request
Bit 8 - Expected start frame
Bit 11 - Suspend mode request
Bit 14 - Packet memory area over / underrun
impl W<u32, Reg<u32, _DADDR>>
Bits 0:6 - Device address
pub fn ef(&mut self) -> EF_W<'_>
impl W<u32, Reg<u32, _BTABLE>>
impl W<u32, Reg<u32, _CR>>
Bits 24:31 - Clock prescaler
Bit 23 - Polling match mode
Bit 22 - Automatic poll mode stop
Bit 20 - TimeOut interrupt enable
Bit 19 - Status match interrupt enable
Bit 18 - FIFO threshold interrupt enable
Bit 17 - Transfer complete interrupt enable
Bit 16 - Transfer error interrupt enable
Bits 8:12 - IFO threshold level
Bit 7 - FLASH memory selection
Bit 3 - Timeout counter enable
pub fn en(&mut self) -> EN_W<'_>
impl W<u32, Reg<u32, _DCR>>
Bits 16:20 - FLASH memory size
Bits 8:10 - Chip select high time
impl W<u32, Reg<u32, _FCR>>
Bit 4 - Clear timeout flag
Bit 3 - Clear status match flag
Bit 1 - Clear transfer complete flag
Bit 0 - Clear transfer error flag
impl W<u32, Reg<u32, _DLR>>
pub fn dl(&mut self) -> DL_W<'_>
impl W<u32, Reg<u32, _CCR>>
Bit 31 - Double data rate mode
Bit 30 - DDR hold half cycle
Bit 28 - Send instruction only once mode
Bits 26:27 - Functional mode
Bits 18:22 - Number of dummy cycles
Bits 16:17 - Alternate bytes size
Bits 14:15 - Alternate bytes mode
Bits 12:13 - Address size
Bits 10:11 - Address mode
Bits 8:9 - Instruction mode
impl W<u32, Reg<u32, _AR>>
impl W<u32, Reg<u32, _ABR>>
impl W<u32, Reg<u32, _DR>>
impl W<u32, Reg<u32, _PSMKR>>
impl W<u32, Reg<u32, _PSMAR>>
impl W<u32, Reg<u32, _PIR>>
Bits 0:15 - Polling interval
impl W<u32, Reg<u32, _LPTR>>
Bits 0:15 - Timeout period
impl W<u32, Reg<u32, _BCR1>>
Bit 21 - Write FIFO Disable
Bits 16:18 - CRAM page size
impl W<u32, Reg<u32, _BTR>>
impl W<u32, Reg<u32, _BCR>>
Bit 21 - Write FIFO disable
Bits 16:18 - CRAM page size
impl W<u32, Reg<u32, _PCR>>
impl W<u32, Reg<u32, _SR>>
impl W<u32, Reg<u32, _PMEM>>
impl W<u32, Reg<u32, _PATT>>
impl W<u32, Reg<u32, _BWTR>>
Bits 16:19 - Bus turnaround phase duration
impl W<u32, Reg<u32, _CFGR1>>
impl W<u32, Reg<u32, _CFGR2>>
impl W<u32, Reg<u32, _AWSCDR>>
impl W<u32, Reg<u32, _WDATR>>
impl W<u32, Reg<u32, _DATINR>>
impl W<u32, Reg<u32, _CR2>>
Bit 30 - Analog watchdog fast mode select
Bit 29 - Fast conversion mode selection for regular conversions
Bits 24:26 - Regular channel selection
Bit 21 - DMA channel enabled to read data for the regular conversion
Bit 19 - Launch regular conversion synchronously with DFSDM0
Bit 18 - Continuous mode selection for regular conversions
Bit 17 - Software start of a conversion on the regular channel
Bits 13:14 - Trigger enable and trigger edge selection for injected conversions
Bits 8:10 - Trigger signal selection for launching injected conversions
Bit 5 - DMA channel enabled to read data for the injected channel group
Bit 4 - Scanning conversion mode for injected conversions
Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
Bit 1 - Start a conversion of the injected group of channels
impl W<u32, Reg<u32, _ICR>>
Bits 24:31 - Clear the short-circuit detector flag
Bits 16:23 - Clear the clock absence flag
Bit 3 - Clear the regular conversion overrun flag
Bit 2 - Clear the injected conversion overrun flag
impl W<u32, Reg<u32, _JCHGR>>
Bits 0:7 - Injected channel group selection
impl W<u32, Reg<u32, _FCR>>
Bits 29:31 - Sinc filter order
Bits 16:25 - Sinc filter oversampling ratio (decimation rate)
Bits 0:7 - Integrator oversampling ratio (averaging length)
impl W<u32, Reg<u32, _AWHTR>>
Bits 8:31 - Analog watchdog high threshold
Bits 0:3 - Break signal assignment to analog watchdog high threshold event
impl W<u32, Reg<u32, _AWLTR>>
Bits 8:31 - Analog watchdog low threshold
Bits 0:3 - Break signal assignment to analog watchdog low threshold event
impl W<u32, Reg<u32, _AWCFR>>
Bits 8:15 - Clear the analog watchdog high threshold flag
Bits 0:7 - Clear the analog watchdog low threshold flag
impl W<u32, Reg<u32, _DFSDM0_CR2>>
Bits 16:23 - Analog watchdog channel selection
Bits 8:15 - Extremes detector channel selection
Bit 6 - Clock absence interrupt enable
Bit 5 - Short-circuit detector interrupt enable
Bit 4 - Analog watchdog interrupt enable
Bit 3 - Regular data overrun interrupt enable
Bit 2 - Injected data overrun interrupt enable
Bit 1 - Regular end of conversion interrupt enable
Bit 0 - Injected end of conversion interrupt enable
impl W<u32, Reg<u32, _DFSDM1_CR2>>
Bits 16:23 - Analog watchdog channel selection
Bits 8:15 - Extremes detector channel selection
Bit 6 - Clock absence interrupt enable
Bit 5 - Short-circuit detector interrupt enable
Bit 4 - Analog watchdog interrupt enable
Bit 3 - Regular data overrun interrupt enable
Bit 2 - Injected data overrun interrupt enable
Bit 1 - Regular end of conversion interrupt enable
Bit 0 - Injected end of conversion interrupt enable
impl W<u32, Reg<u32, _DFSDM2_CR2>>
Bits 16:23 - Analog watchdog channel selection
Bits 8:15 - Extremes detector channel selection
Bit 6 - Clock absence interrupt enable
Bit 5 - Short-circuit detector interrupt enable
Bit 4 - Analog watchdog interrupt enable
Bit 3 - Regular data overrun interrupt enable
Bit 2 - Injected data overrun interrupt enable
Bit 1 - Regular end of conversion interrupt enable
Bit 0 - Injected end of conversion interrupt enable
impl W<u32, Reg<u32, _DFSDM3_CR2>>
Bits 16:23 - Analog watchdog channel selection
Bits 8:15 - Extremes detector channel selection
Bit 6 - Clock absence interrupt enable
Bit 5 - Short-circuit detector interrupt enable
Bit 4 - Analog watchdog interrupt enable
Bit 3 - Regular data overrun interrupt enable
Bit 2 - Injected data overrun interrupt enable
Bit 1 - Regular end of conversion interrupt enable
Bit 0 - Injected end of conversion interrupt enable
impl W<u32, Reg<u32, _CR1>>
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
impl W<u32, Reg<u32, _CR2>>
Bit 14 - Output Idle state 4
Bit 13 - Output Idle state 3
Bit 12 - Output Idle state 3
Bit 11 - Output Idle state 2
Bit 10 - Output Idle state 2
Bit 9 - Output Idle state 1
Bit 8 - Output Idle state 1
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
Bit 2 - Capture/compare control update selection
Bit 0 - Capture/compare preloaded control
impl W<u32, Reg<u32, _SMCR>>
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
Bit 7 - Break interrupt enable
Bit 5 - COM interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 7 - Break interrupt flag
Bit 6 - Trigger interrupt flag
Bit 5 - COM interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn bg(&mut self) -> BG_W<'_>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 5 - Capture/Compare control update generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 15 - Output Compare 2 clear enable
Bits 12:14 - Output Compare 2 mode
Bit 11 - Output Compare 2 preload enable
Bit 10 - Output Compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output Compare 1 clear enable
Bits 4:6 - Output Compare 1 mode
Bit 3 - Output Compare 1 preload enable
Bit 2 - Output Compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/Compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/compare 3 selection
impl W<u32, Reg<u32, _CCER>>
Bit 13 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 10 - Capture/Compare 3 complementary output enable
Bit 9 - Capture/Compare 3 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 6 - Capture/Compare 2 complementary output enable
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 2 - Capture/Compare 1 complementary output enable
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 0:15 - counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _RCR>>
Bits 0:7 - Repetition counter value
impl W<u32, Reg<u32, _CCR>>
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _BDTR>>
Bit 15 - Main output enable
Bit 14 - Automatic output enable
Bit 11 - Off-state selection for Run mode
Bit 10 - Off-state selection for Idle mode
Bits 8:9 - Lock configuration
Bits 0:7 - Dead-time generator setup
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR1>>
Bits 0:1 - External trigger remap on ADC2 analog watchdog
Bits 2:3 - External trigger remap on ADC3 analog watchdog
Bit 4 - Input Capture 1 remap
impl W<u32, Reg<u32, _CCMR3_OUTPUT>>
Bit 24 - Output Compare 6 mode bit 3
Bits 16:18 - Output Compare 5 mode bit 3
Bit 15 - Output compare 6 clear enable
Bits 12:14 - Output compare 6 mode
Bit 11 - Output compare 6 preload enable
Bit 10 - Output compare 6 fast enable
Bit 7 - Output compare 5 clear enable
Bits 4:6 - Output compare 5 mode
Bit 3 - Output compare 5 preload enable
Bit 2 - Output compare 5 fast enable
impl W<u32, Reg<u32, _CCR5>>
Bits 0:15 - Capture/Compare value
Bit 29 - Group Channel 5 and Channel 1
Bit 30 - Group Channel 5 and Channel 2
Bit 31 - Group Channel 5 and Channel 3
impl W<u32, Reg<u32, _CCR6>>
Bits 0:15 - Capture/Compare value
impl W<u32, Reg<u32, _OR2>>
Bit 0 - BRK BKIN input enable
Bit 8 - BRK DFSDM_BREAK2 enable
Bit 9 - BRK BKIN input polarity
Bit 10 - BRK COMP1 input polarity
Bit 11 - BRK COMP2 input polarity
Bits 14:16 - ETR source selection
impl W<u32, Reg<u32, _OR3>>
Bit 0 - BRK2 BKIN input enable
Bit 1 - BRK2 COMP1 enable
Bit 2 - BRK2 COMP2 enable
Bit 8 - BRK2 DFSDM_BREAK3 enable
Bit 9 - BRK2 BKIN input polarity
Bit 10 - BRK2 COMP1 input polarity
Bit 11 - BRK2 COMP2 input polarity
impl W<u32, Reg<u32, _CR>>
Bit 19 - Clock security system enable
Bit 18 - HSE crystal oscillator bypass
Bit 16 - HSE clock enable
Bit 11 - HSI automatic start from Stop
Bit 9 - HSI always enable for peripheral kernels
Bits 4:7 - MSI clock ranges
Bit 3 - MSI clock range selection
Bit 2 - MSI clock PLL enable
impl W<u32, Reg<u32, _ICSCR>>
Bits 24:28 - HSI clock trimming
Bits 8:15 - MSI clock trimming
impl W<u32, Reg<u32, _CFGR>>
Bits 24:26 - Microcontroller clock output
Bit 15 - Wakeup from Stop and CSS backup clock selection
Bits 11:13 - APB high-speed prescaler (APB2)
Bits 8:10 - PB low-speed prescaler (APB1)
pub fn sw(&mut self) -> SW_W<'_>
Bits 0:1 - System clock switch
impl W<u32, Reg<u32, _PLLCFGR>>
Bits 25:26 - Main PLL division factor for PLLCLK (system clock)
Bit 24 - Main PLL PLLCLK output enable
Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)
Bit 20 - Main PLL PLLUSB1CLK output enable
Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
Bit 16 - Main PLL PLLSAI3CLK output enable
Bits 8:14 - Main PLL multiplication factor for VCO
Bits 4:6 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source
impl W<u32, Reg<u32, _PLLSAI1CFGR>>
Bits 25:26 - PLLSAI1 division factor for PLLADC1CLK (ADC clock)
Bit 24 - PLLSAI1 PLLADC1CLK output enable
Bits 21:22 - SAI1PLL division factor for PLLUSB2CLK (48 MHz clock)
Bit 20 - SAI1PLL PLLUSB2CLK output enable
Bit 17 - SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock)
Bit 16 - SAI1PLL PLLSAI1CLK output enable
Bits 8:14 - SAI1PLL multiplication factor for VCO
impl W<u32, Reg<u32, _PLLSAI2CFGR>>
Bits 25:26 - PLLSAI2 division factor for PLLADC2CLK (ADC clock)
Bit 24 - PLLSAI2 PLLADC2CLK output enable
Bit 17 - SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock)
Bit 16 - SAI2PLL PLLSAI2CLK output enable
Bits 8:14 - SAI2PLL multiplication factor for VCO
impl W<u32, Reg<u32, _CIER>>
Bit 9 - LSE clock security system interrupt enable
Bit 7 - PLLSAI2 ready interrupt enable
Bit 6 - PLLSAI1 ready interrupt enable
Bit 5 - PLL ready interrupt enable
Bit 4 - HSE ready interrupt enable
Bit 3 - HSI ready interrupt enable
Bit 2 - MSI ready interrupt enable
Bit 1 - LSE ready interrupt enable
Bit 0 - LSI ready interrupt enable
impl W<u32, Reg<u32, _CICR>>
Bit 9 - LSE Clock security system interrupt clear
Bit 8 - Clock security system interrupt clear
Bit 7 - PLLSAI2 ready interrupt clear
Bit 6 - PLLSAI1 ready interrupt clear
Bit 5 - PLL ready interrupt clear
Bit 4 - HSE ready interrupt clear
Bit 3 - HSI ready interrupt clear
Bit 2 - MSI ready interrupt clear
Bit 1 - LSE ready interrupt clear
Bit 0 - LSI ready interrupt clear
impl W<u32, Reg<u32, _AHB1RSTR>>
Bit 16 - Touch Sensing Controller reset
Bit 8 - Flash memory interface reset
impl W<u32, Reg<u32, _AHB2RSTR>>
Bit 18 - Random number generator reset
Bit 16 - AES hardware accelerator reset
Bit 12 - USB OTG FS reset
impl W<u32, Reg<u32, _AHB3RSTR>>
Bit 8 - Quad SPI memory interface reset
Bit 0 - Flexible memory controller reset
impl W<u32, Reg<u32, _APB1RSTR1>>
Bit 31 - Low Power Timer 1 reset
Bit 30 - OPAMP interface reset
Bit 29 - DAC1 interface reset
Bit 28 - Power interface reset
Bit 9 - LCD interface reset
impl W<u32, Reg<u32, _APB1RSTR2>>
Bit 5 - Low-power timer 2 reset
Bit 2 - Single wire protocol reset
Bit 0 - Low-power UART 1 reset
impl W<u32, Reg<u32, _APB2RSTR>>
Bit 24 - Digital filters for sigma-delata modulators (DFSDM) reset
Bit 22 - Serial audio interface 2 (SAI2) reset
Bit 21 - Serial audio interface 1 (SAI1) reset
Bit 18 - TIM17 timer reset
Bit 17 - TIM16 timer reset
Bit 16 - TIM15 timer reset
Bit 13 - TIM8 timer reset
Bit 11 - TIM1 timer reset
Bit 0 - System configuration (SYSCFG) reset
impl W<u32, Reg<u32, _AHB1ENR>>
Bit 16 - Touch Sensing Controller clock enable
Bit 11 - CRC clock enable
Bit 8 - Flash memory interface clock enable
Bit 1 - DMA2 clock enable
Bit 0 - DMA1 clock enable
impl W<u32, Reg<u32, _AHB2ENR>>
Bit 18 - Random Number Generator clock enable
Bit 16 - AES accelerator clock enable
Bit 13 - ADC clock enable
Bit 12 - OTG full speed clock enable
Bit 7 - IO port H clock enable
Bit 6 - IO port G clock enable
Bit 5 - IO port F clock enable
Bit 4 - IO port E clock enable
Bit 3 - IO port D clock enable
Bit 2 - IO port C clock enable
Bit 1 - IO port B clock enable
Bit 0 - IO port A clock enable
impl W<u32, Reg<u32, _AHB3ENR>>
Bit 0 - Flexible memory controller clock enable
impl W<u32, Reg<u32, _APB1ENR1>>
Bit 31 - Low power timer 1 clock enable
Bit 30 - OPAMP interface clock enable
Bit 29 - DAC1 interface clock enable
Bit 28 - Power interface clock enable
Bit 25 - CAN1 clock enable
Bit 23 - I2C3 clock enable
Bit 22 - I2C2 clock enable
Bit 21 - I2C1 clock enable
Bit 20 - UART5 clock enable
Bit 19 - UART4 clock enable
Bit 18 - USART3 clock enable
Bit 17 - USART2 clock enable
Bit 15 - SPI peripheral 3 clock enable
Bit 14 - SPI2 clock enable
Bit 11 - Window watchdog clock enable
Bit 5 - TIM7 timer clock enable
Bit 4 - TIM6 timer clock enable
Bit 3 - TIM5 timer clock enable
Bit 2 - TIM4 timer clock enable
Bit 1 - TIM3 timer clock enable
Bit 0 - TIM2 timer clock enable
Bit 10 - Enables the real time clock (RTC) peripheral
impl W<u32, Reg<u32, _APB1ENR2>>
Bit 2 - Single wire protocol clock enable
Bit 0 - Low power UART 1 clock enable
impl W<u32, Reg<u32, _APB2ENR>>
Bit 24 - DFSDM timer clock enable
Bit 22 - SAI2 clock enable
Bit 21 - SAI1 clock enable
Bit 18 - TIM17 timer clock enable
Bit 17 - TIM16 timer clock enable
Bit 16 - TIM15 timer clock enable
Bit 14 - USART1clock enable
Bit 13 - TIM8 timer clock enable
Bit 12 - SPI1 clock enable
Bit 11 - TIM1 timer clock enable
Bit 10 - SDMMC clock enable
Bit 7 - Firewall clock enable
Bit 0 - SYSCFG clock enable
impl W<u32, Reg<u32, _AHB1SMENR>>
Bit 16 - Touch Sensing Controller clocks enable during Sleep and Stop modes
Bit 9 - SRAM1 interface clocks enable during Sleep and Stop modes
Bit 8 - Flash memory interface clocks enable during Sleep and Stop modes
Bit 1 - DMA2 clocks enable during Sleep and Stop modes
Bit 0 - DMA1 clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _AHB2SMENR>>
Bit 18 - Random Number Generator clocks enable during Sleep and Stop modes
Bit 16 - AES accelerator clocks enable during Sleep and Stop modes
Bit 13 - ADC clocks enable during Sleep and Stop modes
Bit 12 - OTG full speed clocks enable during Sleep and Stop modes
Bit 9 - SRAM2 interface clocks enable during Sleep and Stop modes
Bit 7 - IO port H clocks enable during Sleep and Stop modes
Bit 6 - IO port G clocks enable during Sleep and Stop modes
Bit 5 - IO port F clocks enable during Sleep and Stop modes
Bit 4 - IO port E clocks enable during Sleep and Stop modes
Bit 3 - IO port D clocks enable during Sleep and Stop modes
Bit 2 - IO port C clocks enable during Sleep and Stop modes
Bit 1 - IO port B clocks enable during Sleep and Stop modes
Bit 0 - IO port A clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _AHB3SMENR>>
Bit 0 - Flexible memory controller clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _APB1SMENR1>>
Bit 31 - Low power timer 1 clocks enable during Sleep and Stop modes
Bit 30 - OPAMP interface clocks enable during Sleep and Stop modes
Bit 29 - DAC1 interface clocks enable during Sleep and Stop modes
Bit 28 - Power interface clocks enable during Sleep and Stop modes
Bit 25 - CAN1 clocks enable during Sleep and Stop modes
Bit 23 - I2C3 clocks enable during Sleep and Stop modes
Bit 22 - I2C2 clocks enable during Sleep and Stop modes
Bit 21 - I2C1 clocks enable during Sleep and Stop modes
Bit 20 - UART5 clocks enable during Sleep and Stop modes
Bit 19 - UART4 clocks enable during Sleep and Stop modes
Bit 18 - USART3 clocks enable during Sleep and Stop modes
Bit 17 - USART2 clocks enable during Sleep and Stop modes
Bit 15 - SPI3 clocks enable during Sleep and Stop modes
Bit 14 - SPI2 clocks enable during Sleep and Stop modes
Bit 11 - Window watchdog clocks enable during Sleep and Stop modes
Bit 9 - LCD clocks enable during Sleep and Stop modes
Bit 5 - TIM7 timer clocks enable during Sleep and Stop modes
Bit 4 - TIM6 timer clocks enable during Sleep and Stop modes
Bit 3 - TIM5 timer clocks enable during Sleep and Stop modes
Bit 2 - TIM4 timer clocks enable during Sleep and Stop modes
Bit 1 - TIM3 timer clocks enable during Sleep and Stop modes
Bit 0 - TIM2 timer clocks enable during Sleep and Stop modes
Bit 10 - RTC APB clock enable during Sleep and Stop modes
impl W<u32, Reg<u32, _APB1SMENR2>>
Bit 2 - Single wire protocol clocks enable during Sleep and Stop modes
Bit 0 - Low power UART 1 clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _APB2SMENR>>
Bit 24 - DFSDM timer clocks enable during Sleep and Stop modes
Bit 22 - SAI2 clocks enable during Sleep and Stop modes
Bit 21 - SAI1 clocks enable during Sleep and Stop modes
Bit 18 - TIM17 timer clocks enable during Sleep and Stop modes
Bit 17 - TIM16 timer clocks enable during Sleep and Stop modes
Bit 16 - TIM15 timer clocks enable during Sleep and Stop modes
Bit 14 - USART1clocks enable during Sleep and Stop modes
Bit 13 - TIM8 timer clocks enable during Sleep and Stop modes
Bit 12 - SPI1 clocks enable during Sleep and Stop modes
Bit 11 - TIM1 timer clocks enable during Sleep and Stop modes
Bit 10 - SDMMC clocks enable during Sleep and Stop modes
Bit 0 - SYSCFG clocks enable during Sleep and Stop modes
impl W<u32, Reg<u32, _CCIPR>>
Bit 31 - DFSDM clock source selection
Bit 30 - SWPMI1 clock source selection
Bits 28:29 - ADCs clock source selection
Bits 26:27 - 48 MHz clock source selection
Bits 24:25 - SAI2 clock source selection
Bits 22:23 - SAI1 clock source selection
Bits 20:21 - Low power timer 2 clock source selection
Bits 18:19 - Low power timer 1 clock source selection
Bits 16:17 - I2C3 clock source selection
Bits 14:15 - I2C2 clock source selection
Bits 12:13 - I2C1 clock source selection
Bits 10:11 - LPUART1 clock source selection
Bits 8:9 - UART5 clock source selection
Bits 6:7 - UART4 clock source selection
Bits 4:5 - USART3 clock source selection
Bits 2:3 - USART2 clock source selection
Bits 0:1 - USART1 clock source selection
impl W<u32, Reg<u32, _BDCR>>
Bit 25 - Low speed clock output selection
Bit 24 - Low speed clock output enable
Bit 16 - Backup domain software reset
Bit 15 - RTC clock enable
Bits 8:9 - RTC clock source selection
Bits 3:4 - SE oscillator drive capability
Bit 2 - LSE oscillator bypass
Bit 0 - LSE oscillator enable
impl W<u32, Reg<u32, _CSR>>
Bit 23 - Remove reset flag
Bits 8:11 - SI range after Standby mode
Bit 0 - LSI oscillator enable
impl W<u32, Reg<u32, _CRRCR>>
Bit 0 - Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.
impl W<u32, Reg<u32, _CCR>>
Bits 0:4 - Multi ADC mode selection
Bits 8:11 - Delay between 2 sampling phases
Bit 13 - DMA configuration (for multi-ADC mode)
Bits 14:15 - Direct memory access mode for multi ADC mode
Bits 16:17 - ADC clock mode
Bit 23 - CH18 selection (Vbat)
Bit 24 - CH17 selection (temperature)
impl W<u32, Reg<u32, _CR>>
Bit 2 - Debug Standby Mode
Bit 5 - Trace pin assignment control
Bits 6:7 - Trace pin assignment control
impl W<u32, Reg<u32, _APB1_FZR1>>
Bit 0 - Debug Timer 2 stopped when Core is halted
Bit 1 - TIM3 counter stopped when core is halted
Bit 2 - TIM4 counter stopped when core is halted
Bit 3 - TIM5 counter stopped when core is halted
Bit 4 - Debug Timer 6 stopped when Core is halted
Bit 5 - TIM7 counter stopped when core is halted
Bit 10 - Debug RTC stopped when Core is halted
Bit 11 - Debug Window Wachdog stopped when Core is halted
Bit 12 - Debug Independent Wachdog stopped when Core is halted
Bit 21 - I2C1 SMBUS timeout mode stopped when core is halted
Bit 22 - I2C2 SMBUS timeout mode stopped when core is halted
Bit 23 - I2C3 SMBUS timeout counter stopped when core is halted
Bit 25 - bxCAN stopped when core is halted
Bit 31 - LPTIM1 counter stopped when core is halted
impl W<u32, Reg<u32, _APB1_FZR2>>
Bit 5 - LPTIM2 counter stopped when core is halted
impl W<u32, Reg<u32, _APB2_FZR>>
Bit 11 - TIM1 counter stopped when core is halted
Bit 13 - TIM8 counter stopped when core is halted
Bit 16 - TIM15 counter stopped when core is halted
Bit 17 - TIM16 counter stopped when core is halted
Bit 18 - TIM17 counter stopped when core is halted
impl W<u32, Reg<u32, _FPCCR>>
impl W<u32, Reg<u32, _FPCAR>>
Bits 3:31 - Location of unpopulated floating-point
impl W<u32, Reg<u32, _FPSCR>>
Bit 0 - Invalid operation cumulative exception bit
Bit 1 - Division by zero cumulative exception bit.
Bit 2 - Overflow cumulative exception bit
Bit 3 - Underflow cumulative exception bit
Bit 4 - Inexact cumulative exception bit
Bit 7 - Input denormal cumulative exception bit.
Bits 22:23 - Rounding Mode control field
pub fn fz(&mut self) -> FZ_W<'_>
Bit 24 - Flush-to-zero mode control bit:
pub fn dn(&mut self) -> DN_W<'_>
Bit 25 - Default NaN mode control bit
Bit 26 - Alternative half-precision control bit
pub fn v(&mut self) -> V_W<'_>
Bit 28 - Overflow condition code flag
pub fn c(&mut self) -> C_W<'_>
Bit 29 - Carry condition code flag
pub fn z(&mut self) -> Z_W<'_>
Bit 30 - Zero condition code flag
pub fn n(&mut self) -> N_W<'_>
Bit 31 - Negative condition code flag
impl W<u32, Reg<u32, _CTRL>>
Bit 1 - SysTick exception request enable
Bit 2 - Clock source selection
impl W<u32, Reg<u32, _LOAD>>
impl W<u32, Reg<u32, _VAL>>
Bits 0:23 - Current counter value
impl W<u32, Reg<u32, _CALIB>>
Bits 0:23 - Calibration value
Bit 30 - SKEW flag: Indicates whether the TENMS value is exact
Bit 31 - NOREF flag. Reads as zero
impl W<u32, Reg<u32, _STIR>>
Bits 0:8 - Software generated interrupt ID
impl W<u32, Reg<u32, _CPACR>>
pub fn cp(&mut self) -> CP_W<'_>
impl W<u32, Reg<u32, _ACTRL>>
impl W<u32, Reg<u32, _CR1>>
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
impl W<u32, Reg<u32, _CR2>>
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 15 - Output compare 2 clear enable
Bits 12:14 - Output compare 2 mode
Bit 11 - Output compare 2 preload enable
Bit 10 - Output compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output compare 1 clear enable
Bits 4:6 - Output compare 1 mode
Bit 3 - Output compare 1 preload enable
Bit 2 - Output compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
Bit 15 - Capture/Compare 4 output Polarity
Bit 13 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 9 - Capture/Compare 3 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 16:31 - High counter value (TIM2 only)
Bits 0:15 - Counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 16:31 - High Auto-reload value (TIM2 only)
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _CCR>>
Bits 16:31 - High Capture/Compare 1 value (TIM2 only)
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR>>
Bits 0:2 - Timer2 ETR remap
Bits 3:4 - Internal trigger
impl W<u32, Reg<u32, _CR1>>
Bits 8:9 - Clock division
Bit 7 - Auto-reload preload enable
Bits 5:6 - Center-aligned mode selection
Bit 2 - Update request source
impl W<u32, Reg<u32, _CR2>>
Bits 4:6 - Master mode selection
Bit 3 - Capture/compare DMA selection
impl W<u32, Reg<u32, _SMCR>>
Bit 15 - External trigger polarity
Bit 14 - External clock enable
Bits 12:13 - External trigger prescaler
Bits 8:11 - External trigger filter
Bit 7 - Master/Slave mode
pub fn ts(&mut self) -> TS_W<'_>
Bits 4:6 - Trigger selection
Bits 0:2 - Slave mode selection
impl W<u32, Reg<u32, _DIER>>
Bit 14 - Trigger DMA request enable
Bit 13 - COM DMA request enable
Bit 12 - Capture/Compare 4 DMA request enable
Bit 11 - Capture/Compare 3 DMA request enable
Bit 10 - Capture/Compare 2 DMA request enable
Bit 9 - Capture/Compare 1 DMA request enable
Bit 8 - Update DMA request enable
Bit 6 - Trigger interrupt enable
Bit 4 - Capture/Compare 4 interrupt enable
Bit 3 - Capture/Compare 3 interrupt enable
Bit 2 - Capture/Compare 2 interrupt enable
Bit 1 - Capture/Compare 1 interrupt enable
Bit 0 - Update interrupt enable
impl W<u32, Reg<u32, _SR>>
Bit 12 - Capture/Compare 4 overcapture flag
Bit 11 - Capture/Compare 3 overcapture flag
Bit 10 - Capture/compare 2 overcapture flag
Bit 9 - Capture/Compare 1 overcapture flag
Bit 6 - Trigger interrupt flag
Bit 4 - Capture/Compare 4 interrupt flag
Bit 3 - Capture/Compare 3 interrupt flag
Bit 2 - Capture/Compare 2 interrupt flag
Bit 1 - Capture/compare 1 interrupt flag
Bit 0 - Update interrupt flag
impl W<u32, Reg<u32, _EGR>>
pub fn tg(&mut self) -> TG_W<'_>
Bit 6 - Trigger generation
Bit 4 - Capture/compare 4 generation
Bit 3 - Capture/compare 3 generation
Bit 2 - Capture/compare 2 generation
Bit 1 - Capture/compare 1 generation
pub fn ug(&mut self) -> UG_W<'_>
Bit 0 - Update generation
impl W<u32, Reg<u32, _CCMR1_OUTPUT>>
Bit 15 - Output compare 2 clear enable
Bits 12:14 - Output compare 2 mode
Bit 11 - Output compare 2 preload enable
Bit 10 - Output compare 2 fast enable
Bits 8:9 - Capture/Compare 2 selection
Bit 7 - Output compare 1 clear enable
Bits 4:6 - Output compare 1 mode
Bit 3 - Output compare 1 preload enable
Bit 2 - Output compare 1 fast enable
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR1_INPUT>>
Bits 12:15 - Input capture 2 filter
Bits 10:11 - Input capture 2 prescaler
Bits 8:9 - Capture/compare 2 selection
Bits 4:7 - Input capture 1 filter
Bits 2:3 - Input capture 1 prescaler
Bits 0:1 - Capture/Compare 1 selection
impl W<u32, Reg<u32, _CCMR2_OUTPUT>>
Bit 15 - Output compare 4 clear enable
Bits 12:14 - Output compare 4 mode
Bit 11 - Output compare 4 preload enable
Bit 10 - Output compare 4 fast enable
Bits 8:9 - Capture/Compare 4 selection
Bit 7 - Output compare 3 clear enable
Bits 4:6 - Output compare 3 mode
Bit 3 - Output compare 3 preload enable
Bit 2 - Output compare 3 fast enable
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCMR2_INPUT>>
Bits 12:15 - Input capture 4 filter
Bits 10:11 - Input capture 4 prescaler
Bits 8:9 - Capture/Compare 4 selection
Bits 4:7 - Input capture 3 filter
Bits 2:3 - Input capture 3 prescaler
Bits 0:1 - Capture/Compare 3 selection
impl W<u32, Reg<u32, _CCER>>
Bit 15 - Capture/Compare 4 output Polarity
Bit 13 - Capture/Compare 3 output Polarity
Bit 12 - Capture/Compare 4 output enable
Bit 11 - Capture/Compare 3 output Polarity
Bit 9 - Capture/Compare 3 output Polarity
Bit 8 - Capture/Compare 3 output enable
Bit 7 - Capture/Compare 2 output Polarity
Bit 5 - Capture/Compare 2 output Polarity
Bit 4 - Capture/Compare 2 output enable
Bit 3 - Capture/Compare 1 output Polarity
Bit 1 - Capture/Compare 1 output Polarity
Bit 0 - Capture/Compare 1 output enable
impl W<u32, Reg<u32, _CNT>>
Bits 16:31 - High counter value (TIM2 only)
Bits 0:15 - Counter value
impl W<u32, Reg<u32, _PSC>>
Bits 0:15 - Prescaler value
impl W<u32, Reg<u32, _ARR>>
Bits 16:31 - High Auto-reload value (TIM2 only)
Bits 0:15 - Auto-reload value
impl W<u32, Reg<u32, _CCR>>
Bits 16:31 - High Capture/Compare 1 value (TIM2 only)
Bits 0:15 - Capture/Compare 1 value
impl W<u32, Reg<u32, _DCR>>
Bits 8:12 - DMA burst length
Bits 0:4 - DMA base address
impl W<u32, Reg<u32, _DMAR>>
Bits 0:15 - DMA register for burst accesses
impl W<u32, Reg<u32, _OR>>
Bits 0:2 - Timer2 ETR remap
Bits 3:4 - Internal trigger
impl<T> Any for T where
T: 'static + ?Sized,
Immutably borrows from an owned value. Read more
Mutably borrows from an owned value. Read more
impl<T, U> Into<U> for T where
U: From<T>,
The type returned in the event of a conversion error.
The type returned in the event of a conversion error.