#[repr(u8)]pub enum OC4M_A {
Show 14 variants
FROZEN = 0,
ACTIVEONMATCH = 1,
INACTIVEONMATCH = 2,
TOGGLE = 3,
FORCEINACTIVE = 4,
FORCEACTIVE = 5,
PWMMODE1 = 6,
PWMMODE2 = 7,
OPMMODE1 = 8,
OPMMODE2 = 9,
COMBINEDPWMMODE1 = 12,
COMBINEDPWMMODE2 = 13,
ASYMMETRICPWMMODE1 = 14,
ASYMMETRICPWMMODE2 = 15,
}
Expand description
Output compare 4 mode
Value on reset: 0
Variants§
FROZEN = 0
0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
ACTIVEONMATCH = 1
1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
INACTIVEONMATCH = 2
2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
TOGGLE = 3
3: OCyREF toggles when TIMx_CNT=TIMx_CCRy
FORCEINACTIVE = 4
4: OCyREF is forced low
FORCEACTIVE = 5
5: OCyREF is forced high
PWMMODE1 = 6
6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
PWMMODE2 = 7
7: Inversely to PwmMode1
OPMMODE1 = 8
8: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
OPMMODE2 = 9
9: Inversely to OpmMode1
COMBINEDPWMMODE1 = 12
12: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
COMBINEDPWMMODE2 = 13
13: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
ASYMMETRICPWMMODE1 = 14
14: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
ASYMMETRICPWMMODE2 = 15
15: OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down