Enum stm32l4_stm32hal::stm32l4x5::tim8::cr2::MMS_A [−][src]
#[repr(u8)] pub enum MMS_A { RESET, ENABLE, UPDATE, COMPAREPULSE, COMPAREOC1, COMPAREOC2, COMPAREOC3, COMPAREOC4, }
Expand description
Master mode selection
Value on reset: 0
Variants
0: The UG bit from the TIMx_EGR register is used as trigger output
1: The counter enable signal, CNT_EN, is used as trigger output
2: The update event is selected as trigger output
3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: OC1REF signal is used as trigger output
5: OC2REF signal is used as trigger output
6: OC3REF signal is used as trigger output
7: OC4REF signal is used as trigger output