[−][src]Struct stm32l1::R
Register/field reader
Result of the read method of a register.
Also it can be used in the modify method
Methods
impl<U, T> R<U, T> where
U: Copy, [src]
U: Copy,
impl<FI> R<bool, FI>[src]
pub fn bit(&self) -> bool[src]
Value of the field as raw bits
pub fn bit_is_clear(&self) -> bool[src]
Returns true if the bit is clear (0)
pub fn bit_is_set(&self) -> bool[src]
Returns true if the bit is set (1)
impl R<u32, Reg<u32, _CR>>[src]
pub fn dmaouten(&self) -> DMAOUTEN_R[src]
Bit 12 - Enable DMA management of data output phase
pub fn dmainen(&self) -> DMAINEN_R[src]
Bit 11 - Enable DMA management of data input phase
pub fn errie(&self) -> ERRIE_R[src]
Bit 10 - Error interrupt enable
pub fn ccfie(&self) -> CCFIE_R[src]
Bit 9 - CCF flag interrupt enable
pub fn errc(&self) -> ERRC_R[src]
Bit 8 - Error clear
pub fn ccfc(&self) -> CCFC_R[src]
Bit 7 - Computation Complete Flag Clear
pub fn chmod(&self) -> CHMOD_R[src]
Bits 5:6 - AES chaining mode
pub fn mode(&self) -> MODE_R[src]
Bits 3:4 - AES operating mode
pub fn datatype(&self) -> DATATYPE_R[src]
Bits 1:2 - Data type selection
pub fn en(&self) -> EN_R[src]
Bit 0 - AES enable
impl R<u32, Reg<u32, _SR>>[src]
pub fn wrerr(&self) -> WRERR_R[src]
Bit 2 - Write error flag
pub fn rderr(&self) -> RDERR_R[src]
Bit 1 - Read error flag
pub fn ccf(&self) -> CCF_R[src]
Bit 0 - Computation complete flag
impl R<u32, Reg<u32, _DINR>>[src]
impl R<u32, Reg<u32, _DOUTR>>[src]
impl R<u32, Reg<u32, _KEYR0>>[src]
impl R<u32, Reg<u32, _KEYR1>>[src]
impl R<u32, Reg<u32, _KEYR2>>[src]
impl R<u32, Reg<u32, _KEYR3>>[src]
impl R<u32, Reg<u32, _IVR0>>[src]
impl R<u32, Reg<u32, _IVR1>>[src]
impl R<u32, Reg<u32, _IVR2>>[src]
impl R<u32, Reg<u32, _IVR3>>[src]
impl R<u32, Reg<u32, _CSR>>[src]
pub fn tsusp(&self) -> TSUSP_R[src]
Bit 31 - Suspend Timer Mode
pub fn caif(&self) -> CAIF_R[src]
Bit 30 - Channel acquisition interrupt flag
pub fn caie(&self) -> CAIE_R[src]
Bit 29 - Channel Acquisition Interrupt Enable / Clear
pub fn rch13(&self) -> RCH13_R[src]
Bit 28 - Select GPIO port PC3 as re-routed ADC input channel CH13.
pub fn fch8(&self) -> FCH8_R[src]
Bit 27 - Select GPIO port PB0 as fast ADC input channel CH8.
pub fn fch3(&self) -> FCH3_R[src]
Bit 26 - Select GPIO port PA3 as fast ADC input channel CH3.
pub fn outsel(&self) -> OUTSEL_R[src]
Bits 21:23 - Comparator 2 output selection
pub fn insel(&self) -> INSEL_R[src]
Bits 18:20 - Inverted input selection
pub fn wndwe(&self) -> WNDWE_R[src]
Bit 17 - Window mode enable
pub fn vrefouten(&self) -> VREFOUTEN_R[src]
Bit 16 - VREFINT output enable
pub fn cmp2out(&self) -> CMP2OUT_R[src]
Bit 13 - Comparator 2 output
pub fn speed(&self) -> SPEED_R[src]
Bit 12 - Comparator 2 speed mode
pub fn cmp1out(&self) -> CMP1OUT_R[src]
Bit 7 - Comparator 1 output
pub fn sw1(&self) -> SW1_R[src]
Bit 5 - SW1 analog switch enable
pub fn cmp1en(&self) -> CMP1EN_R[src]
Bit 4 - Comparator 1 enable
pub fn pd400k(&self) -> PD400K_R[src]
Bit 3 - 400 kO pull-down resistor
pub fn pd10k(&self) -> PD10K_R[src]
Bit 2 - 10 kO pull-down resistor
pub fn pu400k(&self) -> PU400K_R[src]
Bit 1 - 400 kO pull-up resistor
pub fn pu10k(&self) -> PU10K_R[src]
Bit 0 - 10 kO pull-up resistor
impl R<u32, Reg<u32, _DR>>[src]
impl R<u32, Reg<u32, _IDR>>[src]
impl R<bool, DMAUDRIE2_A>[src]
pub fn variant(&self) -> DMAUDRIE2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, DMAEN2_A>[src]
pub fn variant(&self) -> DMAEN2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, WAVE2_A>[src]
pub fn variant(&self) -> Variant<u8, WAVE2_A>[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_noise(&self) -> bool[src]
Checks if the value of the field is NOISE
pub fn is_triangle(&self) -> bool[src]
Checks if the value of the field is TRIANGLE
impl R<u8, TSEL2_A>[src]
pub fn variant(&self) -> TSEL2_A[src]
Get enumerated values variant
pub fn is_tim6_trgo(&self) -> bool[src]
Checks if the value of the field is TIM6_TRGO
pub fn is_tim8_trgo(&self) -> bool[src]
Checks if the value of the field is TIM8_TRGO
pub fn is_tim7_trgo(&self) -> bool[src]
Checks if the value of the field is TIM7_TRGO
pub fn is_tim5_trgo(&self) -> bool[src]
Checks if the value of the field is TIM5_TRGO
pub fn is_tim2_trgo(&self) -> bool[src]
Checks if the value of the field is TIM2_TRGO
pub fn is_tim4_trgo(&self) -> bool[src]
Checks if the value of the field is TIM4_TRGO
pub fn is_exti9(&self) -> bool[src]
Checks if the value of the field is EXTI9
pub fn is_software(&self) -> bool[src]
Checks if the value of the field is SOFTWARE
impl R<bool, TEN2_A>[src]
pub fn variant(&self) -> TEN2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, BOFF2_A>[src]
pub fn variant(&self) -> BOFF2_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, EN2_A>[src]
pub fn variant(&self) -> EN2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, WAVE1_A>[src]
pub fn variant(&self) -> Variant<u8, WAVE1_A>[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_noise(&self) -> bool[src]
Checks if the value of the field is NOISE
pub fn is_triangle(&self) -> bool[src]
Checks if the value of the field is TRIANGLE
impl R<u8, TSEL1_A>[src]
pub fn variant(&self) -> Variant<u8, TSEL1_A>[src]
Get enumerated values variant
pub fn is_tim6_trgo(&self) -> bool[src]
Checks if the value of the field is TIM6_TRGO
pub fn is_tim3_trgo(&self) -> bool[src]
Checks if the value of the field is TIM3_TRGO
pub fn is_tim7_trgo(&self) -> bool[src]
Checks if the value of the field is TIM7_TRGO
pub fn is_tim15_trgo(&self) -> bool[src]
Checks if the value of the field is TIM15_TRGO
pub fn is_tim2_trgo(&self) -> bool[src]
Checks if the value of the field is TIM2_TRGO
pub fn is_exti9(&self) -> bool[src]
Checks if the value of the field is EXTI9
pub fn is_software(&self) -> bool[src]
Checks if the value of the field is SOFTWARE
impl R<u32, Reg<u32, _CR>>[src]
pub fn dmaudrie2(&self) -> DMAUDRIE2_R[src]
Bit 29 - DAC channel2 DMA underrun interrupt enable
pub fn dmaen2(&self) -> DMAEN2_R[src]
Bit 28 - DAC channel2 DMA enable
pub fn mamp2(&self) -> MAMP2_R[src]
Bits 24:27 - DAC channel2 mask/amplitude selector
pub fn wave2(&self) -> WAVE2_R[src]
Bits 22:23 - DAC channel2 noise/triangle wave generation enable
pub fn tsel2(&self) -> TSEL2_R[src]
Bits 19:21 - DAC channel2 trigger selection
pub fn ten2(&self) -> TEN2_R[src]
Bit 18 - DAC channel2 trigger enable
pub fn boff2(&self) -> BOFF2_R[src]
Bit 17 - DAC channel2 output buffer disable
pub fn en2(&self) -> EN2_R[src]
Bit 16 - DAC channel2 enable
pub fn dmaudrie1(&self) -> DMAUDRIE1_R[src]
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
pub fn dmaen1(&self) -> DMAEN1_R[src]
Bit 12 - DAC channel1 DMA enable
pub fn mamp1(&self) -> MAMP1_R[src]
Bits 8:11 - DAC channel1 mask/amplitude selector
pub fn wave1(&self) -> WAVE1_R[src]
Bits 6:7 - DAC channel1 noise/triangle wave generation enable
pub fn tsel1(&self) -> TSEL1_R[src]
Bits 3:5 - DAC channel1 trigger selection
pub fn ten1(&self) -> TEN1_R[src]
Bit 2 - DAC channel1 trigger enable
pub fn boff1(&self) -> BOFF1_R[src]
Bit 1 - DAC channel1 output buffer disable
pub fn en1(&self) -> EN1_R[src]
Bit 0 - DAC channel1 enable
impl R<u32, Reg<u32, _DHR12R1>>[src]
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
impl R<u32, Reg<u32, _DHR12L1>>[src]
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
impl R<u32, Reg<u32, _DHR8R1>>[src]
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl R<u32, Reg<u32, _DHR12R2>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 0:11 - DAC channel2 12-bit right-aligned data
impl R<u32, Reg<u32, _DHR12L2>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 4:15 - DAC channel2 12-bit left-aligned data
impl R<u32, Reg<u32, _DHR8R2>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 0:7 - DAC channel2 8-bit right-aligned data
impl R<u32, Reg<u32, _DHR12RD>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 16:27 - DAC channel2 12-bit right-aligned data
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
impl R<u32, Reg<u32, _DHR12LD>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 20:31 - DAC channel2 12-bit left-aligned data
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
impl R<u32, Reg<u32, _DHR8RD>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 8:15 - DAC channel2 8-bit right-aligned data
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl R<u32, Reg<u32, _DOR1>>[src]
pub fn dacc1dor(&self) -> DACC1DOR_R[src]
Bits 0:11 - DAC channel1 data output
impl R<u32, Reg<u32, _DOR2>>[src]
pub fn dacc2dor(&self) -> DACC2DOR_R[src]
Bits 0:11 - DAC channel2 data output
impl R<bool, DMAUDR2_A>[src]
pub fn variant(&self) -> DMAUDR2_A[src]
Get enumerated values variant
pub fn is_no_underrun(&self) -> bool[src]
Checks if the value of the field is NOUNDERRUN
pub fn is_underrun(&self) -> bool[src]
Checks if the value of the field is UNDERRUN
impl R<u32, Reg<u32, _SR>>[src]
pub fn dmaudr2(&self) -> DMAUDR2_R[src]
Bit 29 - DAC channel2 DMA underrun flag
pub fn dmaudr1(&self) -> DMAUDR1_R[src]
Bit 13 - DAC channel1 DMA underrun flag
impl R<u32, Reg<u32, _ISR>>[src]
pub fn teif7(&self) -> TEIF7_R[src]
Bit 27 - Channel x transfer error flag (x = 1 ..7)
pub fn htif7(&self) -> HTIF7_R[src]
Bit 26 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif7(&self) -> TCIF7_R[src]
Bit 25 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif7(&self) -> GIF7_R[src]
Bit 24 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif6(&self) -> TEIF6_R[src]
Bit 23 - Channel x transfer error flag (x = 1 ..7)
pub fn htif6(&self) -> HTIF6_R[src]
Bit 22 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif6(&self) -> TCIF6_R[src]
Bit 21 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif6(&self) -> GIF6_R[src]
Bit 20 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif5(&self) -> TEIF5_R[src]
Bit 19 - Channel x transfer error flag (x = 1 ..7)
pub fn htif5(&self) -> HTIF5_R[src]
Bit 18 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif5(&self) -> TCIF5_R[src]
Bit 17 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif5(&self) -> GIF5_R[src]
Bit 16 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif4(&self) -> TEIF4_R[src]
Bit 15 - Channel x transfer error flag (x = 1 ..7)
pub fn htif4(&self) -> HTIF4_R[src]
Bit 14 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif4(&self) -> TCIF4_R[src]
Bit 13 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif4(&self) -> GIF4_R[src]
Bit 12 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif3(&self) -> TEIF3_R[src]
Bit 11 - Channel x transfer error flag (x = 1 ..7)
pub fn htif3(&self) -> HTIF3_R[src]
Bit 10 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif3(&self) -> TCIF3_R[src]
Bit 9 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif3(&self) -> GIF3_R[src]
Bit 8 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif2(&self) -> TEIF2_R[src]
Bit 7 - Channel x transfer error flag (x = 1 ..7)
pub fn htif2(&self) -> HTIF2_R[src]
Bit 6 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif2(&self) -> TCIF2_R[src]
Bit 5 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif2(&self) -> GIF2_R[src]
Bit 4 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif1(&self) -> TEIF1_R[src]
Bit 3 - Channel x transfer error flag (x = 1 ..7)
pub fn htif1(&self) -> HTIF1_R[src]
Bit 2 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif1(&self) -> TCIF1_R[src]
Bit 1 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif1(&self) -> GIF1_R[src]
Bit 0 - Channel x global interrupt flag (x = 1 ..7)
impl R<u32, Reg<u32, _CCR1>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR1>>[src]
impl R<u32, Reg<u32, _CPAR1>>[src]
impl R<u32, Reg<u32, _CMAR1>>[src]
impl R<u32, Reg<u32, _CCR2>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR2>>[src]
impl R<u32, Reg<u32, _CPAR2>>[src]
impl R<u32, Reg<u32, _CMAR2>>[src]
impl R<u32, Reg<u32, _CCR3>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR3>>[src]
impl R<u32, Reg<u32, _CPAR3>>[src]
impl R<u32, Reg<u32, _CMAR3>>[src]
impl R<u32, Reg<u32, _CCR4>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR4>>[src]
impl R<u32, Reg<u32, _CPAR4>>[src]
impl R<u32, Reg<u32, _CMAR4>>[src]
impl R<u32, Reg<u32, _CCR5>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR5>>[src]
impl R<u32, Reg<u32, _CPAR5>>[src]
impl R<u32, Reg<u32, _CMAR5>>[src]
impl R<u32, Reg<u32, _CCR6>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR6>>[src]
impl R<u32, Reg<u32, _CPAR6>>[src]
impl R<u32, Reg<u32, _CMAR6>>[src]
impl R<u32, Reg<u32, _CCR7>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR7>>[src]
impl R<u32, Reg<u32, _CPAR7>>[src]
impl R<u32, Reg<u32, _CMAR7>>[src]
impl R<bool, MR0_A>[src]
pub fn variant(&self) -> MR0_A[src]
Get enumerated values variant
pub fn is_masked(&self) -> bool[src]
Checks if the value of the field is MASKED
pub fn is_unmasked(&self) -> bool[src]
Checks if the value of the field is UNMASKED
impl R<u32, Reg<u32, _IMR>>[src]
pub fn mr0(&self) -> MR0_R[src]
Bit 0 - Interrupt mask on line x
pub fn mr1(&self) -> MR1_R[src]
Bit 1 - Interrupt mask on line x
pub fn mr2(&self) -> MR2_R[src]
Bit 2 - Interrupt mask on line x
pub fn mr3(&self) -> MR3_R[src]
Bit 3 - Interrupt mask on line x
pub fn mr4(&self) -> MR4_R[src]
Bit 4 - Interrupt mask on line x
pub fn mr5(&self) -> MR5_R[src]
Bit 5 - Interrupt mask on line x
pub fn mr6(&self) -> MR6_R[src]
Bit 6 - Interrupt mask on line x
pub fn mr7(&self) -> MR7_R[src]
Bit 7 - Interrupt mask on line x
pub fn mr8(&self) -> MR8_R[src]
Bit 8 - Interrupt mask on line x
pub fn mr9(&self) -> MR9_R[src]
Bit 9 - Interrupt mask on line x
pub fn mr10(&self) -> MR10_R[src]
Bit 10 - Interrupt mask on line x
pub fn mr11(&self) -> MR11_R[src]
Bit 11 - Interrupt mask on line x
pub fn mr12(&self) -> MR12_R[src]
Bit 12 - Interrupt mask on line x
pub fn mr13(&self) -> MR13_R[src]
Bit 13 - Interrupt mask on line x
pub fn mr14(&self) -> MR14_R[src]
Bit 14 - Interrupt mask on line x
pub fn mr15(&self) -> MR15_R[src]
Bit 15 - Interrupt mask on line x
pub fn mr16(&self) -> MR16_R[src]
Bit 16 - Interrupt mask on line x
pub fn mr17(&self) -> MR17_R[src]
Bit 17 - Interrupt mask on line x
pub fn mr18(&self) -> MR18_R[src]
Bit 18 - Interrupt mask on line x
pub fn mr19(&self) -> MR19_R[src]
Bit 19 - Interrupt mask on line x
pub fn mr20(&self) -> MR20_R[src]
Bit 20 - Interrupt mask on line x
pub fn mr21(&self) -> MR21_R[src]
Bit 21 - Interrupt mask on line x
pub fn mr22(&self) -> MR22_R[src]
Bit 22 - Interrupt mask on line x
impl R<bool, MR0_A>[src]
pub fn variant(&self) -> MR0_A[src]
Get enumerated values variant
pub fn is_masked(&self) -> bool[src]
Checks if the value of the field is MASKED
pub fn is_unmasked(&self) -> bool[src]
Checks if the value of the field is UNMASKED
impl R<u32, Reg<u32, _EMR>>[src]
pub fn mr0(&self) -> MR0_R[src]
Bit 0 - Event mask on line x
pub fn mr1(&self) -> MR1_R[src]
Bit 1 - Event mask on line x
pub fn mr2(&self) -> MR2_R[src]
Bit 2 - Event mask on line x
pub fn mr3(&self) -> MR3_R[src]
Bit 3 - Event mask on line x
pub fn mr4(&self) -> MR4_R[src]
Bit 4 - Event mask on line x
pub fn mr5(&self) -> MR5_R[src]
Bit 5 - Event mask on line x
pub fn mr6(&self) -> MR6_R[src]
Bit 6 - Event mask on line x
pub fn mr7(&self) -> MR7_R[src]
Bit 7 - Event mask on line x
pub fn mr8(&self) -> MR8_R[src]
Bit 8 - Event mask on line x
pub fn mr9(&self) -> MR9_R[src]
Bit 9 - Event mask on line x
pub fn mr10(&self) -> MR10_R[src]
Bit 10 - Event mask on line x
pub fn mr11(&self) -> MR11_R[src]
Bit 11 - Event mask on line x
pub fn mr12(&self) -> MR12_R[src]
Bit 12 - Event mask on line x
pub fn mr13(&self) -> MR13_R[src]
Bit 13 - Event mask on line x
pub fn mr14(&self) -> MR14_R[src]
Bit 14 - Event mask on line x
pub fn mr15(&self) -> MR15_R[src]
Bit 15 - Event mask on line x
pub fn mr16(&self) -> MR16_R[src]
Bit 16 - Event mask on line x
pub fn mr17(&self) -> MR17_R[src]
Bit 17 - Event mask on line x
pub fn mr18(&self) -> MR18_R[src]
Bit 18 - Event mask on line x
pub fn mr19(&self) -> MR19_R[src]
Bit 19 - Event mask on line x
pub fn mr20(&self) -> MR20_R[src]
Bit 20 - Event mask on line x
pub fn mr21(&self) -> MR21_R[src]
Bit 21 - Event mask on line x
pub fn mr22(&self) -> MR22_R[src]
Bit 22 - Event mask on line x
impl R<bool, TR0_A>[src]
pub fn variant(&self) -> TR0_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _RTSR>>[src]
pub fn tr0(&self) -> TR0_R[src]
Bit 0 - Rising edge trigger event configuration bit of line x
pub fn tr1(&self) -> TR1_R[src]
Bit 1 - Rising edge trigger event configuration bit of line x
pub fn tr2(&self) -> TR2_R[src]
Bit 2 - Rising edge trigger event configuration bit of line x
pub fn tr3(&self) -> TR3_R[src]
Bit 3 - Rising edge trigger event configuration bit of line x
pub fn tr4(&self) -> TR4_R[src]
Bit 4 - Rising edge trigger event configuration bit of line x
pub fn tr5(&self) -> TR5_R[src]
Bit 5 - Rising edge trigger event configuration bit of line x
pub fn tr6(&self) -> TR6_R[src]
Bit 6 - Rising edge trigger event configuration bit of line x
pub fn tr7(&self) -> TR7_R[src]
Bit 7 - Rising edge trigger event configuration bit of line x
pub fn tr8(&self) -> TR8_R[src]
Bit 8 - Rising edge trigger event configuration bit of line x
pub fn tr9(&self) -> TR9_R[src]
Bit 9 - Rising edge trigger event configuration bit of line x
pub fn tr10(&self) -> TR10_R[src]
Bit 10 - Rising edge trigger event configuration bit of line x
pub fn tr11(&self) -> TR11_R[src]
Bit 11 - Rising edge trigger event configuration bit of line x
pub fn tr12(&self) -> TR12_R[src]
Bit 12 - Rising edge trigger event configuration bit of line x
pub fn tr13(&self) -> TR13_R[src]
Bit 13 - Rising edge trigger event configuration bit of line x
pub fn tr14(&self) -> TR14_R[src]
Bit 14 - Rising edge trigger event configuration bit of line x
pub fn tr15(&self) -> TR15_R[src]
Bit 15 - Rising edge trigger event configuration bit of line x
pub fn tr16(&self) -> TR16_R[src]
Bit 16 - Rising edge trigger event configuration bit of line x
pub fn tr17(&self) -> TR17_R[src]
Bit 17 - Rising edge trigger event configuration bit of line x
pub fn tr18(&self) -> TR18_R[src]
Bit 18 - Rising edge trigger event configuration bit of line x
pub fn tr19(&self) -> TR19_R[src]
Bit 19 - Rising edge trigger event configuration bit of line x
pub fn tr20(&self) -> TR20_R[src]
Bit 20 - Rising edge trigger event configuration bit of line x
pub fn tr21(&self) -> TR21_R[src]
Bit 21 - Rising edge trigger event configuration bit of line x
pub fn tr22(&self) -> TR22_R[src]
Bit 22 - Rising edge trigger event configuration bit of line x
impl R<bool, TR0_A>[src]
pub fn variant(&self) -> TR0_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _FTSR>>[src]
pub fn tr0(&self) -> TR0_R[src]
Bit 0 - Falling edge trigger event configuration bit of line x
pub fn tr1(&self) -> TR1_R[src]
Bit 1 - Falling edge trigger event configuration bit of line x
pub fn tr2(&self) -> TR2_R[src]
Bit 2 - Falling edge trigger event configuration bit of line x
pub fn tr3(&self) -> TR3_R[src]
Bit 3 - Falling edge trigger event configuration bit of line x
pub fn tr4(&self) -> TR4_R[src]
Bit 4 - Falling edge trigger event configuration bit of line x
pub fn tr5(&self) -> TR5_R[src]
Bit 5 - Falling edge trigger event configuration bit of line x
pub fn tr6(&self) -> TR6_R[src]
Bit 6 - Falling edge trigger event configuration bit of line x
pub fn tr7(&self) -> TR7_R[src]
Bit 7 - Falling edge trigger event configuration bit of line x
pub fn tr8(&self) -> TR8_R[src]
Bit 8 - Falling edge trigger event configuration bit of line x
pub fn tr9(&self) -> TR9_R[src]
Bit 9 - Falling edge trigger event configuration bit of line x
pub fn tr10(&self) -> TR10_R[src]
Bit 10 - Falling edge trigger event configuration bit of line x
pub fn tr11(&self) -> TR11_R[src]
Bit 11 - Falling edge trigger event configuration bit of line x
pub fn tr12(&self) -> TR12_R[src]
Bit 12 - Falling edge trigger event configuration bit of line x
pub fn tr13(&self) -> TR13_R[src]
Bit 13 - Falling edge trigger event configuration bit of line x
pub fn tr14(&self) -> TR14_R[src]
Bit 14 - Falling edge trigger event configuration bit of line x
pub fn tr15(&self) -> TR15_R[src]
Bit 15 - Falling edge trigger event configuration bit of line x
pub fn tr16(&self) -> TR16_R[src]
Bit 16 - Falling edge trigger event configuration bit of line x
pub fn tr17(&self) -> TR17_R[src]
Bit 17 - Falling edge trigger event configuration bit of line x
pub fn tr18(&self) -> TR18_R[src]
Bit 18 - Falling edge trigger event configuration bit of line x
pub fn tr19(&self) -> TR19_R[src]
Bit 19 - Falling edge trigger event configuration bit of line x
pub fn tr20(&self) -> TR20_R[src]
Bit 20 - Falling edge trigger event configuration bit of line x
pub fn tr21(&self) -> TR21_R[src]
Bit 21 - Falling edge trigger event configuration bit of line x
pub fn tr22(&self) -> TR22_R[src]
Bit 22 - Falling edge trigger event configuration bit of line x
impl R<bool, SWIER0_A>[src]
pub fn variant(&self) -> Variant<bool, SWIER0_A>[src]
Get enumerated values variant
pub fn is_pend(&self) -> bool[src]
Checks if the value of the field is PEND
impl R<u32, Reg<u32, _SWIER>>[src]
pub fn swier0(&self) -> SWIER0_R[src]
Bit 0 - Software interrupt on line x
pub fn swier1(&self) -> SWIER1_R[src]
Bit 1 - Software interrupt on line x
pub fn swier2(&self) -> SWIER2_R[src]
Bit 2 - Software interrupt on line x
pub fn swier3(&self) -> SWIER3_R[src]
Bit 3 - Software interrupt on line x
pub fn swier4(&self) -> SWIER4_R[src]
Bit 4 - Software interrupt on line x
pub fn swier5(&self) -> SWIER5_R[src]
Bit 5 - Software interrupt on line x
pub fn swier6(&self) -> SWIER6_R[src]
Bit 6 - Software interrupt on line x
pub fn swier7(&self) -> SWIER7_R[src]
Bit 7 - Software interrupt on line x
pub fn swier8(&self) -> SWIER8_R[src]
Bit 8 - Software interrupt on line x
pub fn swier9(&self) -> SWIER9_R[src]
Bit 9 - Software interrupt on line x
pub fn swier10(&self) -> SWIER10_R[src]
Bit 10 - Software interrupt on line x
pub fn swier11(&self) -> SWIER11_R[src]
Bit 11 - Software interrupt on line x
pub fn swier12(&self) -> SWIER12_R[src]
Bit 12 - Software interrupt on line x
pub fn swier13(&self) -> SWIER13_R[src]
Bit 13 - Software interrupt on line x
pub fn swier14(&self) -> SWIER14_R[src]
Bit 14 - Software interrupt on line x
pub fn swier15(&self) -> SWIER15_R[src]
Bit 15 - Software interrupt on line x
pub fn swier16(&self) -> SWIER16_R[src]
Bit 16 - Software interrupt on line x
pub fn swier17(&self) -> SWIER17_R[src]
Bit 17 - Software interrupt on line x
pub fn swier18(&self) -> SWIER18_R[src]
Bit 18 - Software interrupt on line x
pub fn swier19(&self) -> SWIER19_R[src]
Bit 19 - Software interrupt on line x
pub fn swier20(&self) -> SWIER20_R[src]
Bit 20 - Software interrupt on line x
pub fn swier21(&self) -> SWIER21_R[src]
Bit 21 - Software interrupt on line x
pub fn swier22(&self) -> SWIER22_R[src]
Bit 22 - Software interrupt on line x
impl R<bool, PR0_A>[src]
pub fn variant(&self) -> PR0_A[src]
Get enumerated values variant
pub fn is_not_pending(&self) -> bool[src]
Checks if the value of the field is NOTPENDING
pub fn is_pending(&self) -> bool[src]
Checks if the value of the field is PENDING
impl R<u32, Reg<u32, _PR>>[src]
pub fn pr0(&self) -> PR0_R[src]
Bit 0 - Pending bit
pub fn pr1(&self) -> PR1_R[src]
Bit 1 - Pending bit
pub fn pr2(&self) -> PR2_R[src]
Bit 2 - Pending bit
pub fn pr3(&self) -> PR3_R[src]
Bit 3 - Pending bit
pub fn pr4(&self) -> PR4_R[src]
Bit 4 - Pending bit
pub fn pr5(&self) -> PR5_R[src]
Bit 5 - Pending bit
pub fn pr6(&self) -> PR6_R[src]
Bit 6 - Pending bit
pub fn pr7(&self) -> PR7_R[src]
Bit 7 - Pending bit
pub fn pr8(&self) -> PR8_R[src]
Bit 8 - Pending bit
pub fn pr9(&self) -> PR9_R[src]
Bit 9 - Pending bit
pub fn pr10(&self) -> PR10_R[src]
Bit 10 - Pending bit
pub fn pr11(&self) -> PR11_R[src]
Bit 11 - Pending bit
pub fn pr12(&self) -> PR12_R[src]
Bit 12 - Pending bit
pub fn pr13(&self) -> PR13_R[src]
Bit 13 - Pending bit
pub fn pr14(&self) -> PR14_R[src]
Bit 14 - Pending bit
pub fn pr15(&self) -> PR15_R[src]
Bit 15 - Pending bit
pub fn pr16(&self) -> PR16_R[src]
Bit 16 - Pending bit
pub fn pr17(&self) -> PR17_R[src]
Bit 17 - Pending bit
pub fn pr18(&self) -> PR18_R[src]
Bit 18 - Pending bit
pub fn pr19(&self) -> PR19_R[src]
Bit 19 - Pending bit
pub fn pr20(&self) -> PR20_R[src]
Bit 20 - Pending bit
pub fn pr21(&self) -> PR21_R[src]
Bit 21 - Pending bit
pub fn pr22(&self) -> PR22_R[src]
Bit 22 - Pending bit
impl R<u32, Reg<u32, _ACR>>[src]
pub fn latency(&self) -> LATENCY_R[src]
Bit 0 - Latency
pub fn prften(&self) -> PRFTEN_R[src]
Bit 1 - Prefetch enable
pub fn acc64(&self) -> ACC64_R[src]
Bit 2 - 64-bit access
pub fn sleep_pd(&self) -> SLEEP_PD_R[src]
Bit 3 - Flash mode during Sleep
pub fn run_pd(&self) -> RUN_PD_R[src]
Bit 4 - Flash mode during Run
impl R<u32, Reg<u32, _PECR>>[src]
pub fn pelock(&self) -> PELOCK_R[src]
Bit 0 - FLASH_PECR and data EEPROM lock
pub fn prglock(&self) -> PRGLOCK_R[src]
Bit 1 - Program memory lock
pub fn optlock(&self) -> OPTLOCK_R[src]
Bit 2 - Option bytes block lock
pub fn prog(&self) -> PROG_R[src]
Bit 3 - Program memory selection
pub fn data(&self) -> DATA_R[src]
Bit 4 - Data EEPROM selection
pub fn ftdw(&self) -> FTDW_R[src]
Bit 8 - Fixed time data write for Byte, Half Word and Word programming
pub fn erase(&self) -> ERASE_R[src]
Bit 9 - Page or Double Word erase mode
pub fn fprg(&self) -> FPRG_R[src]
Bit 10 - Half Page/Double Word programming mode
pub fn parallelbank(&self) -> PARALLELBANK_R[src]
Bit 15 - Parallel bank mode
pub fn eopie(&self) -> EOPIE_R[src]
Bit 16 - End of programming interrupt enable
pub fn errie(&self) -> ERRIE_R[src]
Bit 17 - Error interrupt enable
pub fn obl_launch(&self) -> OBL_LAUNCH_R[src]
Bit 18 - Launch the option byte loading
impl R<u32, Reg<u32, _SR>>[src]
pub fn bsy(&self) -> BSY_R[src]
Bit 0 - Write/erase operations in progress
pub fn eop(&self) -> EOP_R[src]
Bit 1 - End of operation
pub fn endhv(&self) -> ENDHV_R[src]
Bit 2 - End of high voltage
pub fn ready(&self) -> READY_R[src]
Bit 3 - Flash memory module ready after low power mode
pub fn wrperr(&self) -> WRPERR_R[src]
Bit 8 - Write protected error
pub fn pgaerr(&self) -> PGAERR_R[src]
Bit 9 - Programming alignment error
pub fn sizerr(&self) -> SIZERR_R[src]
Bit 10 - Size error
pub fn optverr(&self) -> OPTVERR_R[src]
Bit 11 - Option validity error
pub fn optverrusr(&self) -> OPTVERRUSR_R[src]
Bit 12 - Option UserValidity Error
impl R<u32, Reg<u32, _OBR>>[src]
pub fn rdprt(&self) -> RDPRT_R[src]
Bits 0:7 - Read protection
pub fn bor_lev(&self) -> BOR_LEV_R[src]
Bits 16:19 - BOR_LEV
pub fn iwdg_sw(&self) -> IWDG_SW_R[src]
Bit 20 - IWDG_SW
pub fn n_rts_stop(&self) -> NRTS_STOP_R[src]
Bit 21 - nRTS_STOP
pub fn n_rst_stdby(&self) -> NRST_STDBY_R[src]
Bit 22 - nRST_STDBY
pub fn bfb2(&self) -> BFB2_R[src]
Bit 23 - Boot From Bank 2
impl R<u32, Reg<u32, _WRPR1>>[src]
impl R<u32, Reg<u32, _WRPR2>>[src]
impl R<u32, Reg<u32, _WRPR3>>[src]
impl R<bool, CBURSTRW_A>[src]
pub fn variant(&self) -> CBURSTRW_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, ASYNCWAIT_A>[src]
pub fn variant(&self) -> ASYNCWAIT_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, EXTMOD_A>[src]
pub fn variant(&self) -> EXTMOD_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITEN_A>[src]
pub fn variant(&self) -> WAITEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WREN_A>[src]
pub fn variant(&self) -> WREN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITCFG_A>[src]
pub fn variant(&self) -> WAITCFG_A[src]
Get enumerated values variant
pub fn is_before_wait_state(&self) -> bool[src]
Checks if the value of the field is BEFOREWAITSTATE
pub fn is_during_wait_state(&self) -> bool[src]
Checks if the value of the field is DURINGWAITSTATE
impl R<bool, WAITPOL_A>[src]
pub fn variant(&self) -> WAITPOL_A[src]
Get enumerated values variant
pub fn is_active_low(&self) -> bool[src]
Checks if the value of the field is ACTIVELOW
pub fn is_active_high(&self) -> bool[src]
Checks if the value of the field is ACTIVEHIGH
impl R<bool, BURSTEN_A>[src]
pub fn variant(&self) -> BURSTEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, FACCEN_A>[src]
pub fn variant(&self) -> FACCEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, MWID_A>[src]
pub fn variant(&self) -> Variant<u8, MWID_A>[src]
Get enumerated values variant
pub fn is_bits8(&self) -> bool[src]
Checks if the value of the field is BITS8
pub fn is_bits16(&self) -> bool[src]
Checks if the value of the field is BITS16
pub fn is_bits32(&self) -> bool[src]
Checks if the value of the field is BITS32
impl R<u8, MTYP_A>[src]
pub fn variant(&self) -> Variant<u8, MTYP_A>[src]
Get enumerated values variant
pub fn is_sram(&self) -> bool[src]
Checks if the value of the field is SRAM
pub fn is_psram(&self) -> bool[src]
Checks if the value of the field is PSRAM
pub fn is_flash(&self) -> bool[src]
Checks if the value of the field is FLASH
impl R<bool, MUXEN_A>[src]
pub fn variant(&self) -> MUXEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, MBKEN_A>[src]
pub fn variant(&self) -> MBKEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CPSIZE_A>[src]
pub fn variant(&self) -> Variant<u8, CPSIZE_A>[src]
Get enumerated values variant
pub fn is_no_burst_split(&self) -> bool[src]
Checks if the value of the field is NOBURSTSPLIT
pub fn is_bytes128(&self) -> bool[src]
Checks if the value of the field is BYTES128
pub fn is_bytes256(&self) -> bool[src]
Checks if the value of the field is BYTES256
pub fn is_bytes512(&self) -> bool[src]
Checks if the value of the field is BYTES512
pub fn is_bytes1024(&self) -> bool[src]
Checks if the value of the field is BYTES1024
impl R<u32, Reg<u32, _BCR1>>[src]
pub fn cburstrw(&self) -> CBURSTRW_R[src]
Bit 19 - CBURSTRW
pub fn asyncwait(&self) -> ASYNCWAIT_R[src]
Bit 15 - ASYNCWAIT
pub fn extmod(&self) -> EXTMOD_R[src]
Bit 14 - EXTMOD
pub fn waiten(&self) -> WAITEN_R[src]
Bit 13 - WAITEN
pub fn wren(&self) -> WREN_R[src]
Bit 12 - WREN
pub fn waitcfg(&self) -> WAITCFG_R[src]
Bit 11 - WAITCFG
pub fn wrapmod(&self) -> WRAPMOD_R[src]
Bit 10 - WRAPMOD
pub fn waitpol(&self) -> WAITPOL_R[src]
Bit 9 - WAITPOL
pub fn bursten(&self) -> BURSTEN_R[src]
Bit 8 - BURSTEN
pub fn faccen(&self) -> FACCEN_R[src]
Bit 6 - FACCEN
pub fn mwid(&self) -> MWID_R[src]
Bits 4:5 - MWID
pub fn mtyp(&self) -> MTYP_R[src]
Bits 2:3 - MTYP
pub fn muxen(&self) -> MUXEN_R[src]
Bit 1 - MUXEN
pub fn mbken(&self) -> MBKEN_R[src]
Bit 0 - MBKEN
pub fn cpsize(&self) -> CPSIZE_R[src]
Bits 16:18 - CRAM page size
impl R<u8, ACCMOD_A>[src]
pub fn variant(&self) -> ACCMOD_A[src]
Get enumerated values variant
pub fn is_a(&self) -> bool[src]
Checks if the value of the field is A
pub fn is_b(&self) -> bool[src]
Checks if the value of the field is B
pub fn is_c(&self) -> bool[src]
Checks if the value of the field is C
pub fn is_d(&self) -> bool[src]
Checks if the value of the field is D
impl R<u32, Reg<u32, _BTR>>[src]
pub fn accmod(&self) -> ACCMOD_R[src]
Bits 28:29 - ACCMOD
pub fn datlat(&self) -> DATLAT_R[src]
Bits 24:27 - DATLAT
pub fn clkdiv(&self) -> CLKDIV_R[src]
Bits 20:23 - CLKDIV
pub fn busturn(&self) -> BUSTURN_R[src]
Bits 16:19 - BUSTURN
pub fn datast(&self) -> DATAST_R[src]
Bits 8:15 - DATAST
pub fn addhld(&self) -> ADDHLD_R[src]
Bits 4:7 - ADDHLD
pub fn addset(&self) -> ADDSET_R[src]
Bits 0:3 - ADDSET
impl R<bool, CBURSTRW_A>[src]
pub fn variant(&self) -> CBURSTRW_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, ASYNCWAIT_A>[src]
pub fn variant(&self) -> ASYNCWAIT_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, EXTMOD_A>[src]
pub fn variant(&self) -> EXTMOD_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITEN_A>[src]
pub fn variant(&self) -> WAITEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WREN_A>[src]
pub fn variant(&self) -> WREN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITCFG_A>[src]
pub fn variant(&self) -> WAITCFG_A[src]
Get enumerated values variant
pub fn is_before_wait_state(&self) -> bool[src]
Checks if the value of the field is BEFOREWAITSTATE
pub fn is_during_wait_state(&self) -> bool[src]
Checks if the value of the field is DURINGWAITSTATE
impl R<bool, WAITPOL_A>[src]
pub fn variant(&self) -> WAITPOL_A[src]
Get enumerated values variant
pub fn is_active_low(&self) -> bool[src]
Checks if the value of the field is ACTIVELOW
pub fn is_active_high(&self) -> bool[src]
Checks if the value of the field is ACTIVEHIGH
impl R<bool, BURSTEN_A>[src]
pub fn variant(&self) -> BURSTEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, FACCEN_A>[src]
pub fn variant(&self) -> FACCEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, MWID_A>[src]
pub fn variant(&self) -> Variant<u8, MWID_A>[src]
Get enumerated values variant
pub fn is_bits8(&self) -> bool[src]
Checks if the value of the field is BITS8
pub fn is_bits16(&self) -> bool[src]
Checks if the value of the field is BITS16
pub fn is_bits32(&self) -> bool[src]
Checks if the value of the field is BITS32
impl R<u8, MTYP_A>[src]
pub fn variant(&self) -> Variant<u8, MTYP_A>[src]
Get enumerated values variant
pub fn is_sram(&self) -> bool[src]
Checks if the value of the field is SRAM
pub fn is_psram(&self) -> bool[src]
Checks if the value of the field is PSRAM
pub fn is_flash(&self) -> bool[src]
Checks if the value of the field is FLASH
impl R<bool, MUXEN_A>[src]
pub fn variant(&self) -> MUXEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, MBKEN_A>[src]
pub fn variant(&self) -> MBKEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CPSIZE_A>[src]
pub fn variant(&self) -> Variant<u8, CPSIZE_A>[src]
Get enumerated values variant
pub fn is_no_burst_split(&self) -> bool[src]
Checks if the value of the field is NOBURSTSPLIT
pub fn is_bytes128(&self) -> bool[src]
Checks if the value of the field is BYTES128
pub fn is_bytes256(&self) -> bool[src]
Checks if the value of the field is BYTES256
pub fn is_bytes512(&self) -> bool[src]
Checks if the value of the field is BYTES512
pub fn is_bytes1024(&self) -> bool[src]
Checks if the value of the field is BYTES1024
impl R<u32, Reg<u32, _BCR>>[src]
pub fn cburstrw(&self) -> CBURSTRW_R[src]
Bit 19 - CBURSTRW
pub fn asyncwait(&self) -> ASYNCWAIT_R[src]
Bit 15 - ASYNCWAIT
pub fn extmod(&self) -> EXTMOD_R[src]
Bit 14 - EXTMOD
pub fn waiten(&self) -> WAITEN_R[src]
Bit 13 - WAITEN
pub fn wren(&self) -> WREN_R[src]
Bit 12 - WREN
pub fn waitcfg(&self) -> WAITCFG_R[src]
Bit 11 - WAITCFG
pub fn wrapmod(&self) -> WRAPMOD_R[src]
Bit 10 - WRAPMOD
pub fn waitpol(&self) -> WAITPOL_R[src]
Bit 9 - WAITPOL
pub fn bursten(&self) -> BURSTEN_R[src]
Bit 8 - BURSTEN
pub fn faccen(&self) -> FACCEN_R[src]
Bit 6 - FACCEN
pub fn mwid(&self) -> MWID_R[src]
Bits 4:5 - MWID
pub fn mtyp(&self) -> MTYP_R[src]
Bits 2:3 - MTYP
pub fn muxen(&self) -> MUXEN_R[src]
Bit 1 - MUXEN
pub fn mbken(&self) -> MBKEN_R[src]
Bit 0 - MBKEN
pub fn cpsize(&self) -> CPSIZE_R[src]
Bits 16:18 - CRAM page size
impl R<u8, ACCMOD_A>[src]
pub fn variant(&self) -> ACCMOD_A[src]
Get enumerated values variant
pub fn is_a(&self) -> bool[src]
Checks if the value of the field is A
pub fn is_b(&self) -> bool[src]
Checks if the value of the field is B
pub fn is_c(&self) -> bool[src]
Checks if the value of the field is C
pub fn is_d(&self) -> bool[src]
Checks if the value of the field is D
impl R<u32, Reg<u32, _BWTR>>[src]
pub fn accmod(&self) -> ACCMOD_R[src]
Bits 28:29 - ACCMOD
pub fn datlat(&self) -> DATLAT_R[src]
Bits 24:27 - DATLAT
pub fn clkdiv(&self) -> CLKDIV_R[src]
Bits 20:23 - CLKDIV
pub fn datast(&self) -> DATAST_R[src]
Bits 8:15 - DATAST
pub fn addhld(&self) -> ADDHLD_R[src]
Bits 4:7 - ADDHLD
pub fn addset(&self) -> ADDSET_R[src]
Bits 0:3 - ADDSET
pub fn busturn(&self) -> BUSTURN_R[src]
Bits 16:19 - Bus turnaround phase duration
impl R<u8, MODER15_A>[src]
pub fn variant(&self) -> MODER15_A[src]
Get enumerated values variant
pub fn is_input(&self) -> bool[src]
Checks if the value of the field is INPUT
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
pub fn is_alternate(&self) -> bool[src]
Checks if the value of the field is ALTERNATE
pub fn is_analog(&self) -> bool[src]
Checks if the value of the field is ANALOG
impl R<u32, Reg<u32, _MODER>>[src]
pub fn moder15(&self) -> MODER15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&self) -> MODER14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&self) -> MODER13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&self) -> MODER12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&self) -> MODER11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&self) -> MODER10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&self) -> MODER9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&self) -> MODER8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&self) -> MODER7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&self) -> MODER6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&self) -> MODER5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&self) -> MODER4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&self) -> MODER3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&self) -> MODER2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&self) -> MODER1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&self) -> MODER0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, OT15_A>[src]
pub fn variant(&self) -> OT15_A[src]
Get enumerated values variant
pub fn is_push_pull(&self) -> bool[src]
Checks if the value of the field is PUSHPULL
pub fn is_open_drain(&self) -> bool[src]
Checks if the value of the field is OPENDRAIN
impl R<u32, Reg<u32, _OTYPER>>[src]
pub fn ot15(&self) -> OT15_R[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&self) -> OT14_R[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&self) -> OT13_R[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&self) -> OT12_R[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&self) -> OT11_R[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&self) -> OT10_R[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&self) -> OT9_R[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&self) -> OT8_R[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&self) -> OT7_R[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&self) -> OT6_R[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&self) -> OT5_R[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&self) -> OT4_R[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&self) -> OT3_R[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&self) -> OT2_R[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&self) -> OT1_R[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&self) -> OT0_R[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl R<u8, OSPEEDR15_A>[src]
pub fn variant(&self) -> OSPEEDR15_A[src]
Get enumerated values variant
pub fn is_low_speed(&self) -> bool[src]
Checks if the value of the field is LOWSPEED
pub fn is_medium_speed(&self) -> bool[src]
Checks if the value of the field is MEDIUMSPEED
pub fn is_high_speed(&self) -> bool[src]
Checks if the value of the field is HIGHSPEED
pub fn is_very_high_speed(&self) -> bool[src]
Checks if the value of the field is VERYHIGHSPEED
impl R<u32, Reg<u32, _OSPEEDR>>[src]
pub fn ospeedr15(&self) -> OSPEEDR15_R[src]
Bits 30:31 - OSPEEDR15
pub fn ospeedr14(&self) -> OSPEEDR14_R[src]
Bits 28:29 - OSPEEDR14
pub fn ospeedr13(&self) -> OSPEEDR13_R[src]
Bits 26:27 - OSPEEDR13
pub fn ospeedr12(&self) -> OSPEEDR12_R[src]
Bits 24:25 - OSPEEDR12
pub fn ospeedr11(&self) -> OSPEEDR11_R[src]
Bits 22:23 - OSPEEDR11
pub fn ospeedr10(&self) -> OSPEEDR10_R[src]
Bits 20:21 - OSPEEDR10
pub fn ospeedr9(&self) -> OSPEEDR9_R[src]
Bits 18:19 - OSPEEDR9
pub fn ospeedr8(&self) -> OSPEEDR8_R[src]
Bits 16:17 - OSPEEDR8
pub fn ospeedr7(&self) -> OSPEEDR7_R[src]
Bits 14:15 - OSPEEDR7
pub fn ospeedr6(&self) -> OSPEEDR6_R[src]
Bits 12:13 - OSPEEDR6
pub fn ospeedr5(&self) -> OSPEEDR5_R[src]
Bits 10:11 - OSPEEDR5
pub fn ospeedr4(&self) -> OSPEEDR4_R[src]
Bits 8:9 - OSPEEDR4
pub fn ospeedr3(&self) -> OSPEEDR3_R[src]
Bits 6:7 - OSPEEDR3
pub fn ospeedr2(&self) -> OSPEEDR2_R[src]
Bits 4:5 - OSPEEDR2
pub fn ospeedr1(&self) -> OSPEEDR1_R[src]
Bits 2:3 - OSPEEDR1
pub fn ospeedr0(&self) -> OSPEEDR0_R[src]
Bits 0:1 - OSPEEDR0
impl R<u8, PUPDR15_A>[src]
pub fn variant(&self) -> Variant<u8, PUPDR15_A>[src]
Get enumerated values variant
pub fn is_floating(&self) -> bool[src]
Checks if the value of the field is FLOATING
pub fn is_pull_up(&self) -> bool[src]
Checks if the value of the field is PULLUP
pub fn is_pull_down(&self) -> bool[src]
Checks if the value of the field is PULLDOWN
impl R<u32, Reg<u32, _PUPDR>>[src]
pub fn pupdr15(&self) -> PUPDR15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&self) -> PUPDR14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&self) -> PUPDR13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&self) -> PUPDR12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&self) -> PUPDR11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&self) -> PUPDR10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&self) -> PUPDR9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&self) -> PUPDR8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&self) -> PUPDR7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&self) -> PUPDR6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&self) -> PUPDR5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&self) -> PUPDR4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&self) -> PUPDR3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&self) -> PUPDR2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&self) -> PUPDR1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&self) -> PUPDR0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, IDR15_A>[src]
pub fn variant(&self) -> IDR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _IDR>>[src]
pub fn idr15(&self) -> IDR15_R[src]
Bit 15 - Port input data (y = 0..15)
pub fn idr14(&self) -> IDR14_R[src]
Bit 14 - Port input data (y = 0..15)
pub fn idr13(&self) -> IDR13_R[src]
Bit 13 - Port input data (y = 0..15)
pub fn idr12(&self) -> IDR12_R[src]
Bit 12 - Port input data (y = 0..15)
pub fn idr11(&self) -> IDR11_R[src]
Bit 11 - Port input data (y = 0..15)
pub fn idr10(&self) -> IDR10_R[src]
Bit 10 - Port input data (y = 0..15)
pub fn idr9(&self) -> IDR9_R[src]
Bit 9 - Port input data (y = 0..15)
pub fn idr8(&self) -> IDR8_R[src]
Bit 8 - Port input data (y = 0..15)
pub fn idr7(&self) -> IDR7_R[src]
Bit 7 - Port input data (y = 0..15)
pub fn idr6(&self) -> IDR6_R[src]
Bit 6 - Port input data (y = 0..15)
pub fn idr5(&self) -> IDR5_R[src]
Bit 5 - Port input data (y = 0..15)
pub fn idr4(&self) -> IDR4_R[src]
Bit 4 - Port input data (y = 0..15)
pub fn idr3(&self) -> IDR3_R[src]
Bit 3 - Port input data (y = 0..15)
pub fn idr2(&self) -> IDR2_R[src]
Bit 2 - Port input data (y = 0..15)
pub fn idr1(&self) -> IDR1_R[src]
Bit 1 - Port input data (y = 0..15)
pub fn idr0(&self) -> IDR0_R[src]
Bit 0 - Port input data (y = 0..15)
impl R<bool, ODR15_A>[src]
pub fn variant(&self) -> ODR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _ODR>>[src]
pub fn odr15(&self) -> ODR15_R[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&self) -> ODR14_R[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&self) -> ODR13_R[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&self) -> ODR12_R[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&self) -> ODR11_R[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&self) -> ODR10_R[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&self) -> ODR9_R[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&self) -> ODR8_R[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&self) -> ODR7_R[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&self) -> ODR6_R[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&self) -> ODR5_R[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&self) -> ODR4_R[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&self) -> ODR3_R[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&self) -> ODR2_R[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&self) -> ODR1_R[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&self) -> ODR0_R[src]
Bit 0 - Port output data (y = 0..15)
impl R<bool, LCKK_A>[src]
pub fn variant(&self) -> LCKK_A[src]
Get enumerated values variant
pub fn is_not_active(&self) -> bool[src]
Checks if the value of the field is NOTACTIVE
pub fn is_active(&self) -> bool[src]
Checks if the value of the field is ACTIVE
impl R<bool, LCK15_A>[src]
pub fn variant(&self) -> LCK15_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, LCK9_A>[src]
pub fn variant(&self) -> LCK9_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<u32, Reg<u32, _LCKR>>[src]
pub fn lckk(&self) -> LCKK_R[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&self) -> LCK15_R[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&self) -> LCK14_R[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&self) -> LCK13_R[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&self) -> LCK12_R[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&self) -> LCK11_R[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&self) -> LCK10_R[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&self) -> LCK9_R[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&self) -> LCK8_R[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&self) -> LCK7_R[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&self) -> LCK6_R[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&self) -> LCK5_R[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&self) -> LCK4_R[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&self) -> LCK3_R[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&self) -> LCK2_R[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&self) -> LCK1_R[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&self) -> LCK0_R[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl R<u8, AFRL7_A>[src]
pub fn variant(&self) -> AFRL7_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRL>>[src]
pub fn afrl7(&self) -> AFRL7_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&self) -> AFRL6_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&self) -> AFRL5_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&self) -> AFRL4_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&self) -> AFRL3_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&self) -> AFRL2_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&self) -> AFRL1_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&self) -> AFRL0_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl R<u8, AFRH15_A>[src]
pub fn variant(&self) -> AFRH15_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRH>>[src]
pub fn afrh15(&self) -> AFRH15_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&self) -> AFRH14_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&self) -> AFRH13_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&self) -> AFRH12_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&self) -> AFRH11_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&self) -> AFRH10_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&self) -> AFRH9_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&self) -> AFRH8_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl R<u8, MODER15_A>[src]
pub fn variant(&self) -> MODER15_A[src]
Get enumerated values variant
pub fn is_input(&self) -> bool[src]
Checks if the value of the field is INPUT
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
pub fn is_alternate(&self) -> bool[src]
Checks if the value of the field is ALTERNATE
pub fn is_analog(&self) -> bool[src]
Checks if the value of the field is ANALOG
impl R<u32, Reg<u32, _MODER>>[src]
pub fn moder15(&self) -> MODER15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&self) -> MODER14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&self) -> MODER13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&self) -> MODER12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&self) -> MODER11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&self) -> MODER10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&self) -> MODER9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&self) -> MODER8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&self) -> MODER7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&self) -> MODER6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&self) -> MODER5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&self) -> MODER4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&self) -> MODER3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&self) -> MODER2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&self) -> MODER1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&self) -> MODER0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, OT15_A>[src]
pub fn variant(&self) -> OT15_A[src]
Get enumerated values variant
pub fn is_push_pull(&self) -> bool[src]
Checks if the value of the field is PUSHPULL
pub fn is_open_drain(&self) -> bool[src]
Checks if the value of the field is OPENDRAIN
impl R<u32, Reg<u32, _OTYPER>>[src]
pub fn ot15(&self) -> OT15_R[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&self) -> OT14_R[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&self) -> OT13_R[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&self) -> OT12_R[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&self) -> OT11_R[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&self) -> OT10_R[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&self) -> OT9_R[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&self) -> OT8_R[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&self) -> OT7_R[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&self) -> OT6_R[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&self) -> OT5_R[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&self) -> OT4_R[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&self) -> OT3_R[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&self) -> OT2_R[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&self) -> OT1_R[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&self) -> OT0_R[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl R<u8, OSPEEDR15_A>[src]
pub fn variant(&self) -> OSPEEDR15_A[src]
Get enumerated values variant
pub fn is_low_speed(&self) -> bool[src]
Checks if the value of the field is LOWSPEED
pub fn is_medium_speed(&self) -> bool[src]
Checks if the value of the field is MEDIUMSPEED
pub fn is_high_speed(&self) -> bool[src]
Checks if the value of the field is HIGHSPEED
pub fn is_very_high_speed(&self) -> bool[src]
Checks if the value of the field is VERYHIGHSPEED
impl R<u32, Reg<u32, _OSPEEDR>>[src]
pub fn ospeedr15(&self) -> OSPEEDR15_R[src]
Bits 30:31 - OSPEEDR15
pub fn ospeedr14(&self) -> OSPEEDR14_R[src]
Bits 28:29 - OSPEEDR14
pub fn ospeedr13(&self) -> OSPEEDR13_R[src]
Bits 26:27 - OSPEEDR13
pub fn ospeedr12(&self) -> OSPEEDR12_R[src]
Bits 24:25 - OSPEEDR12
pub fn ospeedr11(&self) -> OSPEEDR11_R[src]
Bits 22:23 - OSPEEDR11
pub fn ospeedr10(&self) -> OSPEEDR10_R[src]
Bits 20:21 - OSPEEDR10
pub fn ospeedr9(&self) -> OSPEEDR9_R[src]
Bits 18:19 - OSPEEDR9
pub fn ospeedr8(&self) -> OSPEEDR8_R[src]
Bits 16:17 - OSPEEDR8
pub fn ospeedr7(&self) -> OSPEEDR7_R[src]
Bits 14:15 - OSPEEDR7
pub fn ospeedr6(&self) -> OSPEEDR6_R[src]
Bits 12:13 - OSPEEDR6
pub fn ospeedr5(&self) -> OSPEEDR5_R[src]
Bits 10:11 - OSPEEDR5
pub fn ospeedr4(&self) -> OSPEEDR4_R[src]
Bits 8:9 - OSPEEDR4
pub fn ospeedr3(&self) -> OSPEEDR3_R[src]
Bits 6:7 - OSPEEDR3
pub fn ospeedr2(&self) -> OSPEEDR2_R[src]
Bits 4:5 - OSPEEDR2
pub fn ospeedr1(&self) -> OSPEEDR1_R[src]
Bits 2:3 - OSPEEDR1
pub fn ospeedr0(&self) -> OSPEEDR0_R[src]
Bits 0:1 - OSPEEDR0
impl R<u8, PUPDR15_A>[src]
pub fn variant(&self) -> Variant<u8, PUPDR15_A>[src]
Get enumerated values variant
pub fn is_floating(&self) -> bool[src]
Checks if the value of the field is FLOATING
pub fn is_pull_up(&self) -> bool[src]
Checks if the value of the field is PULLUP
pub fn is_pull_down(&self) -> bool[src]
Checks if the value of the field is PULLDOWN
impl R<u32, Reg<u32, _PUPDR>>[src]
pub fn pupdr15(&self) -> PUPDR15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&self) -> PUPDR14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&self) -> PUPDR13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&self) -> PUPDR12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&self) -> PUPDR11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&self) -> PUPDR10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&self) -> PUPDR9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&self) -> PUPDR8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&self) -> PUPDR7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&self) -> PUPDR6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&self) -> PUPDR5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&self) -> PUPDR4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&self) -> PUPDR3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&self) -> PUPDR2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&self) -> PUPDR1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&self) -> PUPDR0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, IDR15_A>[src]
pub fn variant(&self) -> IDR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _IDR>>[src]
pub fn idr15(&self) -> IDR15_R[src]
Bit 15 - Port input data (y = 0..15)
pub fn idr14(&self) -> IDR14_R[src]
Bit 14 - Port input data (y = 0..15)
pub fn idr13(&self) -> IDR13_R[src]
Bit 13 - Port input data (y = 0..15)
pub fn idr12(&self) -> IDR12_R[src]
Bit 12 - Port input data (y = 0..15)
pub fn idr11(&self) -> IDR11_R[src]
Bit 11 - Port input data (y = 0..15)
pub fn idr10(&self) -> IDR10_R[src]
Bit 10 - Port input data (y = 0..15)
pub fn idr9(&self) -> IDR9_R[src]
Bit 9 - Port input data (y = 0..15)
pub fn idr8(&self) -> IDR8_R[src]
Bit 8 - Port input data (y = 0..15)
pub fn idr7(&self) -> IDR7_R[src]
Bit 7 - Port input data (y = 0..15)
pub fn idr6(&self) -> IDR6_R[src]
Bit 6 - Port input data (y = 0..15)
pub fn idr5(&self) -> IDR5_R[src]
Bit 5 - Port input data (y = 0..15)
pub fn idr4(&self) -> IDR4_R[src]
Bit 4 - Port input data (y = 0..15)
pub fn idr3(&self) -> IDR3_R[src]
Bit 3 - Port input data (y = 0..15)
pub fn idr2(&self) -> IDR2_R[src]
Bit 2 - Port input data (y = 0..15)
pub fn idr1(&self) -> IDR1_R[src]
Bit 1 - Port input data (y = 0..15)
pub fn idr0(&self) -> IDR0_R[src]
Bit 0 - Port input data (y = 0..15)
impl R<bool, ODR15_A>[src]
pub fn variant(&self) -> ODR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _ODR>>[src]
pub fn odr15(&self) -> ODR15_R[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&self) -> ODR14_R[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&self) -> ODR13_R[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&self) -> ODR12_R[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&self) -> ODR11_R[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&self) -> ODR10_R[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&self) -> ODR9_R[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&self) -> ODR8_R[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&self) -> ODR7_R[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&self) -> ODR6_R[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&self) -> ODR5_R[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&self) -> ODR4_R[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&self) -> ODR3_R[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&self) -> ODR2_R[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&self) -> ODR1_R[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&self) -> ODR0_R[src]
Bit 0 - Port output data (y = 0..15)
impl R<bool, LCKK_A>[src]
pub fn variant(&self) -> LCKK_A[src]
Get enumerated values variant
pub fn is_not_active(&self) -> bool[src]
Checks if the value of the field is NOTACTIVE
pub fn is_active(&self) -> bool[src]
Checks if the value of the field is ACTIVE
impl R<bool, LCK15_A>[src]
pub fn variant(&self) -> LCK15_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, LCK9_A>[src]
pub fn variant(&self) -> LCK9_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<u32, Reg<u32, _LCKR>>[src]
pub fn lckk(&self) -> LCKK_R[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&self) -> LCK15_R[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&self) -> LCK14_R[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&self) -> LCK13_R[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&self) -> LCK12_R[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&self) -> LCK11_R[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&self) -> LCK10_R[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&self) -> LCK9_R[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&self) -> LCK8_R[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&self) -> LCK7_R[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&self) -> LCK6_R[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&self) -> LCK5_R[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&self) -> LCK4_R[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&self) -> LCK3_R[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&self) -> LCK2_R[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&self) -> LCK1_R[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&self) -> LCK0_R[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl R<u8, AFRL7_A>[src]
pub fn variant(&self) -> AFRL7_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRL>>[src]
pub fn afrl7(&self) -> AFRL7_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&self) -> AFRL6_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&self) -> AFRL5_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&self) -> AFRL4_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&self) -> AFRL3_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&self) -> AFRL2_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&self) -> AFRL1_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&self) -> AFRL0_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl R<u8, AFRH15_A>[src]
pub fn variant(&self) -> AFRH15_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRH>>[src]
pub fn afrh15(&self) -> AFRH15_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&self) -> AFRH14_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&self) -> AFRH13_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&self) -> AFRH12_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&self) -> AFRH11_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&self) -> AFRH10_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&self) -> AFRH9_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&self) -> AFRH8_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl R<u8, MODER15_A>[src]
pub fn variant(&self) -> MODER15_A[src]
Get enumerated values variant
pub fn is_input(&self) -> bool[src]
Checks if the value of the field is INPUT
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
pub fn is_alternate(&self) -> bool[src]
Checks if the value of the field is ALTERNATE
pub fn is_analog(&self) -> bool[src]
Checks if the value of the field is ANALOG
impl R<u32, Reg<u32, _MODER>>[src]
pub fn moder15(&self) -> MODER15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&self) -> MODER14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&self) -> MODER13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&self) -> MODER12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&self) -> MODER11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&self) -> MODER10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&self) -> MODER9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&self) -> MODER8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&self) -> MODER7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&self) -> MODER6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&self) -> MODER5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&self) -> MODER4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&self) -> MODER3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&self) -> MODER2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&self) -> MODER1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&self) -> MODER0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, OT15_A>[src]
pub fn variant(&self) -> OT15_A[src]
Get enumerated values variant
pub fn is_push_pull(&self) -> bool[src]
Checks if the value of the field is PUSHPULL
pub fn is_open_drain(&self) -> bool[src]
Checks if the value of the field is OPENDRAIN
impl R<u32, Reg<u32, _OTYPER>>[src]
pub fn ot15(&self) -> OT15_R[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&self) -> OT14_R[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&self) -> OT13_R[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&self) -> OT12_R[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&self) -> OT11_R[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&self) -> OT10_R[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&self) -> OT9_R[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&self) -> OT8_R[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&self) -> OT7_R[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&self) -> OT6_R[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&self) -> OT5_R[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&self) -> OT4_R[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&self) -> OT3_R[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&self) -> OT2_R[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&self) -> OT1_R[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&self) -> OT0_R[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl R<u8, OSPEEDR15_A>[src]
pub fn variant(&self) -> OSPEEDR15_A[src]
Get enumerated values variant
pub fn is_low_speed(&self) -> bool[src]
Checks if the value of the field is LOWSPEED
pub fn is_medium_speed(&self) -> bool[src]
Checks if the value of the field is MEDIUMSPEED
pub fn is_high_speed(&self) -> bool[src]
Checks if the value of the field is HIGHSPEED
pub fn is_very_high_speed(&self) -> bool[src]
Checks if the value of the field is VERYHIGHSPEED
impl R<u32, Reg<u32, _OSPEEDR>>[src]
pub fn ospeedr15(&self) -> OSPEEDR15_R[src]
Bits 30:31 - OSPEEDR15
pub fn ospeedr14(&self) -> OSPEEDR14_R[src]
Bits 28:29 - OSPEEDR14
pub fn ospeedr13(&self) -> OSPEEDR13_R[src]
Bits 26:27 - OSPEEDR13
pub fn ospeedr12(&self) -> OSPEEDR12_R[src]
Bits 24:25 - OSPEEDR12
pub fn ospeedr11(&self) -> OSPEEDR11_R[src]
Bits 22:23 - OSPEEDR11
pub fn ospeedr10(&self) -> OSPEEDR10_R[src]
Bits 20:21 - OSPEEDR10
pub fn ospeedr9(&self) -> OSPEEDR9_R[src]
Bits 18:19 - OSPEEDR9
pub fn ospeedr8(&self) -> OSPEEDR8_R[src]
Bits 16:17 - OSPEEDR8
pub fn ospeedr7(&self) -> OSPEEDR7_R[src]
Bits 14:15 - OSPEEDR7
pub fn ospeedr6(&self) -> OSPEEDR6_R[src]
Bits 12:13 - OSPEEDR6
pub fn ospeedr5(&self) -> OSPEEDR5_R[src]
Bits 10:11 - OSPEEDR5
pub fn ospeedr4(&self) -> OSPEEDR4_R[src]
Bits 8:9 - OSPEEDR4
pub fn ospeedr3(&self) -> OSPEEDR3_R[src]
Bits 6:7 - OSPEEDR3
pub fn ospeedr2(&self) -> OSPEEDR2_R[src]
Bits 4:5 - OSPEEDR2
pub fn ospeedr1(&self) -> OSPEEDR1_R[src]
Bits 2:3 - OSPEEDR1
pub fn ospeedr0(&self) -> OSPEEDR0_R[src]
Bits 0:1 - OSPEEDR0
impl R<u8, PUPDR15_A>[src]
pub fn variant(&self) -> Variant<u8, PUPDR15_A>[src]
Get enumerated values variant
pub fn is_floating(&self) -> bool[src]
Checks if the value of the field is FLOATING
pub fn is_pull_up(&self) -> bool[src]
Checks if the value of the field is PULLUP
pub fn is_pull_down(&self) -> bool[src]
Checks if the value of the field is PULLDOWN
impl R<u32, Reg<u32, _PUPDR>>[src]
pub fn pupdr15(&self) -> PUPDR15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&self) -> PUPDR14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&self) -> PUPDR13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&self) -> PUPDR12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&self) -> PUPDR11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&self) -> PUPDR10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&self) -> PUPDR9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&self) -> PUPDR8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&self) -> PUPDR7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&self) -> PUPDR6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&self) -> PUPDR5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&self) -> PUPDR4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&self) -> PUPDR3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&self) -> PUPDR2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&self) -> PUPDR1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&self) -> PUPDR0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, IDR15_A>[src]
pub fn variant(&self) -> IDR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _IDR>>[src]
pub fn idr15(&self) -> IDR15_R[src]
Bit 15 - Port input data (y = 0..15)
pub fn idr14(&self) -> IDR14_R[src]
Bit 14 - Port input data (y = 0..15)
pub fn idr13(&self) -> IDR13_R[src]
Bit 13 - Port input data (y = 0..15)
pub fn idr12(&self) -> IDR12_R[src]
Bit 12 - Port input data (y = 0..15)
pub fn idr11(&self) -> IDR11_R[src]
Bit 11 - Port input data (y = 0..15)
pub fn idr10(&self) -> IDR10_R[src]
Bit 10 - Port input data (y = 0..15)
pub fn idr9(&self) -> IDR9_R[src]
Bit 9 - Port input data (y = 0..15)
pub fn idr8(&self) -> IDR8_R[src]
Bit 8 - Port input data (y = 0..15)
pub fn idr7(&self) -> IDR7_R[src]
Bit 7 - Port input data (y = 0..15)
pub fn idr6(&self) -> IDR6_R[src]
Bit 6 - Port input data (y = 0..15)
pub fn idr5(&self) -> IDR5_R[src]
Bit 5 - Port input data (y = 0..15)
pub fn idr4(&self) -> IDR4_R[src]
Bit 4 - Port input data (y = 0..15)
pub fn idr3(&self) -> IDR3_R[src]
Bit 3 - Port input data (y = 0..15)
pub fn idr2(&self) -> IDR2_R[src]
Bit 2 - Port input data (y = 0..15)
pub fn idr1(&self) -> IDR1_R[src]
Bit 1 - Port input data (y = 0..15)
pub fn idr0(&self) -> IDR0_R[src]
Bit 0 - Port input data (y = 0..15)
impl R<bool, ODR15_A>[src]
pub fn variant(&self) -> ODR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _ODR>>[src]
pub fn odr15(&self) -> ODR15_R[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&self) -> ODR14_R[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&self) -> ODR13_R[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&self) -> ODR12_R[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&self) -> ODR11_R[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&self) -> ODR10_R[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&self) -> ODR9_R[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&self) -> ODR8_R[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&self) -> ODR7_R[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&self) -> ODR6_R[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&self) -> ODR5_R[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&self) -> ODR4_R[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&self) -> ODR3_R[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&self) -> ODR2_R[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&self) -> ODR1_R[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&self) -> ODR0_R[src]
Bit 0 - Port output data (y = 0..15)
impl R<bool, LCKK_A>[src]
pub fn variant(&self) -> LCKK_A[src]
Get enumerated values variant
pub fn is_not_active(&self) -> bool[src]
Checks if the value of the field is NOTACTIVE
pub fn is_active(&self) -> bool[src]
Checks if the value of the field is ACTIVE
impl R<bool, LCK15_A>[src]
pub fn variant(&self) -> LCK15_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, LCK9_A>[src]
pub fn variant(&self) -> LCK9_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<u32, Reg<u32, _LCKR>>[src]
pub fn lckk(&self) -> LCKK_R[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&self) -> LCK15_R[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&self) -> LCK14_R[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&self) -> LCK13_R[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&self) -> LCK12_R[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&self) -> LCK11_R[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&self) -> LCK10_R[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&self) -> LCK9_R[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&self) -> LCK8_R[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&self) -> LCK7_R[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&self) -> LCK6_R[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&self) -> LCK5_R[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&self) -> LCK4_R[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&self) -> LCK3_R[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&self) -> LCK2_R[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&self) -> LCK1_R[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&self) -> LCK0_R[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl R<u8, AFRL7_A>[src]
pub fn variant(&self) -> AFRL7_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRL>>[src]
pub fn afrl7(&self) -> AFRL7_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&self) -> AFRL6_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&self) -> AFRL5_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&self) -> AFRL4_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&self) -> AFRL3_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&self) -> AFRL2_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&self) -> AFRL1_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&self) -> AFRL0_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl R<u8, AFRH15_A>[src]
pub fn variant(&self) -> AFRH15_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRH>>[src]
pub fn afrh15(&self) -> AFRH15_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&self) -> AFRH14_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&self) -> AFRH13_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&self) -> AFRH12_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&self) -> AFRH11_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&self) -> AFRH10_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&self) -> AFRH9_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&self) -> AFRH8_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl R<bool, SWRST_A>[src]
pub fn variant(&self) -> SWRST_A[src]
Get enumerated values variant
pub fn is_not_reset(&self) -> bool[src]
Checks if the value of the field is NOTRESET
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<bool, ALERT_A>[src]
pub fn variant(&self) -> ALERT_A[src]
Get enumerated values variant
pub fn is_release(&self) -> bool[src]
Checks if the value of the field is RELEASE
pub fn is_drive(&self) -> bool[src]
Checks if the value of the field is DRIVE
impl R<bool, PEC_A>[src]
pub fn variant(&self) -> PEC_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, POS_A>[src]
pub fn variant(&self) -> POS_A[src]
Get enumerated values variant
pub fn is_current(&self) -> bool[src]
Checks if the value of the field is CURRENT
pub fn is_next(&self) -> bool[src]
Checks if the value of the field is NEXT
impl R<bool, ACK_A>[src]
pub fn variant(&self) -> ACK_A[src]
Get enumerated values variant
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_ack(&self) -> bool[src]
Checks if the value of the field is ACK
impl R<bool, STOP_A>[src]
pub fn variant(&self) -> STOP_A[src]
Get enumerated values variant
pub fn is_no_stop(&self) -> bool[src]
Checks if the value of the field is NOSTOP
pub fn is_stop(&self) -> bool[src]
Checks if the value of the field is STOP
impl R<bool, START_A>[src]
pub fn variant(&self) -> START_A[src]
Get enumerated values variant
pub fn is_no_start(&self) -> bool[src]
Checks if the value of the field is NOSTART
pub fn is_start(&self) -> bool[src]
Checks if the value of the field is START
impl R<bool, NOSTRETCH_A>[src]
pub fn variant(&self) -> NOSTRETCH_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, ENGC_A>[src]
pub fn variant(&self) -> ENGC_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ENPEC_A>[src]
pub fn variant(&self) -> ENPEC_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ENARP_A>[src]
pub fn variant(&self) -> ENARP_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, SMBTYPE_A>[src]
pub fn variant(&self) -> SMBTYPE_A[src]
Get enumerated values variant
pub fn is_device(&self) -> bool[src]
Checks if the value of the field is DEVICE
pub fn is_host(&self) -> bool[src]
Checks if the value of the field is HOST
impl R<bool, SMBUS_A>[src]
pub fn variant(&self) -> SMBUS_A[src]
Get enumerated values variant
pub fn is_i2c(&self) -> bool[src]
Checks if the value of the field is I2C
pub fn is_smbus(&self) -> bool[src]
Checks if the value of the field is SMBUS
impl R<bool, PE_A>[src]
pub fn variant(&self) -> PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn swrst(&self) -> SWRST_R[src]
Bit 15 - Software reset
pub fn alert(&self) -> ALERT_R[src]
Bit 13 - SMBus alert
pub fn pec(&self) -> PEC_R[src]
Bit 12 - Packet error checking
pub fn pos(&self) -> POS_R[src]
Bit 11 - Acknowledge/PEC Position (for data reception)
pub fn ack(&self) -> ACK_R[src]
Bit 10 - Acknowledge enable
pub fn stop(&self) -> STOP_R[src]
Bit 9 - Stop generation
pub fn start(&self) -> START_R[src]
Bit 8 - Start generation
pub fn nostretch(&self) -> NOSTRETCH_R[src]
Bit 7 - Clock stretching disable (Slave mode)
pub fn engc(&self) -> ENGC_R[src]
Bit 6 - General call enable
pub fn enpec(&self) -> ENPEC_R[src]
Bit 5 - PEC enable
pub fn enarp(&self) -> ENARP_R[src]
Bit 4 - ARP enable
pub fn smbtype(&self) -> SMBTYPE_R[src]
Bit 3 - SMBus type
pub fn smbus(&self) -> SMBUS_R[src]
Bit 1 - SMBus mode
pub fn pe(&self) -> PE_R[src]
Bit 0 - Peripheral enable
impl R<bool, LAST_A>[src]
pub fn variant(&self) -> LAST_A[src]
Get enumerated values variant
pub fn is_not_last(&self) -> bool[src]
Checks if the value of the field is NOTLAST
pub fn is_last(&self) -> bool[src]
Checks if the value of the field is LAST
impl R<bool, DMAEN_A>[src]
pub fn variant(&self) -> DMAEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ITBUFEN_A>[src]
pub fn variant(&self) -> ITBUFEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ITEVTEN_A>[src]
pub fn variant(&self) -> ITEVTEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ITERREN_A>[src]
pub fn variant(&self) -> ITERREN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR2>>[src]
pub fn last(&self) -> LAST_R[src]
Bit 12 - DMA last transfer
pub fn dmaen(&self) -> DMAEN_R[src]
Bit 11 - DMA requests enable
pub fn itbufen(&self) -> ITBUFEN_R[src]
Bit 10 - Buffer interrupt enable
pub fn itevten(&self) -> ITEVTEN_R[src]
Bit 9 - Event interrupt enable
pub fn iterren(&self) -> ITERREN_R[src]
Bit 8 - Error interrupt enable
pub fn freq(&self) -> FREQ_R[src]
Bits 0:5 - Peripheral clock frequency
impl R<bool, ADDMODE_A>[src]
pub fn variant(&self) -> ADDMODE_A[src]
Get enumerated values variant
pub fn is_add7(&self) -> bool[src]
Checks if the value of the field is ADD7
pub fn is_add10(&self) -> bool[src]
Checks if the value of the field is ADD10
impl R<u32, Reg<u32, _OAR1>>[src]
pub fn addmode(&self) -> ADDMODE_R[src]
Bit 15 - ADDMODE
pub fn add(&self) -> ADD_R[src]
Bits 0:9 - Interface address
impl R<bool, ENDUAL_A>[src]
pub fn variant(&self) -> ENDUAL_A[src]
Get enumerated values variant
pub fn is_single(&self) -> bool[src]
Checks if the value of the field is SINGLE
pub fn is_dual(&self) -> bool[src]
Checks if the value of the field is DUAL
impl R<u32, Reg<u32, _OAR2>>[src]
pub fn add2(&self) -> ADD2_R[src]
Bits 1:7 - Interface address
pub fn endual(&self) -> ENDUAL_R[src]
Bit 0 - Dual addressing mode enable
impl R<u32, Reg<u32, _DR>>[src]
impl R<bool, SMBALERT_A>[src]
pub fn variant(&self) -> SMBALERT_A[src]
Get enumerated values variant
pub fn is_no_alert(&self) -> bool[src]
Checks if the value of the field is NOALERT
pub fn is_alert(&self) -> bool[src]
Checks if the value of the field is ALERT
impl R<bool, TIMEOUT_A>[src]
pub fn variant(&self) -> TIMEOUT_A[src]
Get enumerated values variant
pub fn is_no_timeout(&self) -> bool[src]
Checks if the value of the field is NOTIMEOUT
pub fn is_timeout(&self) -> bool[src]
Checks if the value of the field is TIMEOUT
impl R<bool, PECERR_A>[src]
pub fn variant(&self) -> PECERR_A[src]
Get enumerated values variant
pub fn is_no_error(&self) -> bool[src]
Checks if the value of the field is NOERROR
pub fn is_error(&self) -> bool[src]
Checks if the value of the field is ERROR
impl R<bool, OVR_A>[src]
pub fn variant(&self) -> OVR_A[src]
Get enumerated values variant
pub fn is_no_overrun(&self) -> bool[src]
Checks if the value of the field is NOOVERRUN
pub fn is_overrun(&self) -> bool[src]
Checks if the value of the field is OVERRUN
impl R<bool, AF_A>[src]
pub fn variant(&self) -> AF_A[src]
Get enumerated values variant
pub fn is_no_failure(&self) -> bool[src]
Checks if the value of the field is NOFAILURE
pub fn is_failure(&self) -> bool[src]
Checks if the value of the field is FAILURE
impl R<bool, ARLO_A>[src]
pub fn variant(&self) -> ARLO_A[src]
Get enumerated values variant
pub fn is_no_lost(&self) -> bool[src]
Checks if the value of the field is NOLOST
pub fn is_lost(&self) -> bool[src]
Checks if the value of the field is LOST
impl R<bool, BERR_A>[src]
pub fn variant(&self) -> BERR_A[src]
Get enumerated values variant
pub fn is_no_error(&self) -> bool[src]
Checks if the value of the field is NOERROR
pub fn is_error(&self) -> bool[src]
Checks if the value of the field is ERROR
impl R<bool, TXE_A>[src]
pub fn variant(&self) -> TXE_A[src]
Get enumerated values variant
pub fn is_not_empty(&self) -> bool[src]
Checks if the value of the field is NOTEMPTY
pub fn is_empty(&self) -> bool[src]
Checks if the value of the field is EMPTY
impl R<bool, RXNE_A>[src]
pub fn variant(&self) -> RXNE_A[src]
Get enumerated values variant
pub fn is_empty(&self) -> bool[src]
Checks if the value of the field is EMPTY
pub fn is_not_empty(&self) -> bool[src]
Checks if the value of the field is NOTEMPTY
impl R<bool, STOPF_A>[src]
pub fn variant(&self) -> STOPF_A[src]
Get enumerated values variant
pub fn is_no_stop(&self) -> bool[src]
Checks if the value of the field is NOSTOP
pub fn is_stop(&self) -> bool[src]
Checks if the value of the field is STOP
impl R<bool, BTF_A>[src]
pub fn variant(&self) -> BTF_A[src]
Get enumerated values variant
pub fn is_not_finished(&self) -> bool[src]
Checks if the value of the field is NOTFINISHED
pub fn is_finished(&self) -> bool[src]
Checks if the value of the field is FINISHED
impl R<bool, ADDR_A>[src]
pub fn variant(&self) -> ADDR_A[src]
Get enumerated values variant
pub fn is_not_match(&self) -> bool[src]
Checks if the value of the field is NOTMATCH
pub fn is_match_(&self) -> bool[src]
Checks if the value of the field is MATCH
impl R<bool, SB_A>[src]
pub fn variant(&self) -> SB_A[src]
Get enumerated values variant
pub fn is_no_start(&self) -> bool[src]
Checks if the value of the field is NOSTART
pub fn is_start(&self) -> bool[src]
Checks if the value of the field is START
impl R<u32, Reg<u32, _SR1>>[src]
pub fn smbalert(&self) -> SMBALERT_R[src]
Bit 15 - SMBus alert
pub fn timeout(&self) -> TIMEOUT_R[src]
Bit 14 - Timeout or Tlow error
pub fn pecerr(&self) -> PECERR_R[src]
Bit 12 - PEC Error in reception
pub fn ovr(&self) -> OVR_R[src]
Bit 11 - Overrun/Underrun
pub fn af(&self) -> AF_R[src]
Bit 10 - Acknowledge failure
pub fn arlo(&self) -> ARLO_R[src]
Bit 9 - Arbitration lost (master mode)
pub fn berr(&self) -> BERR_R[src]
Bit 8 - Bus error
pub fn tx_e(&self) -> TXE_R[src]
Bit 7 - Data register empty (transmitters)
pub fn rx_ne(&self) -> RXNE_R[src]
Bit 6 - Data register not empty (receivers)
pub fn stopf(&self) -> STOPF_R[src]
Bit 4 - Stop detection (slave mode)
pub fn add10(&self) -> ADD10_R[src]
Bit 3 - 10-bit header sent (Master mode)
pub fn btf(&self) -> BTF_R[src]
Bit 2 - Byte transfer finished
pub fn addr(&self) -> ADDR_R[src]
Bit 1 - Address sent (master mode)/matched (slave mode)
pub fn sb(&self) -> SB_R[src]
Bit 0 - Start bit (Master mode)
impl R<u32, Reg<u32, _SR2>>[src]
pub fn pec(&self) -> PEC_R[src]
Bits 8:15 - acket error checking register
pub fn dualf(&self) -> DUALF_R[src]
Bit 7 - Dual flag (Slave mode)
pub fn smbhost(&self) -> SMBHOST_R[src]
Bit 6 - SMBus host header (Slave mode)
pub fn smbdefault(&self) -> SMBDEFAULT_R[src]
Bit 5 - SMBus device default address (Slave mode)
pub fn gencall(&self) -> GENCALL_R[src]
Bit 4 - General call address (Slave mode)
pub fn tra(&self) -> TRA_R[src]
Bit 2 - Transmitter/receiver
pub fn busy(&self) -> BUSY_R[src]
Bit 1 - Bus busy
pub fn msl(&self) -> MSL_R[src]
Bit 0 - Master/slave
impl R<bool, F_S_A>[src]
pub fn variant(&self) -> F_S_A[src]
Get enumerated values variant
pub fn is_standard(&self) -> bool[src]
Checks if the value of the field is STANDARD
pub fn is_fast(&self) -> bool[src]
Checks if the value of the field is FAST
impl R<bool, DUTY_A>[src]
pub fn variant(&self) -> DUTY_A[src]
Get enumerated values variant
pub fn is_duty2_1(&self) -> bool[src]
Checks if the value of the field is DUTY2_1
pub fn is_duty16_9(&self) -> bool[src]
Checks if the value of the field is DUTY16_9
impl R<u32, Reg<u32, _CCR>>[src]
pub fn f_s(&self) -> F_S_R[src]
Bit 15 - I2C master mode selection
pub fn duty(&self) -> DUTY_R[src]
Bit 14 - Fast mode duty cycle
pub fn ccr(&self) -> CCR_R[src]
Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)
impl R<u32, Reg<u32, _TRISE>>[src]
impl R<u8, PR_A>[src]
pub fn variant(&self) -> PR_A[src]
Get enumerated values variant
pub fn is_divide_by4(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY4
pub fn is_divide_by8(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY8
pub fn is_divide_by16(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY16
pub fn is_divide_by32(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY32
pub fn is_divide_by64(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY64
pub fn is_divide_by128(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY128
pub fn is_divide_by256(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY256
pub fn is_divide_by256bis(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY256BIS
impl R<u32, Reg<u32, _PR>>[src]
impl R<u32, Reg<u32, _RLR>>[src]
impl R<u32, Reg<u32, _SR>>[src]
pub fn rvu(&self) -> RVU_R[src]
Bit 1 - Watchdog counter reload value update
pub fn pvu(&self) -> PVU_R[src]
Bit 0 - Watchdog prescaler value update
impl R<u32, Reg<u32, _CR>>[src]
pub fn mux_seg(&self) -> MUX_SEG_R[src]
Bit 7 - Mux segment enable
pub fn bias(&self) -> BIAS_R[src]
Bits 5:6 - Bias selector
pub fn duty(&self) -> DUTY_R[src]
Bits 2:4 - Duty selection
pub fn vsel(&self) -> VSEL_R[src]
Bit 1 - Voltage source selection
pub fn lcden(&self) -> LCDEN_R[src]
Bit 0 - LCD controller enable
impl R<u32, Reg<u32, _FCR>>[src]
pub fn ps(&self) -> PS_R[src]
Bits 22:25 - PS 16-bit prescaler
pub fn div(&self) -> DIV_R[src]
Bits 18:21 - DIV clock divider
pub fn blink(&self) -> BLINK_R[src]
Bits 16:17 - Blink mode selection
pub fn blinkf(&self) -> BLINKF_R[src]
Bits 13:15 - Blink frequency selection
pub fn cc(&self) -> CC_R[src]
Bits 10:12 - Contrast control
pub fn dead(&self) -> DEAD_R[src]
Bits 7:9 - Dead time duration
pub fn pon(&self) -> PON_R[src]
Bits 4:6 - Pulse ON duration
pub fn uddie(&self) -> UDDIE_R[src]
Bit 3 - Update display done interrupt enable
pub fn sofie(&self) -> SOFIE_R[src]
Bit 1 - Start of frame interrupt enable
pub fn hd(&self) -> HD_R[src]
Bit 0 - High drive enable
impl R<u32, Reg<u32, _SR>>[src]
pub fn fcrsf(&self) -> FCRSF_R[src]
Bit 5 - LCD Frame Control Register Synchronization flag
pub fn rdy(&self) -> RDY_R[src]
Bit 4 - Ready flag
pub fn udd(&self) -> UDD_R[src]
Bit 3 - Update Display Done
pub fn udr(&self) -> UDR_R[src]
Bit 2 - Update display request
pub fn sof(&self) -> SOF_R[src]
Bit 1 - Start of frame flag
pub fn ens(&self) -> ENS_R[src]
Bit 0 - LCD enabled status
impl R<u32, Reg<u32, _RAM_COM0>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM1>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM2>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM3>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM4>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM5>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM6>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM7>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _CSR>>[src]
pub fn opa3calout(&self) -> OPA3CALOUT_R[src]
Bit 31 - OPAMP3 calibration output
pub fn opa2calout(&self) -> OPA2CALOUT_R[src]
Bit 30 - OPAMP2 calibration output
pub fn opa1calout(&self) -> OPA1CALOUT_R[src]
Bit 29 - OPAMP1 calibration output
pub fn aop_range(&self) -> AOP_RANGE_R[src]
Bit 28 - Power range selection
pub fn s7sel2(&self) -> S7SEL2_R[src]
Bit 27 - Switch 7 for OPAMP2 enable
pub fn anawsel3(&self) -> ANAWSEL3_R[src]
Bit 26 - Switch SanA enable for OPAMP3
pub fn anawsel2(&self) -> ANAWSEL2_R[src]
Bit 25 - Switch SanA enable for OPAMP2
pub fn anawsel1(&self) -> ANAWSEL1_R[src]
Bit 24 - Switch SanA enable for OPAMP1
pub fn opa3lpm(&self) -> OPA3LPM_R[src]
Bit 23 - OPAMP3 low power mode
pub fn opa3cal_h(&self) -> OPA3CAL_H_R[src]
Bit 22 - OPAMP3 offset calibration for N differential pair
pub fn opa3cal_l(&self) -> OPA3CAL_L_R[src]
Bit 21 - OPAMP3 offset Calibration for P differential pair
pub fn s6sel3(&self) -> S6SEL3_R[src]
Bit 20 - Switch 6 for OPAMP3 enable
pub fn s5sel3(&self) -> S5SEL3_R[src]
Bit 19 - Switch 5 for OPAMP3 enable
pub fn s4sel3(&self) -> S4SEL3_R[src]
Bit 18 - Switch 4 for OPAMP3 enable
pub fn s3sel3(&self) -> S3SEL3_R[src]
Bit 17 - Switch 3 for OPAMP3 Enable
pub fn opa3pd(&self) -> OPA3PD_R[src]
Bit 16 - OPAMP3 power down
pub fn opa2lpm(&self) -> OPA2LPM_R[src]
Bit 15 - OPAMP2 low power mode
pub fn opa2cal_h(&self) -> OPA2CAL_H_R[src]
Bit 14 - OPAMP2 offset calibration for N differential pair
pub fn opa2cal_l(&self) -> OPA2CAL_L_R[src]
Bit 13 - OPAMP2 offset Calibration for P differential pair
pub fn s6sel2(&self) -> S6SEL2_R[src]
Bit 12 - Switch 6 for OPAMP2 enable
pub fn s5sel2(&self) -> S5SEL2_R[src]
Bit 11 - Switch 5 for OPAMP2 enable
pub fn s4sel2(&self) -> S4SEL2_R[src]
Bit 10 - Switch 4 for OPAMP2 enable
pub fn s3sel2(&self) -> S3SEL2_R[src]
Bit 9 - Switch 3 for OPAMP2 enable
pub fn opa2pd(&self) -> OPA2PD_R[src]
Bit 8 - OPAMP2 power down
pub fn opa1lpm(&self) -> OPA1LPM_R[src]
Bit 7 - OPAMP1 low power mode
pub fn opa1cal_h(&self) -> OPA1CAL_H_R[src]
Bit 6 - OPAMP1 offset calibration for N differential pair
pub fn opa1cal_l(&self) -> OPA1CAL_L_R[src]
Bit 5 - OPAMP1 offset calibration for P differential pair
pub fn s6sel1(&self) -> S6SEL1_R[src]
Bit 4 - Switch 6 for OPAMP1 enable
pub fn s5sel1(&self) -> S5SEL1_R[src]
Bit 3 - Switch 5 for OPAMP1 enable
pub fn s4sel1(&self) -> S4SEL1_R[src]
Bit 2 - Switch 4 for OPAMP1 enable
pub fn s3sel1(&self) -> S3SEL1_R[src]
Bit 1 - Switch 3 for OPAMP1 enable
pub fn opa1pd(&self) -> OPA1PD_R[src]
Bit 0 - OPAMP1 power down
impl R<u32, Reg<u32, _OTR>>[src]
pub fn ot_user(&self) -> OT_USER_R[src]
Bit 31 - Select user or factory trimming value
pub fn ao3_opt_offset_trim(&self) -> AO3_OPT_OFFSET_TRIM_R[src]
Bits 20:29 - OPAMP3, 10-bit offset trim value for normal mode
pub fn ao2_opt_offset_trim(&self) -> AO2_OPT_OFFSET_TRIM_R[src]
Bits 10:19 - OPAMP2, 10-bit offset trim value for normal mode
pub fn ao1_opt_offset_trim(&self) -> AO1_OPT_OFFSET_TRIM_R[src]
Bits 0:9 - OPAMP1, 10-bit offset trim value for normal mode
impl R<u32, Reg<u32, _LPOTR>>[src]
pub fn ao3_opt_offset_trim_lp(&self) -> AO3_OPT_OFFSET_TRIM_LP_R[src]
Bits 20:29 - OPAMP3, 10-bit offset trim value for low power mode
pub fn ao2_opt_offset_trim_lp(&self) -> AO2_OPT_OFFSET_TRIM_LP_R[src]
Bits 10:19 - OPAMP2, 10-bit offset trim value for low power mode
pub fn ao1_opt_offset_trim_lp(&self) -> AO1_OPT_OFFSET_TRIM_LP_R[src]
Bits 0:9 - OPAMP1, 10-bit offset trim value for low power mode
impl R<bool, PDDS_A>[src]
pub fn variant(&self) -> PDDS_A[src]
Get enumerated values variant
pub fn is_stop_mode(&self) -> bool[src]
Checks if the value of the field is STOP_MODE
pub fn is_standby_mode(&self) -> bool[src]
Checks if the value of the field is STANDBY_MODE
impl R<u32, Reg<u32, _CR>>[src]
pub fn lprun(&self) -> LPRUN_R[src]
Bit 14 - Low power run mode
pub fn vos(&self) -> VOS_R[src]
Bits 11:12 - Voltage scaling range selection
pub fn fwu(&self) -> FWU_R[src]
Bit 10 - Fast wakeup
pub fn ulp(&self) -> ULP_R[src]
Bit 9 - Ultralow power mode
pub fn dbp(&self) -> DBP_R[src]
Bit 8 - Disable backup domain write protection
pub fn pls(&self) -> PLS_R[src]
Bits 5:7 - PVD level selection
pub fn pvde(&self) -> PVDE_R[src]
Bit 4 - Power voltage detector enable
pub fn csbf(&self) -> CSBF_R[src]
Bit 3 - Clear standby flag
pub fn cwuf(&self) -> CWUF_R[src]
Bit 2 - Clear wakeup flag
pub fn pdds(&self) -> PDDS_R[src]
Bit 1 - Power down deepsleep
pub fn lpsdsr(&self) -> LPSDSR_R[src]
Bit 0 - Low-power deep sleep
impl R<u32, Reg<u32, _CSR>>[src]
pub fn ewup3(&self) -> EWUP3_R[src]
Bit 10 - Enable WKUP pin 3
pub fn ewup2(&self) -> EWUP2_R[src]
Bit 9 - Enable WKUP pin 2
pub fn ewup1(&self) -> EWUP1_R[src]
Bit 8 - Enable WKUP pin 1
pub fn reglpf(&self) -> REGLPF_R[src]
Bit 5 - Regulator LP flag
pub fn vosf(&self) -> VOSF_R[src]
Bit 4 - Voltage Scaling select flag
pub fn vrefintrdyf(&self) -> VREFINTRDYF_R[src]
Bit 3 - Internal voltage reference (VREFINT) ready flag
pub fn pvdo(&self) -> PVDO_R[src]
Bit 2 - PVD output
pub fn sbf(&self) -> SBF_R[src]
Bit 1 - Standby flag
pub fn wuf(&self) -> WUF_R[src]
Bit 0 - Wakeup flag
impl R<bool, CSSON_A>[src]
pub fn variant(&self) -> CSSON_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, PLLRDY_A>[src]
pub fn variant(&self) -> PLLRDY_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, HSEBYP_A>[src]
pub fn variant(&self) -> HSEBYP_A[src]
Get enumerated values variant
pub fn is_not_bypassed(&self) -> bool[src]
Checks if the value of the field is NOTBYPASSED
pub fn is_bypassed(&self) -> bool[src]
Checks if the value of the field is BYPASSED
impl R<bool, HSERDY_A>[src]
pub fn variant(&self) -> HSERDY_A[src]
Get enumerated values variant
pub fn is_not_ready(&self) -> bool[src]
Checks if the value of the field is NOTREADY
pub fn is_ready(&self) -> bool[src]
Checks if the value of the field is READY
impl R<u8, RTCPRE_A>[src]
pub fn variant(&self) -> RTCPRE_A[src]
Get enumerated values variant
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
pub fn is_div8(&self) -> bool[src]
Checks if the value of the field is DIV8
pub fn is_div16(&self) -> bool[src]
Checks if the value of the field is DIV16
impl R<u32, Reg<u32, _CR>>[src]
pub fn csson(&self) -> CSSON_R[src]
Bit 28 - Clock security system enable
pub fn pllrdy(&self) -> PLLRDY_R[src]
Bit 25 - PLL clock ready flag
pub fn pllon(&self) -> PLLON_R[src]
Bit 24 - PLL enable
pub fn hsebyp(&self) -> HSEBYP_R[src]
Bit 18 - HSE clock bypass
pub fn hserdy(&self) -> HSERDY_R[src]
Bit 17 - HSE clock ready flag
pub fn hseon(&self) -> HSEON_R[src]
Bit 16 - HSE clock enable
pub fn msirdy(&self) -> MSIRDY_R[src]
Bit 9 - MSI clock ready flag
pub fn msion(&self) -> MSION_R[src]
Bit 8 - MSI clock enable
pub fn hsirdy(&self) -> HSIRDY_R[src]
Bit 1 - Internal high-speed clock ready flag
pub fn hsion(&self) -> HSION_R[src]
Bit 0 - Internal high-speed clock enable
pub fn rtcpre(&self) -> RTCPRE_R[src]
Bits 29:30 - TC/LCD prescaler
impl R<u32, Reg<u32, _ICSCR>>[src]
pub fn msitrim(&self) -> MSITRIM_R[src]
Bits 24:31 - MSI clock trimming
pub fn msical(&self) -> MSICAL_R[src]
Bits 16:23 - MSI clock calibration
pub fn msirange(&self) -> MSIRANGE_R[src]
Bits 13:15 - MSI clock ranges
pub fn hsitrim(&self) -> HSITRIM_R[src]
Bits 8:12 - High speed internal clock trimming
pub fn hsical(&self) -> HSICAL_R[src]
Bits 0:7 - nternal high speed clock calibration
impl R<u8, MCOPRE_A>[src]
pub fn variant(&self) -> Variant<u8, MCOPRE_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
pub fn is_div8(&self) -> bool[src]
Checks if the value of the field is DIV8
pub fn is_div16(&self) -> bool[src]
Checks if the value of the field is DIV16
impl R<u8, MCOSEL_A>[src]
pub fn variant(&self) -> MCOSEL_A[src]
Get enumerated values variant
pub fn is_no_clock(&self) -> bool[src]
Checks if the value of the field is NOCLOCK
pub fn is_sysclk(&self) -> bool[src]
Checks if the value of the field is SYSCLK
pub fn is_hsi(&self) -> bool[src]
Checks if the value of the field is HSI
pub fn is_msi(&self) -> bool[src]
Checks if the value of the field is MSI
pub fn is_hse(&self) -> bool[src]
Checks if the value of the field is HSE
pub fn is_pll(&self) -> bool[src]
Checks if the value of the field is PLL
pub fn is_lsi(&self) -> bool[src]
Checks if the value of the field is LSI
pub fn is_lse(&self) -> bool[src]
Checks if the value of the field is LSE
impl R<u8, PLLDIV_A>[src]
pub fn variant(&self) -> Variant<u8, PLLDIV_A>[src]
Get enumerated values variant
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div3(&self) -> bool[src]
Checks if the value of the field is DIV3
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
impl R<u8, PLLMUL_A>[src]
pub fn variant(&self) -> Variant<u8, PLLMUL_A>[src]
Get enumerated values variant
pub fn is_mul3(&self) -> bool[src]
Checks if the value of the field is MUL3
pub fn is_mul4(&self) -> bool[src]
Checks if the value of the field is MUL4
pub fn is_mul6(&self) -> bool[src]
Checks if the value of the field is MUL6
pub fn is_mul8(&self) -> bool[src]
Checks if the value of the field is MUL8
pub fn is_mul12(&self) -> bool[src]
Checks if the value of the field is MUL12
pub fn is_mul16(&self) -> bool[src]
Checks if the value of the field is MUL16
pub fn is_mul24(&self) -> bool[src]
Checks if the value of the field is MUL24
pub fn is_mul32(&self) -> bool[src]
Checks if the value of the field is MUL32
pub fn is_mul48(&self) -> bool[src]
Checks if the value of the field is MUL48
impl R<bool, PLLSRC_A>[src]
pub fn variant(&self) -> PLLSRC_A[src]
Get enumerated values variant
pub fn is_hsi(&self) -> bool[src]
Checks if the value of the field is HSI
pub fn is_hse(&self) -> bool[src]
Checks if the value of the field is HSE
impl R<u8, PPRE2_A>[src]
pub fn variant(&self) -> Variant<u8, PPRE2_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
pub fn is_div8(&self) -> bool[src]
Checks if the value of the field is DIV8
pub fn is_div16(&self) -> bool[src]
Checks if the value of the field is DIV16
impl R<u8, HPRE_A>[src]
pub fn variant(&self) -> Variant<u8, HPRE_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
pub fn is_div8(&self) -> bool[src]
Checks if the value of the field is DIV8
pub fn is_div16(&self) -> bool[src]
Checks if the value of the field is DIV16
pub fn is_div64(&self) -> bool[src]
Checks if the value of the field is DIV64
pub fn is_div128(&self) -> bool[src]
Checks if the value of the field is DIV128
pub fn is_div256(&self) -> bool[src]
Checks if the value of the field is DIV256
pub fn is_div512(&self) -> bool[src]
Checks if the value of the field is DIV512
impl R<u8, SWS_A>[src]
pub fn variant(&self) -> SWS_A[src]
Get enumerated values variant
pub fn is_hsi(&self) -> bool[src]
Checks if the value of the field is HSI
pub fn is_msi(&self) -> bool[src]
Checks if the value of the field is MSI
pub fn is_hse(&self) -> bool[src]
Checks if the value of the field is HSE
pub fn is_pll(&self) -> bool[src]
Checks if the value of the field is PLL
impl R<u8, SW_A>[src]
pub fn variant(&self) -> SW_A[src]
Get enumerated values variant
pub fn is_hsi(&self) -> bool[src]
Checks if the value of the field is HSI
pub fn is_msi(&self) -> bool[src]
Checks if the value of the field is MSI
pub fn is_hse(&self) -> bool[src]
Checks if the value of the field is HSE
pub fn is_pll(&self) -> bool[src]
Checks if the value of the field is PLL
impl R<u32, Reg<u32, _CFGR>>[src]
pub fn mcopre(&self) -> MCOPRE_R[src]
Bits 28:30 - Microcontroller clock output prescaler
pub fn mcosel(&self) -> MCOSEL_R[src]
Bits 24:26 - Microcontroller clock output selection
pub fn plldiv(&self) -> PLLDIV_R[src]
Bits 22:23 - PLL output division
pub fn pllmul(&self) -> PLLMUL_R[src]
Bits 18:21 - PLL multiplication factor
pub fn pllsrc(&self) -> PLLSRC_R[src]
Bit 16 - PLL entry clock source
pub fn ppre2(&self) -> PPRE2_R[src]
Bits 11:13 - APB high-speed prescaler (APB2)
pub fn ppre1(&self) -> PPRE1_R[src]
Bits 8:10 - APB low-speed prescaler (APB1)
pub fn hpre(&self) -> HPRE_R[src]
Bits 4:7 - AHB prescaler
pub fn sws(&self) -> SWS_R[src]
Bits 2:3 - System clock switch status
pub fn sw(&self) -> SW_R[src]
Bits 0:1 - System clock switch
impl R<bool, MSIRDYIE_A>[src]
pub fn variant(&self) -> MSIRDYIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CSSF_A>[src]
pub fn variant(&self) -> CSSF_A[src]
Get enumerated values variant
pub fn is_not_interupted(&self) -> bool[src]
Checks if the value of the field is NOTINTERUPTED
pub fn is_interupted(&self) -> bool[src]
Checks if the value of the field is INTERUPTED
impl R<bool, MSIRDYF_A>[src]
pub fn variant(&self) -> MSIRDYF_A[src]
Get enumerated values variant
pub fn is_not_stable(&self) -> bool[src]
Checks if the value of the field is NOTSTABLE
pub fn is_stable(&self) -> bool[src]
Checks if the value of the field is STABLE
impl R<bool, LSECSSF_A>[src]
pub fn variant(&self) -> LSECSSF_A[src]
Get enumerated values variant
pub fn is_no_failure(&self) -> bool[src]
Checks if the value of the field is NOFAILURE
pub fn is_failure(&self) -> bool[src]
Checks if the value of the field is FAILURE
impl R<bool, LSECSSIE_A>[src]
pub fn variant(&self) -> LSECSSIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CIR>>[src]
pub fn msirdyie(&self) -> MSIRDYIE_R[src]
Bit 13 - MSI ready interrupt enable
pub fn pllrdyie(&self) -> PLLRDYIE_R[src]
Bit 12 - PLL ready interrupt enable
pub fn hserdyie(&self) -> HSERDYIE_R[src]
Bit 11 - HSE ready interrupt enable
pub fn hsirdyie(&self) -> HSIRDYIE_R[src]
Bit 10 - HSI ready interrupt enable
pub fn lserdyie(&self) -> LSERDYIE_R[src]
Bit 9 - LSE ready interrupt enable
pub fn lsirdyie(&self) -> LSIRDYIE_R[src]
Bit 8 - LSI ready interrupt enable
pub fn cssf(&self) -> CSSF_R[src]
Bit 7 - Clock security system interrupt flag
pub fn msirdyf(&self) -> MSIRDYF_R[src]
Bit 5 - MSI ready interrupt flag
pub fn pllrdyf(&self) -> PLLRDYF_R[src]
Bit 4 - PLL ready interrupt flag
pub fn hserdyf(&self) -> HSERDYF_R[src]
Bit 3 - HSE ready interrupt flag
pub fn hsirdyf(&self) -> HSIRDYF_R[src]
Bit 2 - HSI ready interrupt flag
pub fn lserdyf(&self) -> LSERDYF_R[src]
Bit 1 - LSE ready interrupt flag
pub fn lsirdyf(&self) -> LSIRDYF_R[src]
Bit 0 - LSI ready interrupt flag
pub fn lsecssf(&self) -> LSECSSF_R[src]
Bit 6 - LSE Clock security system interrupt flag
pub fn lsecssie(&self) -> LSECSSIE_R[src]
Bit 14 - LSE clock security system interrupt enable
impl R<bool, FSMCRST_A>[src]
pub fn variant(&self) -> Variant<bool, FSMCRST_A>[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<u32, Reg<u32, _AHBRSTR>>[src]
pub fn fsmcrst(&self) -> FSMCRST_R[src]
Bit 30 - FSMC reset
pub fn dma2rst(&self) -> DMA2RST_R[src]
Bit 25 - DMA2 reset
pub fn dma1rst(&self) -> DMA1RST_R[src]
Bit 24 - DMA1 reset
pub fn flitfrst(&self) -> FLITFRST_R[src]
Bit 15 - FLITF reset
pub fn crcrst(&self) -> CRCRST_R[src]
Bit 12 - CRC reset
pub fn gpiogrst(&self) -> GPIOGRST_R[src]
Bit 7 - IO port G reset
pub fn gpiofrst(&self) -> GPIOFRST_R[src]
Bit 6 - IO port F reset
pub fn gpiohrst(&self) -> GPIOHRST_R[src]
Bit 5 - IO port H reset
pub fn gpioerst(&self) -> GPIOERST_R[src]
Bit 4 - IO port E reset
pub fn gpiodrst(&self) -> GPIODRST_R[src]
Bit 3 - IO port D reset
pub fn gpiocrst(&self) -> GPIOCRST_R[src]
Bit 2 - IO port C reset
pub fn gpiobrst(&self) -> GPIOBRST_R[src]
Bit 1 - IO port B reset
pub fn gpioarst(&self) -> GPIOARST_R[src]
Bit 0 - IO port A reset
impl R<bool, USART1RST_A>[src]
pub fn variant(&self) -> Variant<bool, USART1RST_A>[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<u32, Reg<u32, _APB2RSTR>>[src]
pub fn usart1rst(&self) -> USART1RST_R[src]
Bit 14 - USART1RST
pub fn spi1rst(&self) -> SPI1RST_R[src]
Bit 12 - SPI1RST
pub fn sdiorst(&self) -> SDIORST_R[src]
Bit 11 - SDIORST
pub fn adc1rst(&self) -> ADC1RST_R[src]
Bit 9 - ADC1RST
pub fn tm11rst(&self) -> TM11RST_R[src]
Bit 4 - TM11RST
pub fn tm10rst(&self) -> TM10RST_R[src]
Bit 3 - TM10RST
pub fn tim9rst(&self) -> TIM9RST_R[src]
Bit 2 - TIM9RST
pub fn syscfgrst(&self) -> SYSCFGRST_R[src]
Bit 0 - SYSCFGRST
impl R<bool, COMPRST_A>[src]
pub fn variant(&self) -> Variant<bool, COMPRST_A>[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<u32, Reg<u32, _APB1RSTR>>[src]
pub fn comprst(&self) -> COMPRST_R[src]
Bit 31 - COMP interface reset
pub fn dacrst(&self) -> DACRST_R[src]
Bit 29 - DAC interface reset
pub fn pwrrst(&self) -> PWRRST_R[src]
Bit 28 - Power interface reset
pub fn usbrst(&self) -> USBRST_R[src]
Bit 23 - USB reset
pub fn i2c2rst(&self) -> I2C2RST_R[src]
Bit 22 - I2C 2 reset
pub fn i2c1rst(&self) -> I2C1RST_R[src]
Bit 21 - I2C 1 reset
pub fn uart5rst(&self) -> UART5RST_R[src]
Bit 20 - UART 5 reset
pub fn uart4rst(&self) -> UART4RST_R[src]
Bit 19 - UART 4 reset
pub fn usart3rst(&self) -> USART3RST_R[src]
Bit 18 - USART 3 reset
pub fn usart2rst(&self) -> USART2RST_R[src]
Bit 17 - USART 2 reset
pub fn spi3rst(&self) -> SPI3RST_R[src]
Bit 15 - SPI 3 reset
pub fn spi2rst(&self) -> SPI2RST_R[src]
Bit 14 - SPI 2 reset
pub fn wwdrst(&self) -> WWDRST_R[src]
Bit 11 - Window watchdog reset
pub fn lcdrst(&self) -> LCDRST_R[src]
Bit 9 - LCD reset
pub fn tim7rst(&self) -> TIM7RST_R[src]
Bit 5 - Timer 7 reset
pub fn tim6rst(&self) -> TIM6RST_R[src]
Bit 4 - Timer 6reset
pub fn tim5rst(&self) -> TIM5RST_R[src]
Bit 3 - Timer 5 reset
pub fn tim4rst(&self) -> TIM4RST_R[src]
Bit 2 - Timer 4 reset
pub fn tim3rst(&self) -> TIM3RST_R[src]
Bit 1 - Timer 3 reset
pub fn tim2rst(&self) -> TIM2RST_R[src]
Bit 0 - Timer 2 reset
impl R<bool, FSMCEN_A>[src]
pub fn variant(&self) -> FSMCEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _AHBENR>>[src]
pub fn fsmcen(&self) -> FSMCEN_R[src]
Bit 30 - FSMCEN
pub fn dma2en(&self) -> DMA2EN_R[src]
Bit 25 - DMA2 clock enable
pub fn dma1en(&self) -> DMA1EN_R[src]
Bit 24 - DMA1 clock enable
pub fn flitfen(&self) -> FLITFEN_R[src]
Bit 15 - FLITF clock enable
pub fn crcen(&self) -> CRCEN_R[src]
Bit 12 - CRC clock enable
pub fn gpiopgen(&self) -> GPIOPGEN_R[src]
Bit 7 - IO port G clock enable
pub fn gpiopfen(&self) -> GPIOPFEN_R[src]
Bit 6 - IO port F clock enable
pub fn gpiophen(&self) -> GPIOPHEN_R[src]
Bit 5 - IO port H clock enable
pub fn gpiopeen(&self) -> GPIOPEEN_R[src]
Bit 4 - IO port E clock enable
pub fn gpiopden(&self) -> GPIOPDEN_R[src]
Bit 3 - IO port D clock enable
pub fn gpiopcen(&self) -> GPIOPCEN_R[src]
Bit 2 - IO port C clock enable
pub fn gpiopben(&self) -> GPIOPBEN_R[src]
Bit 1 - IO port B clock enable
pub fn gpiopaen(&self) -> GPIOPAEN_R[src]
Bit 0 - IO port A clock enable
impl R<bool, USART1EN_A>[src]
pub fn variant(&self) -> USART1EN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _APB2ENR>>[src]
pub fn usart1en(&self) -> USART1EN_R[src]
Bit 14 - USART1 clock enable
pub fn spi1en(&self) -> SPI1EN_R[src]
Bit 12 - SPI 1 clock enable
pub fn sdioen(&self) -> SDIOEN_R[src]
Bit 11 - SDIO clock enable
pub fn adc1en(&self) -> ADC1EN_R[src]
Bit 9 - ADC1 interface clock enable
pub fn tim11en(&self) -> TIM11EN_R[src]
Bit 4 - TIM11 timer clock enable
pub fn tim10en(&self) -> TIM10EN_R[src]
Bit 3 - TIM10 timer clock enable
pub fn tim9en(&self) -> TIM9EN_R[src]
Bit 2 - TIM9 timer clock enable
pub fn syscfgen(&self) -> SYSCFGEN_R[src]
Bit 0 - System configuration controller clock enable
impl R<bool, COMPEN_A>[src]
pub fn variant(&self) -> COMPEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _APB1ENR>>[src]
pub fn compen(&self) -> COMPEN_R[src]
Bit 31 - COMP interface clock enable
pub fn dacen(&self) -> DACEN_R[src]
Bit 29 - DAC interface clock enable
pub fn pwren(&self) -> PWREN_R[src]
Bit 28 - Power interface clock enable
pub fn usben(&self) -> USBEN_R[src]
Bit 23 - USB clock enable
pub fn i2c2en(&self) -> I2C2EN_R[src]
Bit 22 - I2C 2 clock enable
pub fn i2c1en(&self) -> I2C1EN_R[src]
Bit 21 - I2C 1 clock enable
pub fn usart5en(&self) -> USART5EN_R[src]
Bit 20 - UART 5 clock enable
pub fn usart4en(&self) -> USART4EN_R[src]
Bit 19 - UART 4 clock enable
pub fn usart3en(&self) -> USART3EN_R[src]
Bit 18 - USART 3 clock enable
pub fn usart2en(&self) -> USART2EN_R[src]
Bit 17 - USART 2 clock enable
pub fn spi3en(&self) -> SPI3EN_R[src]
Bit 15 - SPI 3 clock enable
pub fn spi2en(&self) -> SPI2EN_R[src]
Bit 14 - SPI 2 clock enable
pub fn wwdgen(&self) -> WWDGEN_R[src]
Bit 11 - Window watchdog clock enable
pub fn lcden(&self) -> LCDEN_R[src]
Bit 9 - LCD clock enable
pub fn tim7en(&self) -> TIM7EN_R[src]
Bit 5 - Timer 7 clock enable
pub fn tim6en(&self) -> TIM6EN_R[src]
Bit 4 - Timer 6 clock enable
pub fn tim5en(&self) -> TIM5EN_R[src]
Bit 3 - Timer 5 clock enable
pub fn tim4en(&self) -> TIM4EN_R[src]
Bit 2 - Timer 4 clock enable
pub fn tim3en(&self) -> TIM3EN_R[src]
Bit 1 - Timer 3 clock enable
pub fn tim2en(&self) -> TIM2EN_R[src]
Bit 0 - Timer 2 clock enable
impl R<bool, DMA2LPEN_A>[src]
pub fn variant(&self) -> DMA2LPEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _AHBLPENR>>[src]
pub fn dma2lpen(&self) -> DMA2LPEN_R[src]
Bit 25 - DMA2 clock enable during Sleep mode
pub fn dma1lpen(&self) -> DMA1LPEN_R[src]
Bit 24 - DMA1 clock enable during Sleep mode
pub fn sramlpen(&self) -> SRAMLPEN_R[src]
Bit 16 - SRAM clock enable during Sleep mode
pub fn flitflpen(&self) -> FLITFLPEN_R[src]
Bit 15 - FLITF clock enable during Sleep mode
pub fn crclpen(&self) -> CRCLPEN_R[src]
Bit 12 - CRC clock enable during Sleep mode
pub fn gpioglpen(&self) -> GPIOGLPEN_R[src]
Bit 7 - IO port G clock enable during Sleep mode
pub fn gpioflpen(&self) -> GPIOFLPEN_R[src]
Bit 6 - IO port F clock enable during Sleep mode
pub fn gpiohlpen(&self) -> GPIOHLPEN_R[src]
Bit 5 - IO port H clock enable during Sleep mode
pub fn gpioelpen(&self) -> GPIOELPEN_R[src]
Bit 4 - IO port E clock enable during Sleep mode
pub fn gpiodlpen(&self) -> GPIODLPEN_R[src]
Bit 3 - IO port D clock enable during Sleep mode
pub fn gpioclpen(&self) -> GPIOCLPEN_R[src]
Bit 2 - IO port C clock enable during Sleep mode
pub fn gpioblpen(&self) -> GPIOBLPEN_R[src]
Bit 1 - IO port B clock enable during Sleep mode
pub fn gpioalpen(&self) -> GPIOALPEN_R[src]
Bit 0 - IO port A clock enable during Sleep mode
pub fn fsmclpen(&self) -> FSMCLPEN_R[src]
Bit 30 - FSMC clock enable during Sleep mode
pub fn aeslpen(&self) -> AESLPEN_R[src]
Bit 27 - AES clock enable during Sleep mode
impl R<bool, USART1LPEN_A>[src]
pub fn variant(&self) -> USART1LPEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _APB2LPENR>>[src]
pub fn usart1lpen(&self) -> USART1LPEN_R[src]
Bit 14 - USART1 clock enable during Sleep mode
pub fn spi1lpen(&self) -> SPI1LPEN_R[src]
Bit 12 - SPI 1 clock enable during Sleep mode
pub fn sdiolpen(&self) -> SDIOLPEN_R[src]
Bit 11 - SDIO clock enable during Sleep mode
pub fn adc1lpen(&self) -> ADC1LPEN_R[src]
Bit 9 - ADC1 interface clock enable during Sleep mode
pub fn tim11lpen(&self) -> TIM11LPEN_R[src]
Bit 4 - TIM11 timer clock enable during Sleep mode
pub fn tim10lpen(&self) -> TIM10LPEN_R[src]
Bit 3 - TIM10 timer clock enable during Sleep mode
pub fn tim9lpen(&self) -> TIM9LPEN_R[src]
Bit 2 - TIM9 timer clock enable during Sleep mode
pub fn syscfglpen(&self) -> SYSCFGLPEN_R[src]
Bit 0 - System configuration controller clock enable during Sleep mode
impl R<bool, COMPLPEN_A>[src]
pub fn variant(&self) -> COMPLPEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _APB1LPENR>>[src]
pub fn complpen(&self) -> COMPLPEN_R[src]
Bit 31 - COMP interface clock enable during Sleep mode
pub fn daclpen(&self) -> DACLPEN_R[src]
Bit 29 - DAC interface clock enable during Sleep mode
pub fn pwrlpen(&self) -> PWRLPEN_R[src]
Bit 28 - Power interface clock enable during Sleep mode
pub fn usblpen(&self) -> USBLPEN_R[src]
Bit 23 - USB clock enable during Sleep mode
pub fn i2c2lpen(&self) -> I2C2LPEN_R[src]
Bit 22 - I2C 2 clock enable during Sleep mode
pub fn i2c1lpen(&self) -> I2C1LPEN_R[src]
Bit 21 - I2C 1 clock enable during Sleep mode
pub fn usart3lpen(&self) -> USART3LPEN_R[src]
Bit 18 - USART 3 clock enable during Sleep mode
pub fn usart2lpen(&self) -> USART2LPEN_R[src]
Bit 17 - USART 2 clock enable during Sleep mode
pub fn spi2lpen(&self) -> SPI2LPEN_R[src]
Bit 14 - SPI 2 clock enable during Sleep mode
pub fn wwdglpen(&self) -> WWDGLPEN_R[src]
Bit 11 - Window watchdog clock enable during Sleep mode
pub fn lcdlpen(&self) -> LCDLPEN_R[src]
Bit 9 - LCD clock enable during Sleep mode
pub fn tim7lpen(&self) -> TIM7LPEN_R[src]
Bit 5 - Timer 7 clock enable during Sleep mode
pub fn tim6lpen(&self) -> TIM6LPEN_R[src]
Bit 4 - Timer 6 clock enable during Sleep mode
pub fn tim4lpen(&self) -> TIM4LPEN_R[src]
Bit 2 - Timer 4 clock enable during Sleep mode
pub fn tim3lpen(&self) -> TIM3LPEN_R[src]
Bit 1 - Timer 3 clock enable during Sleep mode
pub fn tim2lpen(&self) -> TIM2LPEN_R[src]
Bit 0 - Timer 2 clock enable during Sleep mode
pub fn uart5lpen(&self) -> UART5LPEN_R[src]
Bit 20 - USART 5 clock enable during Sleep mode
pub fn uart4lpen(&self) -> UART4LPEN_R[src]
Bit 19 - USART 4 clock enable during Sleep mode
pub fn spi3lpen(&self) -> SPI3LPEN_R[src]
Bit 15 - SPI 3 clock enable during Sleep mode
pub fn tim5lpen(&self) -> TIM5LPEN_R[src]
Bit 3 - Timer 5 clock enable during Sleep mode
impl R<bool, LPWRSTF_A>[src]
pub fn variant(&self) -> LPWRSTF_A[src]
Get enumerated values variant
pub fn is_no_reset(&self) -> bool[src]
Checks if the value of the field is NORESET
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<bool, RMVF_A>[src]
pub fn variant(&self) -> Variant<bool, RMVF_A>[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
impl R<bool, RTCRST_A>[src]
pub fn variant(&self) -> Variant<bool, RTCRST_A>[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<u32, Reg<u32, _CSR>>[src]
pub fn lpwrstf(&self) -> LPWRSTF_R[src]
Bit 31 - Low-power reset flag
pub fn wwdgrstf(&self) -> WWDGRSTF_R[src]
Bit 30 - Window watchdog reset flag
pub fn iwdgrstf(&self) -> IWDGRSTF_R[src]
Bit 29 - Independent watchdog reset flag
pub fn sftrstf(&self) -> SFTRSTF_R[src]
Bit 28 - Software reset flag
pub fn porrstf(&self) -> PORRSTF_R[src]
Bit 27 - POR/PDR reset flag
pub fn pinrstf(&self) -> PINRSTF_R[src]
Bit 26 - PIN reset flag
pub fn rmvf(&self) -> RMVF_R[src]
Bit 24 - Remove reset flag
pub fn rtcrst(&self) -> RTCRST_R[src]
Bit 23 - RTC software reset
pub fn rtcen(&self) -> RTCEN_R[src]
Bit 22 - RTC clock enable
pub fn rtcsel(&self) -> RTCSEL_R[src]
Bits 16:17 - RTC and LCD clock source selection
pub fn lsebyp(&self) -> LSEBYP_R[src]
Bit 10 - External low-speed oscillator bypass
pub fn lserdy(&self) -> LSERDY_R[src]
Bit 9 - External low-speed oscillator ready
pub fn lseon(&self) -> LSEON_R[src]
Bit 8 - External low-speed oscillator enable
pub fn lsirdy(&self) -> LSIRDY_R[src]
Bit 1 - Internal low-speed oscillator ready
pub fn lsion(&self) -> LSION_R[src]
Bit 0 - Internal low-speed oscillator enable
pub fn oblrstf(&self) -> OBLRSTF_R[src]
Bit 25 - Options bytes loading reset flag
pub fn lsecssd(&self) -> LSECSSD_R[src]
Bit 12 - CSS on LSE failure Detection
pub fn lsecsson(&self) -> LSECSSON_R[src]
Bit 11 - CSS on LSE enable
impl R<u32, Reg<u32, _ICR>>[src]
pub fn ic4(&self) -> IC4_R[src]
Bit 21 - IC4
pub fn ic3(&self) -> IC3_R[src]
Bit 20 - IC3
pub fn ic2(&self) -> IC2_R[src]
Bit 19 - IC2
pub fn ic1(&self) -> IC1_R[src]
Bit 18 - IC1
pub fn tim(&self) -> TIM_R[src]
Bits 16:17 - Timer select bits
pub fn ic4ios(&self) -> IC4IOS_R[src]
Bits 12:15 - Input capture 4 select bits
pub fn ic3ios(&self) -> IC3IOS_R[src]
Bits 8:11 - Input capture 3 select bits
pub fn ic2ios(&self) -> IC2IOS_R[src]
Bits 4:7 - Input capture 2 select bits
pub fn ic1ios(&self) -> IC1IOS_R[src]
Bits 0:3 - Input capture 1 select bits
impl R<u32, Reg<u32, _ASCR1>>[src]
pub fn scm(&self) -> SCM_R[src]
Bit 31 - Switch control mode
pub fn ch30gr11_4(&self) -> CH30GR11_4_R[src]
Bit 30 - Analog switch control
pub fn ch29gr11_3(&self) -> CH29GR11_3_R[src]
Bit 29 - Analog switch control
pub fn ch28gr11_2(&self) -> CH28GR11_2_R[src]
Bit 28 - Analog switch control
pub fn ch27gr11_1(&self) -> CH27GR11_1_R[src]
Bit 27 - Analog switch control
pub fn vcomp(&self) -> VCOMP_R[src]
Bit 26 - ADC analog switch selection for internal node to comparator 1
pub fn ch25(&self) -> CH25_R[src]
Bit 25 - Analog I/O switch control of channel CH25
pub fn ch24(&self) -> CH24_R[src]
Bit 24 - Analog I/O switch control of channel CH24
pub fn ch23(&self) -> CH23_R[src]
Bit 23 - Analog I/O switch control of channel CH23
pub fn ch22(&self) -> CH22_R[src]
Bit 22 - Analog I/O switch control of channel CH22
pub fn ch21gr7_4(&self) -> CH21GR7_4_R[src]
Bit 21 - Analog switch control
pub fn ch20gr7_3(&self) -> CH20GR7_3_R[src]
Bit 20 - Analog switch control
pub fn ch19gr7_2(&self) -> CH19GR7_2_R[src]
Bit 19 - Analog switch control
pub fn ch18gr7_1(&self) -> CH18GR7_1_R[src]
Bit 18 - Analog switch control
pub fn ch31gr7_1(&self) -> CH31GR7_1_R[src]
Bit 16 - Analog switch control
pub fn ch15gr9_2(&self) -> CH15GR9_2_R[src]
Bit 15 - Analog switch control
pub fn ch14gr9_1(&self) -> CH14GR9_1_R[src]
Bit 14 - Analog switch control
pub fn ch13gr8_4(&self) -> CH13GR8_4_R[src]
Bit 13 - Analog switch control
pub fn ch12gr8_3(&self) -> CH12GR8_3_R[src]
Bit 12 - Analog switch control
pub fn ch11gr8_2(&self) -> CH11GR8_2_R[src]
Bit 11 - Analog switch control
pub fn ch10gr8_1(&self) -> CH10GR8_1_R[src]
Bit 10 - Analog switch control
pub fn ch9gr3_2(&self) -> CH9GR3_2_R[src]
Bit 9 - Analog switch control
pub fn ch8gr3_1(&self) -> CH8GR3_1_R[src]
Bit 8 - Analog switch control
pub fn ch7gr2_2(&self) -> CH7GR2_2_R[src]
Bit 7 - Analog switch control
pub fn ch6gr2_1(&self) -> CH6GR2_1_R[src]
Bit 6 - Analog switch control
pub fn comp1_sw1(&self) -> COMP1_SW1_R[src]
Bit 5 - Comparator 1 analog switch
pub fn ch31gr11_5(&self) -> CH31GR11_5_R[src]
Bit 4 - Analog switch control
pub fn ch3gr1_4(&self) -> CH3GR1_4_R[src]
Bit 3 - Analog switch control
pub fn ch2gr1_3(&self) -> CH2GR1_3_R[src]
Bit 2 - Analog switch control
pub fn ch1gr1_2(&self) -> CH1GR1_2_R[src]
Bit 1 - Analog switch control
pub fn ch0gr1_1(&self) -> CH0GR1_1_R[src]
Bit 0 - Analog switch control
impl R<u32, Reg<u32, _ASCR2>>[src]
pub fn gr5_4(&self) -> GR5_4_R[src]
Bit 29 - GR5_4 analog switch control
pub fn gr6_4(&self) -> GR6_4_R[src]
Bit 28 - GR6_4 analog switch control
pub fn gr6_3(&self) -> GR6_3_R[src]
Bit 27 - GR6_3 analog switch control
pub fn gr7_7(&self) -> GR7_7_R[src]
Bit 26 - GR7_7 analog switch control
pub fn gr7_6(&self) -> GR7_6_R[src]
Bit 25 - GR7_6 analog switch control
pub fn gr7_5(&self) -> GR7_5_R[src]
Bit 24 - GR7_5 analog switch control
pub fn gr2_5(&self) -> GR2_5_R[src]
Bit 23 - GR2_5 analog switch control
pub fn gr2_4(&self) -> GR2_4_R[src]
Bit 22 - GR2_4 analog switch control
pub fn gr2_3(&self) -> GR2_3_R[src]
Bit 21 - GR2_3 analog switch control
pub fn gr9_4(&self) -> GR9_4_R[src]
Bit 20 - GR9_4 analog switch control
pub fn gr9_3(&self) -> GR9_3_R[src]
Bit 19 - GR9_3 analog switch control
pub fn gr3_5(&self) -> GR3_5_R[src]
Bit 18 - GR3_5 analog switch control
pub fn gr3_4(&self) -> GR3_4_R[src]
Bit 17 - GR3_4 analog switch control
pub fn gr3_3(&self) -> GR3_3_R[src]
Bit 16 - GR3_3 analog switch control
pub fn gr4_3(&self) -> GR4_3_R[src]
Bit 11 - GR4_3 analog switch control
pub fn gr4_2(&self) -> GR4_2_R[src]
Bit 10 - GR4_2 analog switch control
pub fn gr4_1(&self) -> GR4_1_R[src]
Bit 9 - GR4_1 analog switch control
pub fn gr5_3(&self) -> GR5_3_R[src]
Bit 8 - GR5_3 analog switch control
pub fn gr5_2(&self) -> GR5_2_R[src]
Bit 7 - GR5_2 analog switch control
pub fn gr5_1(&self) -> GR5_1_R[src]
Bit 6 - GR5_1 analog switch control
pub fn gr6_2(&self) -> GR6_2_R[src]
Bit 5 - GR6_2 analog switch control
pub fn gr6_1(&self) -> GR6_1_R[src]
Bit 4 - GR6_1 analog switch control
pub fn gr10_4(&self) -> GR10_4_R[src]
Bit 3 - GR10_4 analog switch control
pub fn gr10_3(&self) -> GR10_3_R[src]
Bit 2 - GR10_3 analog switch control
pub fn gr10_2(&self) -> GR10_2_R[src]
Bit 1 - GR10_2 analog switch control
pub fn gr10_1(&self) -> GR10_1_R[src]
Bit 0 - GR10_1 analog switch control
impl R<u32, Reg<u32, _HYSCR1>>[src]
pub fn pb(&self) -> PB_R[src]
Bits 16:31 - Port B hysteresis control on/off
pub fn pa(&self) -> PA_R[src]
Bits 0:15 - Port A hysteresis control on/off
impl R<u32, Reg<u32, _HYSCR2>>[src]
pub fn pd(&self) -> PD_R[src]
Bits 16:31 - Port D hysteresis control on/off
pub fn pc(&self) -> PC_R[src]
Bits 0:15 - Port C hysteresis control on/off
impl R<u32, Reg<u32, _HYSCR3>>[src]
pub fn pf(&self) -> PF_R[src]
Bits 16:31 - Port F hysteresis control on/off
pub fn pe(&self) -> PE_R[src]
Bits 0:15 - Port E hysteresis control on/off
impl R<u32, Reg<u32, _HYSCR4>>[src]
impl R<u32, Reg<u32, _TR>>[src]
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format
impl R<u32, Reg<u32, _DR>>[src]
pub fn yt(&self) -> YT_R[src]
Bits 20:23 - Year tens in BCD format
pub fn yu(&self) -> YU_R[src]
Bits 16:19 - Year units in BCD format
pub fn wdu(&self) -> WDU_R[src]
Bits 13:15 - Week day units
pub fn mt(&self) -> MT_R[src]
Bit 12 - Month tens in BCD format
pub fn mu(&self) -> MU_R[src]
Bits 8:11 - Month units in BCD format
pub fn dt(&self) -> DT_R[src]
Bits 4:5 - Date tens in BCD format
pub fn du(&self) -> DU_R[src]
Bits 0:3 - Date units in BCD format
impl R<u32, Reg<u32, _CR>>[src]
pub fn coe(&self) -> COE_R[src]
Bit 23 - Calibration output enable
pub fn osel(&self) -> OSEL_R[src]
Bits 21:22 - Output selection
pub fn pol(&self) -> POL_R[src]
Bit 20 - Output polarity
pub fn cosel(&self) -> COSEL_R[src]
Bit 19 - Calibration output selection
pub fn bkp(&self) -> BKP_R[src]
Bit 18 - Backup
pub fn sub1h(&self) -> SUB1H_R[src]
Bit 17 - Subtract 1 hour
pub fn add1h(&self) -> ADD1H_R[src]
Bit 16 - Add 1 hour
pub fn tsie(&self) -> TSIE_R[src]
Bit 15 - Time-stamp interrupt enable
pub fn wutie(&self) -> WUTIE_R[src]
Bit 14 - Wakeup timer interrupt enable
pub fn alrbie(&self) -> ALRBIE_R[src]
Bit 13 - Alarm B interrupt enable
pub fn alraie(&self) -> ALRAIE_R[src]
Bit 12 - Alarm A interrupt enable
pub fn tse(&self) -> TSE_R[src]
Bit 11 - Time stamp enable
pub fn wute(&self) -> WUTE_R[src]
Bit 10 - Wakeup timer enable
pub fn alrbe(&self) -> ALRBE_R[src]
Bit 9 - Alarm B enable
pub fn alrae(&self) -> ALRAE_R[src]
Bit 8 - Alarm A enable
pub fn dce(&self) -> DCE_R[src]
Bit 7 - Coarse digital calibration enable
pub fn fmt(&self) -> FMT_R[src]
Bit 6 - Hour format
pub fn bypshad(&self) -> BYPSHAD_R[src]
Bit 5 - Bypass the shadow registers
pub fn refckon(&self) -> REFCKON_R[src]
Bit 4 - Reference clock detection enable
pub fn tsedge(&self) -> TSEDGE_R[src]
Bit 3 - Time-stamp event active edge
pub fn wcksel(&self) -> WCKSEL_R[src]
Bits 0:2 - WCKSEL
impl R<u32, Reg<u32, _ISR>>[src]
pub fn recalpf(&self) -> RECALPF_R[src]
Bit 16 - Recalibration pending Flag
pub fn tamp3f(&self) -> TAMP3F_R[src]
Bit 15 - TAMPER3 detection flag
pub fn tamp2f(&self) -> TAMP2F_R[src]
Bit 14 - TAMPER2 detection flag
pub fn tamp1f(&self) -> TAMP1F_R[src]
Bit 13 - Tamper detection flag
pub fn tsovf(&self) -> TSOVF_R[src]
Bit 12 - Timestamp overflow flag
pub fn tsf(&self) -> TSF_R[src]
Bit 11 - Timestamp flag
pub fn wutf(&self) -> WUTF_R[src]
Bit 10 - Wakeup timer flag
pub fn alrbf(&self) -> ALRBF_R[src]
Bit 9 - Alarm B flag
pub fn alraf(&self) -> ALRAF_R[src]
Bit 8 - Alarm A flag
pub fn init(&self) -> INIT_R[src]
Bit 7 - Initialization mode
pub fn initf(&self) -> INITF_R[src]
Bit 6 - Initialization flag
pub fn rsf(&self) -> RSF_R[src]
Bit 5 - Registers synchronization flag
pub fn inits(&self) -> INITS_R[src]
Bit 4 - Initialization status flag
pub fn shpf(&self) -> SHPF_R[src]
Bit 3 - Shift operation pending
pub fn wutwf(&self) -> WUTWF_R[src]
Bit 2 - Wakeup timer write flag
pub fn alrbwf(&self) -> ALRBWF_R[src]
Bit 1 - Alarm B write flag
pub fn alrawf(&self) -> ALRAWF_R[src]
Bit 0 - Alarm A write flag
impl R<u32, Reg<u32, _PRER>>[src]
pub fn prediv_a(&self) -> PREDIV_A_R[src]
Bits 16:22 - Asynchronous prescaler factor
pub fn prediv_s(&self) -> PREDIV_S_R[src]
Bits 0:14 - Synchronous prescaler factor
impl R<u32, Reg<u32, _WUTR>>[src]
impl R<u32, Reg<u32, _CALIBR>>[src]
pub fn dcs(&self) -> DCS_R[src]
Bit 7 - Digital calibration sign
pub fn dc(&self) -> DC_R[src]
Bits 0:4 - Digital calibration
impl R<u32, Reg<u32, _ALRMAR>>[src]
pub fn msk4(&self) -> MSK4_R[src]
Bit 31 - Alarm A date mask
pub fn wdsel(&self) -> WDSEL_R[src]
Bit 30 - Week day selection
pub fn dt(&self) -> DT_R[src]
Bits 28:29 - Date tens in BCD format.
pub fn du(&self) -> DU_R[src]
Bits 24:27 - Date units or day in BCD format.
pub fn msk3(&self) -> MSK3_R[src]
Bit 23 - Alarm A hours mask
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format.
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format.
pub fn msk2(&self) -> MSK2_R[src]
Bit 15 - Alarm A minutes mask
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format.
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format.
pub fn msk1(&self) -> MSK1_R[src]
Bit 7 - Alarm A seconds mask
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format.
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format.
impl R<u32, Reg<u32, _ALRMBR>>[src]
pub fn msk4(&self) -> MSK4_R[src]
Bit 31 - Alarm B date mask
pub fn wdsel(&self) -> WDSEL_R[src]
Bit 30 - Week day selection
pub fn dt(&self) -> DT_R[src]
Bits 28:29 - Date tens in BCD format
pub fn du(&self) -> DU_R[src]
Bits 24:27 - Date units or day in BCD format
pub fn msk3(&self) -> MSK3_R[src]
Bit 23 - Alarm B hours mask
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format
pub fn msk2(&self) -> MSK2_R[src]
Bit 15 - Alarm B minutes mask
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format
pub fn msk1(&self) -> MSK1_R[src]
Bit 7 - Alarm B seconds mask
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format
impl R<u32, Reg<u32, _SSR>>[src]
impl R<u32, Reg<u32, _TSTR>>[src]
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format.
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format.
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format.
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format.
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format.
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format.
impl R<u32, Reg<u32, _TSDR>>[src]
pub fn wdu(&self) -> WDU_R[src]
Bits 13:15 - Week day units
pub fn mt(&self) -> MT_R[src]
Bit 12 - Month tens in BCD format
pub fn mu(&self) -> MU_R[src]
Bits 8:11 - Month units in BCD format
pub fn dt(&self) -> DT_R[src]
Bits 4:5 - Date tens in BCD format
pub fn du(&self) -> DU_R[src]
Bits 0:3 - Date units in BCD format
impl R<u32, Reg<u32, _TSSSR>>[src]
impl R<u32, Reg<u32, _CALR>>[src]
pub fn calp(&self) -> CALP_R[src]
Bit 15 - Use an 8-second calibration cycle period
pub fn calw8(&self) -> CALW8_R[src]
Bit 14 - Use a 16-second calibration cycle period
pub fn calw16(&self) -> CALW16_R[src]
Bit 13 - CALW16
pub fn calm(&self) -> CALM_R[src]
Bits 0:8 - Calibration minus
impl R<u32, Reg<u32, _TAFCR>>[src]
pub fn alarmouttype(&self) -> ALARMOUTTYPE_R[src]
Bit 18 - AFO_ALARM output type
pub fn tamppudis(&self) -> TAMPPUDIS_R[src]
Bit 15 - TAMPER pull-up disable
pub fn tampprch(&self) -> TAMPPRCH_R[src]
Bits 13:14 - Tamper precharge duration
pub fn tampflt(&self) -> TAMPFLT_R[src]
Bits 11:12 - Tamper filter count
pub fn tampfreq(&self) -> TAMPFREQ_R[src]
Bits 8:10 - Tamper sampling frequency
pub fn tampts(&self) -> TAMPTS_R[src]
Bit 7 - Activate timestamp on tamper detection event
pub fn tamp3trg(&self) -> TAMP3TRG_R[src]
Bit 6 - TAMPER1 mapping
pub fn tamp3e(&self) -> TAMP3E_R[src]
Bit 5 - TIMESTAMP mapping
pub fn tamp2trg(&self) -> TAMP2TRG_R[src]
Bit 4 - Active level for tamper 2
pub fn tamp2e(&self) -> TAMP2E_R[src]
Bit 3 - Tamper 2 detection enable
pub fn tampie(&self) -> TAMPIE_R[src]
Bit 2 - Tamper interrupt enable
pub fn tamp1etrg(&self) -> TAMP1ETRG_R[src]
Bit 1 - Active level for tamper 1
pub fn tamp1e(&self) -> TAMP1E_R[src]
Bit 0 - Tamper 1 detection enable
impl R<u32, Reg<u32, _ALRMASSR>>[src]
pub fn maskss(&self) -> MASKSS_R[src]
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&self) -> SS_R[src]
Bits 0:14 - Sub seconds value
impl R<u32, Reg<u32, _ALRMBSSR>>[src]
pub fn maskss(&self) -> MASKSS_R[src]
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&self) -> SS_R[src]
Bits 0:14 - Sub seconds value
impl R<u32, Reg<u32, _BKPR>>[src]
impl R<bool, BIDIMODE_A>[src]
pub fn variant(&self) -> BIDIMODE_A[src]
Get enumerated values variant
pub fn is_unidirectional(&self) -> bool[src]
Checks if the value of the field is UNIDIRECTIONAL
pub fn is_bidirectional(&self) -> bool[src]
Checks if the value of the field is BIDIRECTIONAL
impl R<bool, BIDIOE_A>[src]
pub fn variant(&self) -> BIDIOE_A[src]
Get enumerated values variant
pub fn is_output_disabled(&self) -> bool[src]
Checks if the value of the field is OUTPUTDISABLED
pub fn is_output_enabled(&self) -> bool[src]
Checks if the value of the field is OUTPUTENABLED
impl R<bool, CRCEN_A>[src]
pub fn variant(&self) -> CRCEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CRCNEXT_A>[src]
pub fn variant(&self) -> CRCNEXT_A[src]
Get enumerated values variant
pub fn is_tx_buffer(&self) -> bool[src]
Checks if the value of the field is TXBUFFER
pub fn is_crc(&self) -> bool[src]
Checks if the value of the field is CRC
impl R<bool, DFF_A>[src]
pub fn variant(&self) -> DFF_A[src]
Get enumerated values variant
pub fn is_eight_bit(&self) -> bool[src]
Checks if the value of the field is EIGHTBIT
pub fn is_sixteen_bit(&self) -> bool[src]
Checks if the value of the field is SIXTEENBIT
impl R<bool, RXONLY_A>[src]
pub fn variant(&self) -> RXONLY_A[src]
Get enumerated values variant
pub fn is_full_duplex(&self) -> bool[src]
Checks if the value of the field is FULLDUPLEX
pub fn is_output_disabled(&self) -> bool[src]
Checks if the value of the field is OUTPUTDISABLED
impl R<bool, SSM_A>[src]
pub fn variant(&self) -> SSM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, SSI_A>[src]
pub fn variant(&self) -> SSI_A[src]
Get enumerated values variant
pub fn is_slave_selected(&self) -> bool[src]
Checks if the value of the field is SLAVESELECTED
pub fn is_slave_not_selected(&self) -> bool[src]
Checks if the value of the field is SLAVENOTSELECTED
impl R<bool, LSBFIRST_A>[src]
pub fn variant(&self) -> LSBFIRST_A[src]
Get enumerated values variant
pub fn is_msbfirst(&self) -> bool[src]
Checks if the value of the field is MSBFIRST
pub fn is_lsbfirst(&self) -> bool[src]
Checks if the value of the field is LSBFIRST
impl R<bool, SPE_A>[src]
pub fn variant(&self) -> SPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, BR_A>[src]
pub fn variant(&self) -> BR_A[src]
Get enumerated values variant
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
pub fn is_div8(&self) -> bool[src]
Checks if the value of the field is DIV8
pub fn is_div16(&self) -> bool[src]
Checks if the value of the field is DIV16
pub fn is_div32(&self) -> bool[src]
Checks if the value of the field is DIV32
pub fn is_div64(&self) -> bool[src]
Checks if the value of the field is DIV64
pub fn is_div128(&self) -> bool[src]
Checks if the value of the field is DIV128
pub fn is_div256(&self) -> bool[src]
Checks if the value of the field is DIV256
impl R<bool, MSTR_A>[src]
pub fn variant(&self) -> MSTR_A[src]
Get enumerated values variant
pub fn is_slave(&self) -> bool[src]
Checks if the value of the field is SLAVE
pub fn is_master(&self) -> bool[src]
Checks if the value of the field is MASTER
impl R<bool, CPOL_A>[src]
pub fn variant(&self) -> CPOL_A[src]
Get enumerated values variant
pub fn is_idle_low(&self) -> bool[src]
Checks if the value of the field is IDLELOW
pub fn is_idle_high(&self) -> bool[src]
Checks if the value of the field is IDLEHIGH
impl R<bool, CPHA_A>[src]
pub fn variant(&self) -> CPHA_A[src]
Get enumerated values variant
pub fn is_first_edge(&self) -> bool[src]
Checks if the value of the field is FIRSTEDGE
pub fn is_second_edge(&self) -> bool[src]
Checks if the value of the field is SECONDEDGE
impl R<u32, Reg<u32, _CR1>>[src]
pub fn bidimode(&self) -> BIDIMODE_R[src]
Bit 15 - Bidirectional data mode enable
pub fn bidioe(&self) -> BIDIOE_R[src]
Bit 14 - Output enable in bidirectional mode
pub fn crcen(&self) -> CRCEN_R[src]
Bit 13 - Hardware CRC calculation enable
pub fn crcnext(&self) -> CRCNEXT_R[src]
Bit 12 - CRC transfer next
pub fn dff(&self) -> DFF_R[src]
Bit 11 - Data frame format
pub fn rxonly(&self) -> RXONLY_R[src]
Bit 10 - Receive only
pub fn ssm(&self) -> SSM_R[src]
Bit 9 - Software slave management
pub fn ssi(&self) -> SSI_R[src]
Bit 8 - Internal slave select
pub fn lsbfirst(&self) -> LSBFIRST_R[src]
Bit 7 - Frame format
pub fn spe(&self) -> SPE_R[src]
Bit 6 - SPI enable
pub fn br(&self) -> BR_R[src]
Bits 3:5 - Baud rate control
pub fn mstr(&self) -> MSTR_R[src]
Bit 2 - Master selection
pub fn cpol(&self) -> CPOL_R[src]
Bit 1 - Clock polarity
pub fn cpha(&self) -> CPHA_R[src]
Bit 0 - Clock phase
impl R<bool, TXEIE_A>[src]
pub fn variant(&self) -> TXEIE_A[src]
Get enumerated values variant
pub fn is_masked(&self) -> bool[src]
Checks if the value of the field is MASKED
pub fn is_not_masked(&self) -> bool[src]
Checks if the value of the field is NOTMASKED
impl R<bool, RXNEIE_A>[src]
pub fn variant(&self) -> RXNEIE_A[src]
Get enumerated values variant
pub fn is_masked(&self) -> bool[src]
Checks if the value of the field is MASKED
pub fn is_not_masked(&self) -> bool[src]
Checks if the value of the field is NOTMASKED
impl R<bool, ERRIE_A>[src]
pub fn variant(&self) -> ERRIE_A[src]
Get enumerated values variant
pub fn is_masked(&self) -> bool[src]
Checks if the value of the field is MASKED
pub fn is_not_masked(&self) -> bool[src]
Checks if the value of the field is NOTMASKED
impl R<bool, FRF_A>[src]
pub fn variant(&self) -> FRF_A[src]
Get enumerated values variant
pub fn is_motorola(&self) -> bool[src]
Checks if the value of the field is MOTOROLA
pub fn is_ti(&self) -> bool[src]
Checks if the value of the field is TI
impl R<bool, SSOE_A>[src]
pub fn variant(&self) -> SSOE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, TXDMAEN_A>[src]
pub fn variant(&self) -> TXDMAEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, RXDMAEN_A>[src]
pub fn variant(&self) -> RXDMAEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR2>>[src]
pub fn txeie(&self) -> TXEIE_R[src]
Bit 7 - Tx buffer empty interrupt enable
pub fn rxneie(&self) -> RXNEIE_R[src]
Bit 6 - RX buffer not empty interrupt enable
pub fn errie(&self) -> ERRIE_R[src]
Bit 5 - Error interrupt enable
pub fn frf(&self) -> FRF_R[src]
Bit 4 - Frame format
pub fn ssoe(&self) -> SSOE_R[src]
Bit 2 - SS output enable
pub fn txdmaen(&self) -> TXDMAEN_R[src]
Bit 1 - Tx buffer DMA enable
pub fn rxdmaen(&self) -> RXDMAEN_R[src]
Bit 0 - Rx buffer DMA enable
impl R<bool, FRE_A>[src]
pub fn variant(&self) -> FRE_A[src]
Get enumerated values variant
pub fn is_no_error(&self) -> bool[src]
Checks if the value of the field is NOERROR
pub fn is_error(&self) -> bool[src]
Checks if the value of the field is ERROR
impl R<bool, BSY_A>[src]
pub fn variant(&self) -> BSY_A[src]
Get enumerated values variant
pub fn is_not_busy(&self) -> bool[src]
Checks if the value of the field is NOTBUSY
pub fn is_busy(&self) -> bool[src]
Checks if the value of the field is BUSY
impl R<bool, OVR_A>[src]
pub fn variant(&self) -> OVR_A[src]
Get enumerated values variant
pub fn is_no_overrun(&self) -> bool[src]
Checks if the value of the field is NOOVERRUN
pub fn is_overrun(&self) -> bool[src]
Checks if the value of the field is OVERRUN
impl R<bool, MODF_A>[src]
pub fn variant(&self) -> MODF_A[src]
Get enumerated values variant
pub fn is_no_fault(&self) -> bool[src]
Checks if the value of the field is NOFAULT
pub fn is_fault(&self) -> bool[src]
Checks if the value of the field is FAULT
impl R<bool, CRCERR_A>[src]
pub fn variant(&self) -> CRCERR_A[src]
Get enumerated values variant
pub fn is_match_(&self) -> bool[src]
Checks if the value of the field is MATCH
pub fn is_no_match(&self) -> bool[src]
Checks if the value of the field is NOMATCH
impl R<bool, UDR_A>[src]
pub fn variant(&self) -> UDR_A[src]
Get enumerated values variant
pub fn is_no_underrun(&self) -> bool[src]
Checks if the value of the field is NOUNDERRUN
pub fn is_underrun(&self) -> bool[src]
Checks if the value of the field is UNDERRUN
impl R<bool, CHSIDE_A>[src]
pub fn variant(&self) -> CHSIDE_A[src]
Get enumerated values variant
pub fn is_left(&self) -> bool[src]
Checks if the value of the field is LEFT
pub fn is_right(&self) -> bool[src]
Checks if the value of the field is RIGHT
impl R<bool, TXE_A>[src]
pub fn variant(&self) -> TXE_A[src]
Get enumerated values variant
pub fn is_not_empty(&self) -> bool[src]
Checks if the value of the field is NOTEMPTY
pub fn is_empty(&self) -> bool[src]
Checks if the value of the field is EMPTY
impl R<bool, RXNE_A>[src]
pub fn variant(&self) -> RXNE_A[src]
Get enumerated values variant
pub fn is_empty(&self) -> bool[src]
Checks if the value of the field is EMPTY
pub fn is_not_empty(&self) -> bool[src]
Checks if the value of the field is NOTEMPTY
impl R<u32, Reg<u32, _SR>>[src]
pub fn fre(&self) -> FRE_R[src]
Bit 8 - Frame Error
pub fn bsy(&self) -> BSY_R[src]
Bit 7 - Busy flag
pub fn ovr(&self) -> OVR_R[src]
Bit 6 - Overrun flag
pub fn modf(&self) -> MODF_R[src]
Bit 5 - Mode fault
pub fn crcerr(&self) -> CRCERR_R[src]
Bit 4 - CRC error flag
pub fn udr(&self) -> UDR_R[src]
Bit 3 - Underrun flag
pub fn chside(&self) -> CHSIDE_R[src]
Bit 2 - Channel side
pub fn txe(&self) -> TXE_R[src]
Bit 1 - Transmit buffer empty
pub fn rxne(&self) -> RXNE_R[src]
Bit 0 - Receive buffer not empty
impl R<u32, Reg<u32, _DR>>[src]
impl R<u32, Reg<u32, _CRCPR>>[src]
impl R<u32, Reg<u32, _RXCRCR>>[src]
impl R<u32, Reg<u32, _TXCRCR>>[src]
impl R<bool, I2SMOD_A>[src]
pub fn variant(&self) -> I2SMOD_A[src]
Get enumerated values variant
pub fn is_spimode(&self) -> bool[src]
Checks if the value of the field is SPIMODE
pub fn is_i2smode(&self) -> bool[src]
Checks if the value of the field is I2SMODE
impl R<bool, I2SE_A>[src]
pub fn variant(&self) -> I2SE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, I2SCFG_A>[src]
pub fn variant(&self) -> I2SCFG_A[src]
Get enumerated values variant
pub fn is_slave_tx(&self) -> bool[src]
Checks if the value of the field is SLAVETX
pub fn is_slave_rx(&self) -> bool[src]
Checks if the value of the field is SLAVERX
pub fn is_master_tx(&self) -> bool[src]
Checks if the value of the field is MASTERTX
pub fn is_master_rx(&self) -> bool[src]
Checks if the value of the field is MASTERRX
impl R<bool, PCMSYNC_A>[src]
pub fn variant(&self) -> PCMSYNC_A[src]
Get enumerated values variant
pub fn is_short(&self) -> bool[src]
Checks if the value of the field is SHORT
pub fn is_long(&self) -> bool[src]
Checks if the value of the field is LONG
impl R<u8, I2SSTD_A>[src]
pub fn variant(&self) -> I2SSTD_A[src]
Get enumerated values variant
pub fn is_philips(&self) -> bool[src]
Checks if the value of the field is PHILIPS
pub fn is_msb(&self) -> bool[src]
Checks if the value of the field is MSB
pub fn is_lsb(&self) -> bool[src]
Checks if the value of the field is LSB
pub fn is_pcm(&self) -> bool[src]
Checks if the value of the field is PCM
impl R<bool, CKPOL_A>[src]
pub fn variant(&self) -> CKPOL_A[src]
Get enumerated values variant
pub fn is_idle_low(&self) -> bool[src]
Checks if the value of the field is IDLELOW
pub fn is_idle_high(&self) -> bool[src]
Checks if the value of the field is IDLEHIGH
impl R<u8, DATLEN_A>[src]
pub fn variant(&self) -> Variant<u8, DATLEN_A>[src]
Get enumerated values variant
pub fn is_sixteen_bit(&self) -> bool[src]
Checks if the value of the field is SIXTEENBIT
pub fn is_twenty_four_bit(&self) -> bool[src]
Checks if the value of the field is TWENTYFOURBIT
pub fn is_thirty_two_bit(&self) -> bool[src]
Checks if the value of the field is THIRTYTWOBIT
impl R<bool, CHLEN_A>[src]
pub fn variant(&self) -> CHLEN_A[src]
Get enumerated values variant
pub fn is_sixteen_bit(&self) -> bool[src]
Checks if the value of the field is SIXTEENBIT
pub fn is_thirty_two_bit(&self) -> bool[src]
Checks if the value of the field is THIRTYTWOBIT
impl R<u32, Reg<u32, _I2SCFGR>>[src]
pub fn i2smod(&self) -> I2SMOD_R[src]
Bit 11 - I2S mode selection
pub fn i2se(&self) -> I2SE_R[src]
Bit 10 - I2S Enable
pub fn i2scfg(&self) -> I2SCFG_R[src]
Bits 8:9 - I2S configuration mode
pub fn pcmsync(&self) -> PCMSYNC_R[src]
Bit 7 - PCM frame synchronization
pub fn i2sstd(&self) -> I2SSTD_R[src]
Bits 4:5 - I2S standard selection
pub fn ckpol(&self) -> CKPOL_R[src]
Bit 3 - Steady state clock polarity
pub fn datlen(&self) -> DATLEN_R[src]
Bits 1:2 - Data length to be transferred
pub fn chlen(&self) -> CHLEN_R[src]
Bit 0 - Channel length (number of bits per audio channel)
impl R<bool, MCKOE_A>[src]
pub fn variant(&self) -> MCKOE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ODD_A>[src]
pub fn variant(&self) -> ODD_A[src]
Get enumerated values variant
pub fn is_even(&self) -> bool[src]
Checks if the value of the field is EVEN
pub fn is_odd(&self) -> bool[src]
Checks if the value of the field is ODD
impl R<u32, Reg<u32, _I2SPR>>[src]
pub fn mckoe(&self) -> MCKOE_R[src]
Bit 9 - Master clock output enable
pub fn odd(&self) -> ODD_R[src]
Bit 8 - Odd factor for the prescaler
pub fn i2sdiv(&self) -> I2SDIV_R[src]
Bits 0:7 - I2S Linear prescaler
impl R<u32, Reg<u32, _MEMRMP>>[src]
pub fn mem_mode(&self) -> MEM_MODE_R[src]
Bits 0:1 - MEM_MODE
pub fn boot_mode(&self) -> BOOT_MODE_R[src]
Bits 8:9 - BOOT_MODE
impl R<u32, Reg<u32, _PMC>>[src]
impl R<u32, Reg<u32, _EXTICR1>>[src]
pub fn exti3(&self) -> EXTI3_R[src]
Bits 12:15 - EXTI x configuration (x = 0 to 3)
pub fn exti2(&self) -> EXTI2_R[src]
Bits 8:11 - EXTI x configuration (x = 0 to 3)
pub fn exti1(&self) -> EXTI1_R[src]
Bits 4:7 - EXTI x configuration (x = 0 to 3)
pub fn exti0(&self) -> EXTI0_R[src]
Bits 0:3 - EXTI x configuration (x = 0 to 3)
impl R<u32, Reg<u32, _EXTICR2>>[src]
pub fn exti7(&self) -> EXTI7_R[src]
Bits 12:15 - EXTI x configuration (x = 4 to 7)
pub fn exti6(&self) -> EXTI6_R[src]
Bits 8:11 - EXTI x configuration (x = 4 to 7)
pub fn exti5(&self) -> EXTI5_R[src]
Bits 4:7 - EXTI x configuration (x = 4 to 7)
pub fn exti4(&self) -> EXTI4_R[src]
Bits 0:3 - EXTI x configuration (x = 4 to 7)
impl R<u32, Reg<u32, _EXTICR3>>[src]
pub fn exti11(&self) -> EXTI11_R[src]
Bits 12:15 - EXTI x configuration (x = 8 to 11)
pub fn exti10(&self) -> EXTI10_R[src]
Bits 8:11 - EXTI10
pub fn exti9(&self) -> EXTI9_R[src]
Bits 4:7 - EXTI x configuration (x = 8 to 11)
pub fn exti8(&self) -> EXTI8_R[src]
Bits 0:3 - EXTI x configuration (x = 8 to 11)
impl R<u32, Reg<u32, _EXTICR4>>[src]
pub fn exti15(&self) -> EXTI15_R[src]
Bits 12:15 - EXTI x configuration (x = 12 to 15)
pub fn exti14(&self) -> EXTI14_R[src]
Bits 8:11 - EXTI14
pub fn exti13(&self) -> EXTI13_R[src]
Bits 4:7 - EXTI13
pub fn exti12(&self) -> EXTI12_R[src]
Bits 0:3 - EXTI12
impl R<u8, CKD_A>[src]
pub fn variant(&self) -> Variant<u8, CKD_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ckd(&self) -> CKD_R[src]
Bits 8:9 - Clock division
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn cc1ie(&self) -> CC1IE_R[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
pub fn cc1of(&self) -> CC1OF_R[src]
Bit 9 - Capture/compare 1 overcapture flag
pub fn cc1if(&self) -> CC1IF_R[src]
Bit 1 - Capture/Compare 1 interrupt flag
pub fn uif(&self) -> UIF_R[src]
Bit 0 - Update interrupt flag
impl R<bool, UG_A>[src]
pub fn variant(&self) -> Variant<bool, UG_A>[src]
Get enumerated values variant
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
impl R<u32, Reg<u32, _EGR>>[src]
pub fn cc1g(&self) -> CC1G_R[src]
Bit 1 - Capture/Compare 1 generation
pub fn ug(&self) -> UG_R[src]
Bit 0 - Update generation
impl R<u32, Reg<u32, _CCMR1_OUTPUT>>[src]
pub fn oc1m(&self) -> OC1M_R[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&self) -> OC1PE_R[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&self) -> OC1FE_R[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u32, Reg<u32, _CCMR1_INPUT>>[src]
pub fn ic1f(&self) -> IC1F_R[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&self) -> IC1PSC_R[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u32, Reg<u32, _CCER>>[src]
pub fn cc1np(&self) -> CC1NP_R[src]
Bit 3 - Capture/Compare 1 complementary output Polarity
pub fn cc1p(&self) -> CC1P_R[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&self) -> CC1E_R[src]
Bit 0 - Capture/Compare 1 output enable
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u32, Reg<u32, _CCR>>[src]
impl R<u32, Reg<u32, _OR>>[src]
impl R<u8, CKD_A>[src]
pub fn variant(&self) -> Variant<u8, CKD_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CMS_A>[src]
pub fn variant(&self) -> CMS_A[src]
Get enumerated values variant
pub fn is_edge_aligned(&self) -> bool[src]
Checks if the value of the field is EDGEALIGNED
pub fn is_center_aligned1(&self) -> bool[src]
Checks if the value of the field is CENTERALIGNED1
pub fn is_center_aligned2(&self) -> bool[src]
Checks if the value of the field is CENTERALIGNED2
pub fn is_center_aligned3(&self) -> bool[src]
Checks if the value of the field is CENTERALIGNED3
impl R<bool, DIR_A>[src]
pub fn variant(&self) -> DIR_A[src]
Get enumerated values variant
pub fn is_up(&self) -> bool[src]
Checks if the value of the field is UP
pub fn is_down(&self) -> bool[src]
Checks if the value of the field is DOWN
impl R<bool, OPM_A>[src]
pub fn variant(&self) -> OPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ckd(&self) -> CKD_R[src]
Bits 8:9 - Clock division
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&self) -> CMS_R[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Direction
pub fn opm(&self) -> OPM_R[src]
Bit 3 - One-pulse mode
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
impl R<bool, TI1S_A>[src]
pub fn variant(&self) -> TI1S_A[src]
Get enumerated values variant
pub fn is_normal(&self) -> bool[src]
Checks if the value of the field is NORMAL
pub fn is_xor(&self) -> bool[src]
Checks if the value of the field is XOR
impl R<u8, MMS_A>[src]
pub fn variant(&self) -> MMS_A[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
pub fn is_enable(&self) -> bool[src]
Checks if the value of the field is ENABLE
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
pub fn is_compare_pulse(&self) -> bool[src]
Checks if the value of the field is COMPAREPULSE
pub fn is_compare_oc1(&self) -> bool[src]
Checks if the value of the field is COMPAREOC1
pub fn is_compare_oc2(&self) -> bool[src]
Checks if the value of the field is COMPAREOC2
pub fn is_compare_oc3(&self) -> bool[src]
Checks if the value of the field is COMPAREOC3
pub fn is_compare_oc4(&self) -> bool[src]
Checks if the value of the field is COMPAREOC4
impl R<bool, CCDS_A>[src]
pub fn variant(&self) -> CCDS_A[src]
Get enumerated values variant
pub fn is_on_compare(&self) -> bool[src]
Checks if the value of the field is ONCOMPARE
pub fn is_on_update(&self) -> bool[src]
Checks if the value of the field is ONUPDATE
impl R<u32, Reg<u32, _CR2>>[src]
pub fn ti1s(&self) -> TI1S_R[src]
Bit 7 - TI1 selection
pub fn mms(&self) -> MMS_R[src]
Bits 4:6 - Master mode selection
pub fn ccds(&self) -> CCDS_R[src]
Bit 3 - Capture/compare DMA selection
impl R<bool, ETP_A>[src]
pub fn variant(&self) -> ETP_A[src]
Get enumerated values variant
pub fn is_not_inverted(&self) -> bool[src]
Checks if the value of the field is NOTINVERTED
pub fn is_inverted(&self) -> bool[src]
Checks if the value of the field is INVERTED
impl R<bool, ECE_A>[src]
pub fn variant(&self) -> ECE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, ETPS_A>[src]
pub fn variant(&self) -> ETPS_A[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
pub fn is_div8(&self) -> bool[src]
Checks if the value of the field is DIV8
impl R<u8, ETF_A>[src]
pub fn variant(&self) -> ETF_A[src]
Get enumerated values variant
pub fn is_no_filter(&self) -> bool[src]
Checks if the value of the field is NOFILTER
pub fn is_fck_int_n2(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N2
pub fn is_fck_int_n4(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N4
pub fn is_fck_int_n8(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N8
pub fn is_fdts_div2_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N6
pub fn is_fdts_div2_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N8
pub fn is_fdts_div4_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N6
pub fn is_fdts_div4_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N8
pub fn is_fdts_div8_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N6
pub fn is_fdts_div8_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N8
pub fn is_fdts_div16_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N5
pub fn is_fdts_div16_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N6
pub fn is_fdts_div16_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N8
pub fn is_fdts_div32_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N5
pub fn is_fdts_div32_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N6
pub fn is_fdts_div32_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N8
impl R<bool, MSM_A>[src]
pub fn variant(&self) -> MSM_A[src]
Get enumerated values variant
pub fn is_no_sync(&self) -> bool[src]
Checks if the value of the field is NOSYNC
pub fn is_sync(&self) -> bool[src]
Checks if the value of the field is SYNC
impl R<u8, TS_A>[src]
pub fn variant(&self) -> Variant<u8, TS_A>[src]
Get enumerated values variant
pub fn is_itr0(&self) -> bool[src]
Checks if the value of the field is ITR0
pub fn is_itr1(&self) -> bool[src]
Checks if the value of the field is ITR1
pub fn is_itr2(&self) -> bool[src]
Checks if the value of the field is ITR2
pub fn is_ti1f_ed(&self) -> bool[src]
Checks if the value of the field is TI1F_ED
pub fn is_ti1fp1(&self) -> bool[src]
Checks if the value of the field is TI1FP1
pub fn is_ti2fp2(&self) -> bool[src]
Checks if the value of the field is TI2FP2
pub fn is_etrf(&self) -> bool[src]
Checks if the value of the field is ETRF
impl R<u8, SMS_A>[src]
pub fn variant(&self) -> SMS_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_encoder_mode_1(&self) -> bool[src]
Checks if the value of the field is ENCODER_MODE_1
pub fn is_encoder_mode_2(&self) -> bool[src]
Checks if the value of the field is ENCODER_MODE_2
pub fn is_encoder_mode_3(&self) -> bool[src]
Checks if the value of the field is ENCODER_MODE_3
pub fn is_reset_mode(&self) -> bool[src]
Checks if the value of the field is RESET_MODE
pub fn is_gated_mode(&self) -> bool[src]
Checks if the value of the field is GATED_MODE
pub fn is_trigger_mode(&self) -> bool[src]
Checks if the value of the field is TRIGGER_MODE
pub fn is_ext_clock_mode(&self) -> bool[src]
Checks if the value of the field is EXT_CLOCK_MODE
impl R<u32, Reg<u32, _SMCR>>[src]
pub fn etp(&self) -> ETP_R[src]
Bit 15 - External trigger polarity
pub fn ece(&self) -> ECE_R[src]
Bit 14 - External clock enable
pub fn etps(&self) -> ETPS_R[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&self) -> ETF_R[src]
Bits 8:11 - External trigger filter
pub fn msm(&self) -> MSM_R[src]
Bit 7 - Master/Slave mode
pub fn ts(&self) -> TS_R[src]
Bits 4:6 - Trigger selection
pub fn occs(&self) -> OCCS_R[src]
Bit 3 - OCREF clear selection
pub fn sms(&self) -> SMS_R[src]
Bits 0:2 - Slave mode selection
impl R<bool, TDE_A>[src]
pub fn variant(&self) -> TDE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC4DE_A>[src]
pub fn variant(&self) -> CC4DE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, UDE_A>[src]
pub fn variant(&self) -> UDE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, TIE_A>[src]
pub fn variant(&self) -> TIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC4IE_A>[src]
pub fn variant(&self) -> CC4IE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn tde(&self) -> TDE_R[src]
Bit 14 - Trigger DMA request enable
pub fn cc4de(&self) -> CC4DE_R[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&self) -> CC3DE_R[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&self) -> CC2DE_R[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&self) -> CC1DE_R[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&self) -> UDE_R[src]
Bit 8 - Update DMA request enable
pub fn tie(&self) -> TIE_R[src]
Bit 6 - Trigger interrupt enable
pub fn cc4ie(&self) -> CC4IE_R[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&self) -> CC3IE_R[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&self) -> CC2IE_R[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&self) -> CC1IE_R[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
impl R<bool, CC4OF_A>[src]
pub fn variant(&self) -> Variant<bool, CC4OF_A>[src]
Get enumerated values variant
pub fn is_overcapture(&self) -> bool[src]
Checks if the value of the field is OVERCAPTURE
impl R<bool, TIF_A>[src]
pub fn variant(&self) -> TIF_A[src]
Get enumerated values variant
pub fn is_no_trigger(&self) -> bool[src]
Checks if the value of the field is NOTRIGGER
pub fn is_trigger(&self) -> bool[src]
Checks if the value of the field is TRIGGER
impl R<bool, CC4IF_A>[src]
pub fn variant(&self) -> Variant<bool, CC4IF_A>[src]
Get enumerated values variant
pub fn is_match_(&self) -> bool[src]
Checks if the value of the field is MATCH
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
pub fn cc4of(&self) -> CC4OF_R[src]
Bit 12 - Capture/compare 1 overcapture flag
pub fn cc3of(&self) -> CC3OF_R[src]
Bit 11 - Capture/compare 3 overcapture flag
pub fn cc2of(&self) -> CC2OF_R[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&self) -> CC1OF_R[src]
Bit 9 - Capture/compare 1 overcapture flag
pub fn tif(&self) -> TIF_R[src]
Bit 6 - Trigger interrupt flag
pub fn cc4if(&self) -> CC4IF_R[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&self) -> CC3IF_R[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&self) -> CC2IF_R[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&self) -> CC1IF_R[src]
Bit 1 - Capture/Compare 1 interrupt flag
pub fn uif(&self) -> UIF_R[src]
Bit 0 - Update interrupt flag
impl R<bool, TG_A>[src]
pub fn variant(&self) -> Variant<bool, TG_A>[src]
Get enumerated values variant
pub fn is_trigger(&self) -> bool[src]
Checks if the value of the field is TRIGGER
impl R<bool, CC4G_A>[src]
pub fn variant(&self) -> Variant<bool, CC4G_A>[src]
Get enumerated values variant
pub fn is_trigger(&self) -> bool[src]
Checks if the value of the field is TRIGGER
impl R<bool, UG_A>[src]
pub fn variant(&self) -> Variant<bool, UG_A>[src]
Get enumerated values variant
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
impl R<u32, Reg<u32, _EGR>>[src]
pub fn tg(&self) -> TG_R[src]
Bit 6 - Trigger generation
pub fn cc4g(&self) -> CC4G_R[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&self) -> CC3G_R[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&self) -> CC2G_R[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&self) -> CC1G_R[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&self) -> UG_R[src]
Bit 0 - Update generation
impl R<u8, OC2M_A>[src]
pub fn variant(&self) -> OC2M_A[src]
Get enumerated values variant
pub fn is_frozen(&self) -> bool[src]
Checks if the value of the field is FROZEN
pub fn is_active_on_match(&self) -> bool[src]
Checks if the value of the field is ACTIVEONMATCH
pub fn is_inactive_on_match(&self) -> bool[src]
Checks if the value of the field is INACTIVEONMATCH
pub fn is_toggle(&self) -> bool[src]
Checks if the value of the field is TOGGLE
pub fn is_force_inactive(&self) -> bool[src]
Checks if the value of the field is FORCEINACTIVE
pub fn is_force_active(&self) -> bool[src]
Checks if the value of the field is FORCEACTIVE
pub fn is_pwm_mode1(&self) -> bool[src]
Checks if the value of the field is PWMMODE1
pub fn is_pwm_mode2(&self) -> bool[src]
Checks if the value of the field is PWMMODE2
impl R<bool, OC2PE_A>[src]
pub fn variant(&self) -> OC2PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC2S_A>[src]
pub fn variant(&self) -> Variant<bool, CC2S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<bool, OC1PE_A>[src]
pub fn variant(&self) -> OC1PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CC1S_A>[src]
pub fn variant(&self) -> Variant<u8, CC1S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<u32, Reg<u32, _CCMR1_OUTPUT>>[src]
pub fn oc2ce(&self) -> OC2CE_R[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&self) -> OC2M_R[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&self) -> OC2PE_R[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&self) -> OC2FE_R[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&self) -> CC2S_R[src]
Bit 8 - Capture/Compare 2 selection
pub fn oc1ce(&self) -> OC1CE_R[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&self) -> OC1M_R[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&self) -> OC1PE_R[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&self) -> OC1FE_R[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u8, CC2S_A>[src]
pub fn variant(&self) -> Variant<u8, CC2S_A>[src]
Get enumerated values variant
pub fn is_ti2(&self) -> bool[src]
Checks if the value of the field is TI2
pub fn is_ti1(&self) -> bool[src]
Checks if the value of the field is TI1
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u8, IC1F_A>[src]
pub fn variant(&self) -> IC1F_A[src]
Get enumerated values variant
pub fn is_no_filter(&self) -> bool[src]
Checks if the value of the field is NOFILTER
pub fn is_fck_int_n2(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N2
pub fn is_fck_int_n4(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N4
pub fn is_fck_int_n8(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N8
pub fn is_fdts_div2_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N6
pub fn is_fdts_div2_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N8
pub fn is_fdts_div4_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N6
pub fn is_fdts_div4_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N8
pub fn is_fdts_div8_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N6
pub fn is_fdts_div8_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N8
pub fn is_fdts_div16_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N5
pub fn is_fdts_div16_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N6
pub fn is_fdts_div16_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N8
pub fn is_fdts_div32_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N5
pub fn is_fdts_div32_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N6
pub fn is_fdts_div32_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N8
impl R<u8, CC1S_A>[src]
pub fn variant(&self) -> Variant<u8, CC1S_A>[src]
Get enumerated values variant
pub fn is_ti1(&self) -> bool[src]
Checks if the value of the field is TI1
pub fn is_ti2(&self) -> bool[src]
Checks if the value of the field is TI2
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u32, Reg<u32, _CCMR1_INPUT>>[src]
pub fn ic2f(&self) -> IC2F_R[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&self) -> IC2PSC_R[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&self) -> CC2S_R[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&self) -> IC1F_R[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&self) -> IC1PSC_R[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u8, OC4M_A>[src]
pub fn variant(&self) -> OC4M_A[src]
Get enumerated values variant
pub fn is_frozen(&self) -> bool[src]
Checks if the value of the field is FROZEN
pub fn is_active_on_match(&self) -> bool[src]
Checks if the value of the field is ACTIVEONMATCH
pub fn is_inactive_on_match(&self) -> bool[src]
Checks if the value of the field is INACTIVEONMATCH
pub fn is_toggle(&self) -> bool[src]
Checks if the value of the field is TOGGLE
pub fn is_force_inactive(&self) -> bool[src]
Checks if the value of the field is FORCEINACTIVE
pub fn is_force_active(&self) -> bool[src]
Checks if the value of the field is FORCEACTIVE
pub fn is_pwm_mode1(&self) -> bool[src]
Checks if the value of the field is PWMMODE1
pub fn is_pwm_mode2(&self) -> bool[src]
Checks if the value of the field is PWMMODE2
impl R<bool, OC4PE_A>[src]
pub fn variant(&self) -> OC4PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC4S_A>[src]
pub fn variant(&self) -> Variant<bool, CC4S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<bool, OC3PE_A>[src]
pub fn variant(&self) -> OC3PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CC3S_A>[src]
pub fn variant(&self) -> Variant<u8, CC3S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<u32, Reg<u32, _CCMR2_OUTPUT>>[src]
pub fn oc4ce(&self) -> OC4CE_R[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&self) -> OC4M_R[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&self) -> OC4PE_R[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&self) -> OC4FE_R[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&self) -> CC4S_R[src]
Bit 8 - Capture/Compare 4 selection
pub fn oc3ce(&self) -> OC3CE_R[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&self) -> OC3M_R[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&self) -> OC3PE_R[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&self) -> OC3FE_R[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&self) -> CC3S_R[src]
Bits 0:1 - Capture/Compare 3 selection
impl R<u8, CC4S_A>[src]
pub fn variant(&self) -> Variant<u8, CC4S_A>[src]
Get enumerated values variant
pub fn is_ti4(&self) -> bool[src]
Checks if the value of the field is TI4
pub fn is_ti3(&self) -> bool[src]
Checks if the value of the field is TI3
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u8, CC3S_A>[src]
pub fn variant(&self) -> Variant<u8, CC3S_A>[src]
Get enumerated values variant
pub fn is_ti3(&self) -> bool[src]
Checks if the value of the field is TI3
pub fn is_ti4(&self) -> bool[src]
Checks if the value of the field is TI4
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u32, Reg<u32, _CCMR2_INPUT>>[src]
pub fn ic4f(&self) -> IC4F_R[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&self) -> IC4PSC_R[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&self) -> CC4S_R[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&self) -> IC3F_R[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&self) -> IC3PSC_R[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&self) -> CC3S_R[src]
Bits 0:1 - Capture/compare 3 selection
impl R<u32, Reg<u32, _CCER>>[src]
pub fn cc4np(&self) -> CC4NP_R[src]
Bit 15 - Capture/Compare 4 output Polarity
pub fn cc4p(&self) -> CC4P_R[src]
Bit 13 - Capture/Compare 4 output Polarity
pub fn cc4e(&self) -> CC4E_R[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&self) -> CC3NP_R[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3p(&self) -> CC3P_R[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&self) -> CC3E_R[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&self) -> CC2NP_R[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&self) -> CC2P_R[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&self) -> CC2E_R[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&self) -> CC1NP_R[src]
Bit 3 - Capture/Compare 1 complementary output Polarity
pub fn cc1p(&self) -> CC1P_R[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&self) -> CC1E_R[src]
Bit 0 - Capture/Compare 1 output enable
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u32, Reg<u32, _CCR>>[src]
impl R<u32, Reg<u32, _DCR>>[src]
pub fn dbl(&self) -> DBL_R[src]
Bits 8:12 - DMA burst length
pub fn dba(&self) -> DBA_R[src]
Bits 0:4 - DMA base address
impl R<u32, Reg<u32, _DMAR>>[src]
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, OPM_A>[src]
pub fn variant(&self) -> OPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&self) -> OPM_R[src]
Bit 3 - One-pulse mode
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
impl R<u8, MMS_A>[src]
pub fn variant(&self) -> Variant<u8, MMS_A>[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
pub fn is_enable(&self) -> bool[src]
Checks if the value of the field is ENABLE
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
impl R<u32, Reg<u32, _CR2>>[src]
impl R<bool, UDE_A>[src]
pub fn variant(&self) -> UDE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn ude(&self) -> UDE_R[src]
Bit 8 - Update DMA request enable
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
pub fn psc(&self) -> PSC_R[src]
Bits 0:15 - Prescaler valueThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u8, CKD_A>[src]
pub fn variant(&self) -> Variant<u8, CKD_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, OPM_A>[src]
pub fn variant(&self) -> OPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ckd(&self) -> CKD_R[src]
Bits 8:9 - Clock division
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&self) -> OPM_R[src]
Bit 3 - One-pulse mode
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
impl R<u32, Reg<u32, _CR2>>[src]
impl R<u32, Reg<u32, _SMCR>>[src]
pub fn msm(&self) -> MSM_R[src]
Bit 7 - Master/Slave mode
pub fn ts(&self) -> TS_R[src]
Bits 4:6 - Trigger selection
pub fn sms(&self) -> SMS_R[src]
Bits 0:2 - Slave mode selection
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn tie(&self) -> TIE_R[src]
Bit 6 - Trigger interrupt enable
pub fn cc2ie(&self) -> CC2IE_R[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&self) -> CC1IE_R[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
pub fn cc2of(&self) -> CC2OF_R[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&self) -> CC1OF_R[src]
Bit 9 - Capture/compare 1 overcapture flag
pub fn tif(&self) -> TIF_R[src]
Bit 6 - Trigger interrupt flag
pub fn cc2if(&self) -> CC2IF_R[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&self) -> CC1IF_R[src]
Bit 1 - Capture/Compare 1 interrupt flag
pub fn uif(&self) -> UIF_R[src]
Bit 0 - Update interrupt flag
impl R<bool, UG_A>[src]
pub fn variant(&self) -> Variant<bool, UG_A>[src]
Get enumerated values variant
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
impl R<u32, Reg<u32, _EGR>>[src]
pub fn tg(&self) -> TG_R[src]
Bit 6 - Trigger generation
pub fn cc2g(&self) -> CC2G_R[src]
Bit 2 - Capture/Compare 2 generation
pub fn cc1g(&self) -> CC1G_R[src]
Bit 1 - Capture/Compare 1 generation
pub fn ug(&self) -> UG_R[src]
Bit 0 - Update generation
impl R<u32, Reg<u32, _CCMR1_OUTPUT>>[src]
pub fn oc2ce(&self) -> OC2CE_R[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&self) -> OC2M_R[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&self) -> OC2PE_R[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&self) -> OC2FE_R[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&self) -> CC2S_R[src]
Bit 8 - Capture/Compare 2 selection
pub fn oc1ce(&self) -> OC1CE_R[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&self) -> OC1M_R[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&self) -> OC1PE_R[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&self) -> OC1FE_R[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u32, Reg<u32, _CCMR1_INPUT>>[src]
pub fn ic2f(&self) -> IC2F_R[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&self) -> IC2PSC_R[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&self) -> CC2S_R[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&self) -> IC1F_R[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&self) -> IC1PSC_R[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u32, Reg<u32, _CCR>>[src]
impl R<u32, Reg<u32, _OR>>[src]
impl R<u32, Reg<u32, _SR>>[src]
pub fn cts(&self) -> CTS_R[src]
Bit 9 - CTS flag
pub fn lbd(&self) -> LBD_R[src]
Bit 8 - LIN break detection flag
pub fn txe(&self) -> TXE_R[src]
Bit 7 - Transmit data register empty
pub fn tc(&self) -> TC_R[src]
Bit 6 - Transmission complete
pub fn rxne(&self) -> RXNE_R[src]
Bit 5 - Read data register not empty
pub fn idle(&self) -> IDLE_R[src]
Bit 4 - IDLE line detected
pub fn ore(&self) -> ORE_R[src]
Bit 3 - Overrun error
pub fn nf(&self) -> NF_R[src]
Bit 2 - Noise detected flag
pub fn fe(&self) -> FE_R[src]
Bit 1 - Framing error
pub fn pe(&self) -> PE_R[src]
Bit 0 - Parity error
impl R<u32, Reg<u32, _DR>>[src]
impl R<u32, Reg<u32, _BRR>>[src]
pub fn div_mantissa(&self) -> DIV_MANTISSA_R[src]
Bits 4:15 - mantissa of USARTDIV
pub fn div_fraction(&self) -> DIV_FRACTION_R[src]
Bits 0:3 - fraction of USARTDIV
impl R<u32, Reg<u32, _CR1>>[src]
pub fn over8(&self) -> OVER8_R[src]
Bit 15 - Oversampling mode
pub fn ue(&self) -> UE_R[src]
Bit 13 - USART enable
pub fn m(&self) -> M_R[src]
Bit 12 - Word length
pub fn wake(&self) -> WAKE_R[src]
Bit 11 - Wakeup method
pub fn pce(&self) -> PCE_R[src]
Bit 10 - Parity control enable
pub fn ps(&self) -> PS_R[src]
Bit 9 - Parity selection
pub fn peie(&self) -> PEIE_R[src]
Bit 8 - PE interrupt enable
pub fn txeie(&self) -> TXEIE_R[src]
Bit 7 - TXE interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 6 - Transmission complete interrupt enable
pub fn rxneie(&self) -> RXNEIE_R[src]
Bit 5 - RXNE interrupt enable
pub fn idleie(&self) -> IDLEIE_R[src]
Bit 4 - IDLE interrupt enable
pub fn te(&self) -> TE_R[src]
Bit 3 - Transmitter enable
pub fn re(&self) -> RE_R[src]
Bit 2 - Receiver enable
pub fn rwu(&self) -> RWU_R[src]
Bit 1 - Receiver wakeup
pub fn sbk(&self) -> SBK_R[src]
Bit 0 - Send break
impl R<u32, Reg<u32, _CR2>>[src]
pub fn linen(&self) -> LINEN_R[src]
Bit 14 - LIN mode enable
pub fn stop(&self) -> STOP_R[src]
Bits 12:13 - STOP bits
pub fn clken(&self) -> CLKEN_R[src]
Bit 11 - Clock enable
pub fn cpol(&self) -> CPOL_R[src]
Bit 10 - Clock polarity
pub fn cpha(&self) -> CPHA_R[src]
Bit 9 - Clock phase
pub fn lbcl(&self) -> LBCL_R[src]
Bit 8 - Last bit clock pulse
pub fn lbdie(&self) -> LBDIE_R[src]
Bit 6 - LIN break detection interrupt enable
pub fn lbdl(&self) -> LBDL_R[src]
Bit 5 - lin break detection length
pub fn add(&self) -> ADD_R[src]
Bits 0:3 - Address of the USART node
impl R<u32, Reg<u32, _CR3>>[src]
pub fn onebit(&self) -> ONEBIT_R[src]
Bit 11 - One sample bit method enable
pub fn ctsie(&self) -> CTSIE_R[src]
Bit 10 - CTS interrupt enable
pub fn ctse(&self) -> CTSE_R[src]
Bit 9 - CTS enable
pub fn rtse(&self) -> RTSE_R[src]
Bit 8 - RTS enable
pub fn dmat(&self) -> DMAT_R[src]
Bit 7 - DMA enable transmitter
pub fn dmar(&self) -> DMAR_R[src]
Bit 6 - DMA enable receiver
pub fn scen(&self) -> SCEN_R[src]
Bit 5 - Smartcard mode enable
pub fn nack(&self) -> NACK_R[src]
Bit 4 - Smartcard NACK enable
pub fn hdsel(&self) -> HDSEL_R[src]
Bit 3 - Half-duplex selection
pub fn irlp(&self) -> IRLP_R[src]
Bit 2 - IrDA low-power
pub fn iren(&self) -> IREN_R[src]
Bit 1 - IrDA mode enable
pub fn eie(&self) -> EIE_R[src]
Bit 0 - Error interrupt enable
impl R<u32, Reg<u32, _GTPR>>[src]
pub fn gt(&self) -> GT_R[src]
Bits 8:15 - Guard time value
pub fn psc(&self) -> PSC_R[src]
Bits 0:7 - Prescaler value
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP0R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP1R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP2R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP3R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP4R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP5R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP6R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP7R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<bool, FRES_A>[src]
pub fn variant(&self) -> FRES_A[src]
Get enumerated values variant
pub fn is_no_reset(&self) -> bool[src]
Checks if the value of the field is NORESET
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<bool, PDWN_A>[src]
pub fn variant(&self) -> PDWN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, LPMODE_A>[src]
pub fn variant(&self) -> LPMODE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, FSUSP_A>[src]
pub fn variant(&self) -> FSUSP_A[src]
Get enumerated values variant
pub fn is_no_effect(&self) -> bool[src]
Checks if the value of the field is NOEFFECT
pub fn is_suspend(&self) -> bool[src]
Checks if the value of the field is SUSPEND
impl R<bool, RESUME_A>[src]
pub fn variant(&self) -> Variant<bool, RESUME_A>[src]
Get enumerated values variant
pub fn is_requested(&self) -> bool[src]
Checks if the value of the field is REQUESTED
impl R<bool, ESOFM_A>[src]
pub fn variant(&self) -> ESOFM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, SOFM_A>[src]
pub fn variant(&self) -> SOFM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, RESETM_A>[src]
pub fn variant(&self) -> RESETM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, SUSPM_A>[src]
pub fn variant(&self) -> SUSPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WKUPM_A>[src]
pub fn variant(&self) -> WKUPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ERRM_A>[src]
pub fn variant(&self) -> ERRM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, PMAOVRM_A>[src]
pub fn variant(&self) -> PMAOVRM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CTRM_A>[src]
pub fn variant(&self) -> CTRM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CNTR>>[src]
pub fn fres(&self) -> FRES_R[src]
Bit 0 - Force USB Reset
pub fn pdwn(&self) -> PDWN_R[src]
Bit 1 - Power down
pub fn lpmode(&self) -> LPMODE_R[src]
Bit 2 - Low-power mode
pub fn fsusp(&self) -> FSUSP_R[src]
Bit 3 - Force suspend
pub fn resume(&self) -> RESUME_R[src]
Bit 4 - Resume request
pub fn esofm(&self) -> ESOFM_R[src]
Bit 8 - Expected start of frame interrupt mask
pub fn sofm(&self) -> SOFM_R[src]
Bit 9 - Start of frame interrupt mask
pub fn resetm(&self) -> RESETM_R[src]
Bit 10 - USB reset interrupt mask
pub fn suspm(&self) -> SUSPM_R[src]
Bit 11 - Suspend mode interrupt mask
pub fn wkupm(&self) -> WKUPM_R[src]
Bit 12 - Wakeup interrupt mask
pub fn errm(&self) -> ERRM_R[src]
Bit 13 - Error interrupt mask
pub fn pmaovrm(&self) -> PMAOVRM_R[src]
Bit 14 - Packet memory area over / underrun interrupt mask
pub fn ctrm(&self) -> CTRM_R[src]
Bit 15 - Correct transfer interrupt mask
impl R<bool, DIR_A>[src]
pub fn variant(&self) -> DIR_A[src]
Get enumerated values variant
pub fn is_to(&self) -> bool[src]
Checks if the value of the field is TO
pub fn is_from(&self) -> bool[src]
Checks if the value of the field is FROM
impl R<bool, ESOF_A>[src]
pub fn variant(&self) -> Variant<bool, ESOF_A>[src]
Get enumerated values variant
pub fn is_expected_start_of_frame(&self) -> bool[src]
Checks if the value of the field is EXPECTEDSTARTOFFRAME
impl R<bool, SOF_A>[src]
pub fn variant(&self) -> Variant<bool, SOF_A>[src]
Get enumerated values variant
pub fn is_start_of_frame(&self) -> bool[src]
Checks if the value of the field is STARTOFFRAME
impl R<bool, RESET_A>[src]
pub fn variant(&self) -> Variant<bool, RESET_A>[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<bool, SUSP_A>[src]
pub fn variant(&self) -> Variant<bool, SUSP_A>[src]
Get enumerated values variant
pub fn is_suspend(&self) -> bool[src]
Checks if the value of the field is SUSPEND
impl R<bool, WKUP_A>[src]
pub fn variant(&self) -> Variant<bool, WKUP_A>[src]
Get enumerated values variant
pub fn is_wakeup(&self) -> bool[src]
Checks if the value of the field is WAKEUP
impl R<bool, ERR_A>[src]
pub fn variant(&self) -> Variant<bool, ERR_A>[src]
Get enumerated values variant
pub fn is_error(&self) -> bool[src]
Checks if the value of the field is ERROR
impl R<bool, PMAOVR_A>[src]
pub fn variant(&self) -> Variant<bool, PMAOVR_A>[src]
Get enumerated values variant
pub fn is_overrun(&self) -> bool[src]
Checks if the value of the field is OVERRUN
impl R<bool, CTR_A>[src]
pub fn variant(&self) -> Variant<bool, CTR_A>[src]
Get enumerated values variant
pub fn is_completed(&self) -> bool[src]
Checks if the value of the field is COMPLETED
impl R<u32, Reg<u32, _ISTR>>[src]
pub fn ep_id(&self) -> EP_ID_R[src]
Bits 0:3 - Endpoint Identifier
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Direction of transaction
pub fn esof(&self) -> ESOF_R[src]
Bit 8 - Expected start frame
pub fn sof(&self) -> SOF_R[src]
Bit 9 - start of frame
pub fn reset(&self) -> RESET_R[src]
Bit 10 - reset request
pub fn susp(&self) -> SUSP_R[src]
Bit 11 - Suspend mode request
pub fn wkup(&self) -> WKUP_R[src]
Bit 12 - Wakeup
pub fn err(&self) -> ERR_R[src]
Bit 13 - Error
pub fn pmaovr(&self) -> PMAOVR_R[src]
Bit 14 - Packet memory area over / underrun
pub fn ctr(&self) -> CTR_R[src]
Bit 15 - Correct transfer
impl R<bool, LCK_A>[src]
pub fn variant(&self) -> Variant<bool, LCK_A>[src]
Get enumerated values variant
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, RXDM_A>[src]
pub fn variant(&self) -> Variant<bool, RXDM_A>[src]
Get enumerated values variant
pub fn is_received(&self) -> bool[src]
Checks if the value of the field is RECEIVED
impl R<bool, RXDP_A>[src]
pub fn variant(&self) -> Variant<bool, RXDP_A>[src]
Get enumerated values variant
pub fn is_received(&self) -> bool[src]
Checks if the value of the field is RECEIVED
impl R<u32, Reg<u32, _FNR>>[src]
pub fn fn_(&self) -> FN_R[src]
Bits 0:10 - Frame number
pub fn lsof(&self) -> LSOF_R[src]
Bits 11:12 - Lost SOF
pub fn lck(&self) -> LCK_R[src]
Bit 13 - Locked
pub fn rxdm(&self) -> RXDM_R[src]
Bit 14 - Receive data - line status
pub fn rxdp(&self) -> RXDP_R[src]
Bit 15 - Receive data + line status
impl R<bool, EF_A>[src]
pub fn variant(&self) -> EF_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DADDR>>[src]
pub fn add(&self) -> ADD_R[src]
Bits 0:6 - Device address
pub fn ef(&self) -> EF_R[src]
Bit 7 - Enable function
impl R<u32, Reg<u32, _BTABLE>>[src]
impl R<u32, Reg<u32, _CR>>[src]
impl R<u8, WDGTB_A>[src]
pub fn variant(&self) -> WDGTB_A[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
pub fn is_div8(&self) -> bool[src]
Checks if the value of the field is DIV8
impl R<u32, Reg<u32, _CFR>>[src]
pub fn w(&self) -> W_R[src]
Bits 0:6 - 7-bit window value
pub fn wdgtb(&self) -> WDGTB_R[src]
Bits 7:8 - Timer base
impl R<bool, EWIF_A>[src]
pub fn variant(&self) -> EWIF_A[src]
Get enumerated values variant
pub fn is_pending(&self) -> bool[src]
Checks if the value of the field is PENDING
pub fn is_finished(&self) -> bool[src]
Checks if the value of the field is FINISHED
impl R<u32, Reg<u32, _SR>>[src]
impl R<u32, Reg<u32, _SR>>[src]
pub fn jcnr(&self) -> JCNR_R[src]
Bit 9 - Injected channel not ready
pub fn rcnr(&self) -> RCNR_R[src]
Bit 8 - Regular channel not ready
pub fn adons(&self) -> ADONS_R[src]
Bit 6 - ADC ON status
pub fn ovr(&self) -> OVR_R[src]
Bit 5 - Overrun
pub fn strt(&self) -> STRT_R[src]
Bit 4 - Regular channel start flag
pub fn jstrt(&self) -> JSTRT_R[src]
Bit 3 - Injected channel start flag
pub fn jeoc(&self) -> JEOC_R[src]
Bit 2 - Injected channel end of conversion
pub fn eoc(&self) -> EOC_R[src]
Bit 1 - Regular channel end of conversion
pub fn awd(&self) -> AWD_R[src]
Bit 0 - Analog watchdog flag
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ovrie(&self) -> OVRIE_R[src]
Bit 26 - Overrun interrupt enable
pub fn res(&self) -> RES_R[src]
Bits 24:25 - Resolution
pub fn awden(&self) -> AWDEN_R[src]
Bit 23 - Analog watchdog enable on regular channels
pub fn jawden(&self) -> JAWDEN_R[src]
Bit 22 - Analog watchdog enable on injected channels
pub fn pdi(&self) -> PDI_R[src]
Bit 17 - Power down during the idle phase
pub fn pdd(&self) -> PDD_R[src]
Bit 16 - Power down during the delay phase
pub fn discnum(&self) -> DISCNUM_R[src]
Bits 13:15 - Discontinuous mode channel count
pub fn jdiscen(&self) -> JDISCEN_R[src]
Bit 12 - Discontinuous mode on injected channels
pub fn discen(&self) -> DISCEN_R[src]
Bit 11 - Discontinuous mode on regular channels
pub fn jauto(&self) -> JAUTO_R[src]
Bit 10 - Automatic injected group conversion
pub fn awdsgl(&self) -> AWDSGL_R[src]
Bit 9 - Enable the watchdog on a single channel in scan mode
pub fn scan(&self) -> SCAN_R[src]
Bit 8 - Scan mode
pub fn jeocie(&self) -> JEOCIE_R[src]
Bit 7 - Interrupt enable for injected channels
pub fn awdie(&self) -> AWDIE_R[src]
Bit 6 - Analog watchdog interrupt enable
pub fn eocie(&self) -> EOCIE_R[src]
Bit 5 - Interrupt enable for EOC
pub fn awdch(&self) -> AWDCH_R[src]
Bits 0:4 - Analog watchdog channel select bits
impl R<u32, Reg<u32, _CR2>>[src]
pub fn swstart(&self) -> SWSTART_R[src]
Bit 30 - Start conversion of regular channels
pub fn exten(&self) -> EXTEN_R[src]
Bits 28:29 - External trigger enable for regular channels
pub fn extsel(&self) -> EXTSEL_R[src]
Bits 24:27 - External event select for regular group
pub fn jswstart(&self) -> JSWSTART_R[src]
Bit 22 - Start conversion of injected channels
pub fn jexten(&self) -> JEXTEN_R[src]
Bits 20:21 - External trigger enable for injected channels
pub fn jextsel(&self) -> JEXTSEL_R[src]
Bits 16:19 - External event select for injected group
pub fn align(&self) -> ALIGN_R[src]
Bit 11 - Data alignment
pub fn eocs(&self) -> EOCS_R[src]
Bit 10 - End of conversion selection
pub fn dds(&self) -> DDS_R[src]
Bit 9 - DMA disable selection
pub fn dma(&self) -> DMA_R[src]
Bit 8 - Direct memory access mode
pub fn dels(&self) -> DELS_R[src]
Bits 4:6 - Delay selection
pub fn adc_cfg(&self) -> ADC_CFG_R[src]
Bit 2 - ADC configuration
pub fn cont(&self) -> CONT_R[src]
Bit 1 - Continuous conversion
pub fn adon(&self) -> ADON_R[src]
Bit 0 - A/D Converter ON / OFF
impl R<u32, Reg<u32, _SMPR1>>[src]
impl R<u32, Reg<u32, _SMPR2>>[src]
impl R<u32, Reg<u32, _SMPR3>>[src]
impl R<u32, Reg<u32, _JOFR1>>[src]
pub fn joffset1(&self) -> JOFFSET1_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _JOFR2>>[src]
pub fn joffset2(&self) -> JOFFSET2_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _JOFR3>>[src]
pub fn joffset3(&self) -> JOFFSET3_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _JOFR4>>[src]
pub fn joffset4(&self) -> JOFFSET4_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _HTR>>[src]
impl R<u32, Reg<u32, _LTR>>[src]
impl R<u32, Reg<u32, _SQR1>>[src]
pub fn l(&self) -> L_R[src]
Bits 20:23 - Regular channel sequence length
pub fn sq28(&self) -> SQ28_R[src]
Bits 15:19 - 28th conversion in regular sequence
pub fn sq27(&self) -> SQ27_R[src]
Bits 10:14 - 27th conversion in regular sequence
pub fn sq26(&self) -> SQ26_R[src]
Bits 5:9 - 26th conversion in regular sequence
pub fn sq25(&self) -> SQ25_R[src]
Bits 0:4 - 25th conversion in regular sequence
impl R<u32, Reg<u32, _SQR2>>[src]
pub fn sq24(&self) -> SQ24_R[src]
Bits 25:29 - 24th conversion in regular sequence
pub fn sq23(&self) -> SQ23_R[src]
Bits 20:24 - 23rd conversion in regular sequence
pub fn sq22(&self) -> SQ22_R[src]
Bits 15:19 - 22nd conversion in regular sequence
pub fn sq21(&self) -> SQ21_R[src]
Bits 10:14 - 21st conversion in regular sequence
pub fn sq20(&self) -> SQ20_R[src]
Bits 5:9 - 20th conversion in regular sequence
pub fn sq19(&self) -> SQ19_R[src]
Bits 0:4 - 19th conversion in regular sequence
impl R<u32, Reg<u32, _SQR3>>[src]
pub fn sq18(&self) -> SQ18_R[src]
Bits 25:29 - 18th conversion in regular sequence
pub fn sq17(&self) -> SQ17_R[src]
Bits 20:24 - 17th conversion in regular sequence
pub fn sq16(&self) -> SQ16_R[src]
Bits 15:19 - 16th conversion in regular sequence
pub fn sq15(&self) -> SQ15_R[src]
Bits 10:14 - 15th conversion in regular sequence
pub fn sq14(&self) -> SQ14_R[src]
Bits 5:9 - 14th conversion in regular sequence
pub fn sq13(&self) -> SQ13_R[src]
Bits 0:4 - 13th conversion in regular sequence
impl R<u32, Reg<u32, _SQR4>>[src]
pub fn sq12(&self) -> SQ12_R[src]
Bits 25:29 - 12th conversion in regular sequence
pub fn sq11(&self) -> SQ11_R[src]
Bits 20:24 - 11th conversion in regular sequence
pub fn sq10(&self) -> SQ10_R[src]
Bits 15:19 - 10th conversion in regular sequence
pub fn sq9(&self) -> SQ9_R[src]
Bits 10:14 - 9th conversion in regular sequence
pub fn sq8(&self) -> SQ8_R[src]
Bits 5:9 - 8th conversion in regular sequence
pub fn sq7(&self) -> SQ7_R[src]
Bits 0:4 - 7th conversion in regular sequence
impl R<u32, Reg<u32, _SQR5>>[src]
pub fn sq6(&self) -> SQ6_R[src]
Bits 25:29 - 6th conversion in regular sequence
pub fn sq5(&self) -> SQ5_R[src]
Bits 20:24 - 5th conversion in regular sequence
pub fn sq4(&self) -> SQ4_R[src]
Bits 15:19 - 4th conversion in regular sequence
pub fn sq3(&self) -> SQ3_R[src]
Bits 10:14 - 3rd conversion in regular sequence
pub fn sq2(&self) -> SQ2_R[src]
Bits 5:9 - 2nd conversion in regular sequence
pub fn sq1(&self) -> SQ1_R[src]
Bits 0:4 - 1st conversion in regular sequence
impl R<u32, Reg<u32, _JSQR>>[src]
pub fn jl(&self) -> JL_R[src]
Bits 20:21 - Injected sequence length
pub fn jsq4(&self) -> JSQ4_R[src]
Bits 15:19 - 4th conversion in injected sequence
pub fn jsq3(&self) -> JSQ3_R[src]
Bits 10:14 - 3rd conversion in injected sequence
pub fn jsq2(&self) -> JSQ2_R[src]
Bits 5:9 - 2nd conversion in injected sequence
pub fn jsq1(&self) -> JSQ1_R[src]
Bits 0:4 - 1st conversion in injected sequence
impl R<u32, Reg<u32, _JDR1>>[src]
impl R<u32, Reg<u32, _JDR2>>[src]
impl R<u32, Reg<u32, _JDR3>>[src]
impl R<u32, Reg<u32, _JDR4>>[src]
impl R<u32, Reg<u32, _DR>>[src]
pub fn regular_data(&self) -> REGULARDATA_R[src]
Bits 0:15 - Regular data
impl R<u32, Reg<u32, _SMPR0>>[src]
impl R<u32, Reg<u32, _CSR>>[src]
pub fn awd1(&self) -> AWD1_R[src]
Bit 0 - Analog watchdog flag of the ADC
pub fn eoc1(&self) -> EOC1_R[src]
Bit 1 - End of conversion of the ADC
pub fn jeoc1(&self) -> JEOC1_R[src]
Bit 2 - Injected channel end of conversion of the ADC
pub fn jstrt1(&self) -> JSTRT1_R[src]
Bit 3 - Injected channel Start flag of the ADC
pub fn strt1(&self) -> STRT1_R[src]
Bit 4 - Regular channel Start flag of the ADC
pub fn ovr1(&self) -> OVR1_R[src]
Bit 5 - Overrun flag of the ADC
pub fn adons1(&self) -> ADONS1_R[src]
Bit 6 - ADON Status of ADC1
impl R<u32, Reg<u32, _CCR>>[src]
pub fn adcpre(&self) -> ADCPRE_R[src]
Bits 16:17 - ADC prescaler
pub fn tsvrefe(&self) -> TSVREFE_R[src]
Bit 23 - Temperature sensor and VREFINT enable
impl R<u32, Reg<u32, _IDCODE>>[src]
pub fn dev_id(&self) -> DEV_ID_R[src]
Bits 0:11 - Device identifier
pub fn rev_id(&self) -> REV_ID_R[src]
Bits 16:31 - Revision identifie
impl R<u32, Reg<u32, _CR>>[src]
pub fn dbg_sleep(&self) -> DBG_SLEEP_R[src]
Bit 0 - Debug Sleep mode
pub fn dbg_stop(&self) -> DBG_STOP_R[src]
Bit 1 - Debug Stop mode
pub fn dbg_standby(&self) -> DBG_STANDBY_R[src]
Bit 2 - Debug Standby mode
pub fn trace_ioen(&self) -> TRACE_IOEN_R[src]
Bit 5 - Trace pin assignment control
pub fn trace_mode(&self) -> TRACE_MODE_R[src]
Bits 6:7 - Trace pin assignment control
impl R<u32, Reg<u32, _APB1_FZ>>[src]
pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R[src]
Bit 0 - TIM2 counter stopped when core is halted
pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R[src]
Bit 1 - TIM3 counter stopped when core is halted
pub fn dbg_tim4_stop(&self) -> DBG_TIM4_STOP_R[src]
Bit 2 - TIM4 counter stopped when core is halted
pub fn dbg_tim5_stop(&self) -> DBG_TIM5_STOP_R[src]
Bit 3 - TIM5 counter stopped when core is halted
pub fn dbg_tim6_stop(&self) -> DBG_TIM6_STOP_R[src]
Bit 4 - TIM6 counter stopped when core is halted
pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R[src]
Bit 5 - TIM7 counter stopped when core is halted
pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R[src]
Bit 10 - Debug RTC stopped when core is halted
pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R[src]
Bit 11 - Debug window watchdog stopped when core is halted
pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R[src]
Bit 12 - Debug independent watchdog stopped when core is halted
pub fn dbg_i2c1_smbus_timeout(&self) -> DBG_I2C1_SMBUS_TIMEOUT_R[src]
Bit 21 - SMBUS timeout mode stopped when core is halted
pub fn dbg_i2c2_smbus_timeout(&self) -> DBG_I2C2_SMBUS_TIMEOUT_R[src]
Bit 22 - SMBUS timeout mode stopped when core is halted
impl R<u32, Reg<u32, _APB2_FZ>>[src]
pub fn dbg_tim9_stop(&self) -> DBG_TIM9_STOP_R[src]
Bit 2 - TIM counter stopped when core is halted
pub fn dbg_tim10_stop(&self) -> DBG_TIM10_STOP_R[src]
Bit 3 - TIM counter stopped when core is halted
pub fn dbg_tim11_stop(&self) -> DBG_TIM11_STOP_R[src]
Bit 4 - TIM counter stopped when core is halted
impl R<u32, Reg<u32, _POWER>>[src]
impl R<u32, Reg<u32, _CLKCR>>[src]
pub fn hwfc_en(&self) -> HWFC_EN_R[src]
Bit 14 - HW Flow Control enable
pub fn negedge(&self) -> NEGEDGE_R[src]
Bit 13 - SDIO_CK dephasing selection bit
pub fn widbus(&self) -> WIDBUS_R[src]
Bits 11:12 - Wide bus mode enable bit
pub fn bypass(&self) -> BYPASS_R[src]
Bit 10 - Clock divider bypass enable bit
pub fn pwrsav(&self) -> PWRSAV_R[src]
Bit 9 - Power saving configuration bit
pub fn clken(&self) -> CLKEN_R[src]
Bit 8 - Clock enable bit
pub fn clkdiv(&self) -> CLKDIV_R[src]
Bits 0:7 - Clock divide factor
impl R<u32, Reg<u32, _ARG>>[src]
impl R<u32, Reg<u32, _CMD>>[src]
pub fn ce_atacmd(&self) -> CE_ATACMD_R[src]
Bit 14 - CE-ATA command
pub fn n_ien(&self) -> NIEN_R[src]
Bit 13 - not Interrupt Enable
pub fn encmdcompl(&self) -> ENCMDCOMPL_R[src]
Bit 12 - Enable CMD completion
pub fn sdiosuspend(&self) -> SDIOSUSPEND_R[src]
Bit 11 - SD I/O suspend command
pub fn cpsmen(&self) -> CPSMEN_R[src]
Bit 10 - Command path state machine (CPSM) Enable bit
pub fn waitpend(&self) -> WAITPEND_R[src]
Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).
pub fn waitint(&self) -> WAITINT_R[src]
Bit 8 - CPSM waits for interrupt request
pub fn waitresp(&self) -> WAITRESP_R[src]
Bits 6:7 - Wait for response bits
pub fn cmdindex(&self) -> CMDINDEX_R[src]
Bits 0:5 - Command index
impl R<u32, Reg<u32, _RESPCMD>>[src]
impl R<u32, Reg<u32, _RESP1>>[src]
pub fn cardstatus1(&self) -> CARDSTATUS1_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _RESP2>>[src]
pub fn cardstatus2(&self) -> CARDSTATUS2_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _RESP3>>[src]
pub fn cardstatus3(&self) -> CARDSTATUS3_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _RESP4>>[src]
pub fn cardstatus4(&self) -> CARDSTATUS4_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _DTIMER>>[src]
pub fn datatime(&self) -> DATATIME_R[src]
Bits 0:31 - Data timeout period
impl R<u32, Reg<u32, _DLEN>>[src]
pub fn datalength(&self) -> DATALENGTH_R[src]
Bits 0:24 - Data length value
impl R<u32, Reg<u32, _DCTRL>>[src]
pub fn sdioen(&self) -> SDIOEN_R[src]
Bit 11 - SD I/O enable functions
pub fn rwmod(&self) -> RWMOD_R[src]
Bit 10 - Read wait mode
pub fn rwstop(&self) -> RWSTOP_R[src]
Bit 9 - Read wait stop
pub fn rwstart(&self) -> RWSTART_R[src]
Bit 8 - Read wait start
pub fn dblocksize(&self) -> DBLOCKSIZE_R[src]
Bits 4:7 - Data block size
pub fn dmaen(&self) -> DMAEN_R[src]
Bit 3 - DMA enable bit
pub fn dtmode(&self) -> DTMODE_R[src]
Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
pub fn dtdir(&self) -> DTDIR_R[src]
Bit 1 - Data transfer direction selection
pub fn dten(&self) -> DTEN_R[src]
Bit 0 - Data transfer enabled bit
impl R<u32, Reg<u32, _DCOUNT>>[src]
pub fn datacount(&self) -> DATACOUNT_R[src]
Bits 0:24 - Data count value
impl R<u32, Reg<u32, _STA>>[src]
pub fn ceataend(&self) -> CEATAEND_R[src]
Bit 23 - CE-ATA command completion signal received for CMD61
pub fn sdioit(&self) -> SDIOIT_R[src]
Bit 22 - SDIO interrupt received
pub fn rxdavl(&self) -> RXDAVL_R[src]
Bit 21 - Data available in receive FIFO
pub fn txdavl(&self) -> TXDAVL_R[src]
Bit 20 - Data available in transmit FIFO
pub fn rxfifoe(&self) -> RXFIFOE_R[src]
Bit 19 - Receive FIFO empty
pub fn txfifoe(&self) -> TXFIFOE_R[src]
Bit 18 - Transmit FIFO empty
pub fn rxfifof(&self) -> RXFIFOF_R[src]
Bit 17 - Receive FIFO full
pub fn txfifof(&self) -> TXFIFOF_R[src]
Bit 16 - Transmit FIFO full
pub fn rxfifohf(&self) -> RXFIFOHF_R[src]
Bit 15 - Receive FIFO half full: there are at least 8 words in the FIFO
pub fn txfifohe(&self) -> TXFIFOHE_R[src]
Bit 14 - Transmit FIFO half empty: at least 8 words can be written into the FIFO
pub fn rxact(&self) -> RXACT_R[src]
Bit 13 - Data receive in progress
pub fn txact(&self) -> TXACT_R[src]
Bit 12 - Data transmit in progress
pub fn cmdact(&self) -> CMDACT_R[src]
Bit 11 - Command transfer in progress
pub fn dbckend(&self) -> DBCKEND_R[src]
Bit 10 - Data block sent/received (CRC check passed)
pub fn stbiterr(&self) -> STBITERR_R[src]
Bit 9 - Start bit not detected on all data signals in wide bus mode
pub fn dataend(&self) -> DATAEND_R[src]
Bit 8 - Data end (data counter, SDIDCOUNT, is zero)
pub fn cmdsent(&self) -> CMDSENT_R[src]
Bit 7 - Command sent (no response required)
pub fn cmdrend(&self) -> CMDREND_R[src]
Bit 6 - Command response received (CRC check passed)
pub fn rxoverr(&self) -> RXOVERR_R[src]
Bit 5 - Received FIFO overrun error
pub fn txunderr(&self) -> TXUNDERR_R[src]
Bit 4 - Transmit FIFO underrun error
pub fn dtimeout(&self) -> DTIMEOUT_R[src]
Bit 3 - Data timeout
pub fn ctimeout(&self) -> CTIMEOUT_R[src]
Bit 2 - Command response timeout
pub fn dcrcfail(&self) -> DCRCFAIL_R[src]
Bit 1 - Data block sent/received (CRC check failed)
pub fn ccrcfail(&self) -> CCRCFAIL_R[src]
Bit 0 - Command response received (CRC check failed)
impl R<u32, Reg<u32, _ICR>>[src]
pub fn ceataendc(&self) -> CEATAENDC_R[src]
Bit 23 - CEATAEND flag clear bit
pub fn sdioitc(&self) -> SDIOITC_R[src]
Bit 22 - SDIOIT flag clear bit
pub fn dbckendc(&self) -> DBCKENDC_R[src]
Bit 10 - DBCKEND flag clear bit
pub fn stbiterrc(&self) -> STBITERRC_R[src]
Bit 9 - STBITERR flag clear bit
pub fn dataendc(&self) -> DATAENDC_R[src]
Bit 8 - DATAEND flag clear bit
pub fn cmdsentc(&self) -> CMDSENTC_R[src]
Bit 7 - CMDSENT flag clear bit
pub fn cmdrendc(&self) -> CMDRENDC_R[src]
Bit 6 - CMDREND flag clear bit
pub fn rxoverrc(&self) -> RXOVERRC_R[src]
Bit 5 - RXOVERR flag clear bit
pub fn txunderrc(&self) -> TXUNDERRC_R[src]
Bit 4 - TXUNDERR flag clear bit
pub fn dtimeoutc(&self) -> DTIMEOUTC_R[src]
Bit 3 - DTIMEOUT flag clear bit
pub fn ctimeoutc(&self) -> CTIMEOUTC_R[src]
Bit 2 - CTIMEOUT flag clear bit
pub fn dcrcfailc(&self) -> DCRCFAILC_R[src]
Bit 1 - DCRCFAIL flag clear bit
pub fn ccrcfailc(&self) -> CCRCFAILC_R[src]
Bit 0 - CCRCFAIL flag clear bit
impl R<u32, Reg<u32, _MASK>>[src]
pub fn ceataendie(&self) -> CEATAENDIE_R[src]
Bit 23 - CE-ATA command completion signal received interrupt enable
pub fn sdioitie(&self) -> SDIOITIE_R[src]
Bit 22 - SDIO mode interrupt received interrupt enable
pub fn rxdavlie(&self) -> RXDAVLIE_R[src]
Bit 21 - Data available in Rx FIFO interrupt enable
pub fn txdavlie(&self) -> TXDAVLIE_R[src]
Bit 20 - Data available in Tx FIFO interrupt enable
pub fn rxfifoeie(&self) -> RXFIFOEIE_R[src]
Bit 19 - Rx FIFO empty interrupt enable
pub fn txfifoeie(&self) -> TXFIFOEIE_R[src]
Bit 18 - Tx FIFO empty interrupt enable
pub fn rxfifofie(&self) -> RXFIFOFIE_R[src]
Bit 17 - Rx FIFO full interrupt enable
pub fn txfifofie(&self) -> TXFIFOFIE_R[src]
Bit 16 - Tx FIFO full interrupt enable
pub fn rxfifohfie(&self) -> RXFIFOHFIE_R[src]
Bit 15 - Rx FIFO half full interrupt enable
pub fn txfifoheie(&self) -> TXFIFOHEIE_R[src]
Bit 14 - Tx FIFO half empty interrupt enable
pub fn rxactie(&self) -> RXACTIE_R[src]
Bit 13 - Data receive acting interrupt enable
pub fn txactie(&self) -> TXACTIE_R[src]
Bit 12 - Data transmit acting interrupt enable
pub fn cmdactie(&self) -> CMDACTIE_R[src]
Bit 11 - Command acting interrupt enable
pub fn dbckendie(&self) -> DBCKENDIE_R[src]
Bit 10 - Data block end interrupt enable
pub fn stbiterrie(&self) -> STBITERRIE_R[src]
Bit 9 - Start bit error interrupt enable
pub fn dataendie(&self) -> DATAENDIE_R[src]
Bit 8 - Data end interrupt enable
pub fn cmdsentie(&self) -> CMDSENTIE_R[src]
Bit 7 - Command sent interrupt enable
pub fn cmdrendie(&self) -> CMDRENDIE_R[src]
Bit 6 - Command response received interrupt enable
pub fn rxoverrie(&self) -> RXOVERRIE_R[src]
Bit 5 - Rx FIFO overrun error interrupt enable
pub fn txunderrie(&self) -> TXUNDERRIE_R[src]
Bit 4 - Tx FIFO underrun error interrupt enable
pub fn dtimeoutie(&self) -> DTIMEOUTIE_R[src]
Bit 3 - Data timeout interrupt enable
pub fn ctimeoutie(&self) -> CTIMEOUTIE_R[src]
Bit 2 - Command timeout interrupt enable
pub fn dcrcfailie(&self) -> DCRCFAILIE_R[src]
Bit 1 - Data CRC fail interrupt enable
pub fn ccrcfailie(&self) -> CCRCFAILIE_R[src]
Bit 0 - Command CRC fail interrupt enable
impl R<u32, Reg<u32, _FIFOCNT>>[src]
pub fn fifocount(&self) -> FIFOCOUNT_R[src]
Bits 0:23 - Remaining number of words to be written to or read from the FIFO.
impl R<u32, Reg<u32, _FIFO>>[src]
pub fn fif0data(&self) -> FIF0DATA_R[src]
Bits 0:31 - FIF0Data
impl R<u32, Reg<u32, _ACTRL>>[src]
pub fn disfold(&self) -> DISFOLD_R[src]
Bit 2 - DISFOLD
pub fn fpexcodis(&self) -> FPEXCODIS_R[src]
Bit 10 - FPEXCODIS
pub fn disramode(&self) -> DISRAMODE_R[src]
Bit 11 - DISRAMODE
pub fn disitmatbflush(&self) -> DISITMATBFLUSH_R[src]
Bit 12 - DISITMATBFLUSH
impl R<u32, Reg<u32, _STIR>>[src]
impl R<u32, Reg<u32, _CTRL>>[src]
pub fn enable(&self) -> ENABLE_R[src]
Bit 0 - Counter enable
pub fn tickint(&self) -> TICKINT_R[src]
Bit 1 - SysTick exception request enable
pub fn clksource(&self) -> CLKSOURCE_R[src]
Bit 2 - Clock source selection
pub fn countflag(&self) -> COUNTFLAG_R[src]
Bit 16 - COUNTFLAG
impl R<u32, Reg<u32, _LOAD_>>[src]
impl R<u32, Reg<u32, _VAL>>[src]
impl R<u32, Reg<u32, _CALIB>>[src]
impl R<u32, Reg<u32, _CR>>[src]
pub fn dmaouten(&self) -> DMAOUTEN_R[src]
Bit 12 - Enable DMA management of data output phase
pub fn dmainen(&self) -> DMAINEN_R[src]
Bit 11 - Enable DMA management of data input phase
pub fn errie(&self) -> ERRIE_R[src]
Bit 10 - Error interrupt enable
pub fn ccfie(&self) -> CCFIE_R[src]
Bit 9 - CCF flag interrupt enable
pub fn errc(&self) -> ERRC_R[src]
Bit 8 - Error clear
pub fn ccfc(&self) -> CCFC_R[src]
Bit 7 - Computation Complete Flag Clear
pub fn chmod(&self) -> CHMOD_R[src]
Bits 5:6 - AES chaining mode
pub fn mode(&self) -> MODE_R[src]
Bits 3:4 - AES operating mode
pub fn datatype(&self) -> DATATYPE_R[src]
Bits 1:2 - Data type selection
pub fn en(&self) -> EN_R[src]
Bit 0 - AES enable
impl R<u32, Reg<u32, _SR>>[src]
pub fn wrerr(&self) -> WRERR_R[src]
Bit 2 - Write error flag
pub fn rderr(&self) -> RDERR_R[src]
Bit 1 - Read error flag
pub fn ccf(&self) -> CCF_R[src]
Bit 0 - Computation complete flag
impl R<u32, Reg<u32, _DINR>>[src]
impl R<u32, Reg<u32, _DOUTR>>[src]
impl R<u32, Reg<u32, _KEYR0>>[src]
impl R<u32, Reg<u32, _KEYR1>>[src]
impl R<u32, Reg<u32, _KEYR2>>[src]
impl R<u32, Reg<u32, _KEYR3>>[src]
impl R<u32, Reg<u32, _IVR0>>[src]
impl R<u32, Reg<u32, _IVR1>>[src]
impl R<u32, Reg<u32, _IVR2>>[src]
impl R<u32, Reg<u32, _IVR3>>[src]
impl R<u32, Reg<u32, _CSR>>[src]
pub fn tsusp(&self) -> TSUSP_R[src]
Bit 31 - Suspend Timer Mode
pub fn caif(&self) -> CAIF_R[src]
Bit 30 - Channel acquisition interrupt flag
pub fn caie(&self) -> CAIE_R[src]
Bit 29 - Channel Acquisition Interrupt Enable / Clear
pub fn rch13(&self) -> RCH13_R[src]
Bit 28 - Select GPIO port PC3 as re-routed ADC input channel CH13.
pub fn fch8(&self) -> FCH8_R[src]
Bit 27 - Select GPIO port PB0 as fast ADC input channel CH8.
pub fn fch3(&self) -> FCH3_R[src]
Bit 26 - Select GPIO port PA3 as fast ADC input channel CH3.
pub fn outsel(&self) -> OUTSEL_R[src]
Bits 21:23 - Comparator 2 output selection
pub fn insel(&self) -> INSEL_R[src]
Bits 18:20 - Inverted input selection
pub fn wndwe(&self) -> WNDWE_R[src]
Bit 17 - Window mode enable
pub fn vrefouten(&self) -> VREFOUTEN_R[src]
Bit 16 - VREFINT output enable
pub fn cmp2out(&self) -> CMP2OUT_R[src]
Bit 13 - Comparator 2 output
pub fn speed(&self) -> SPEED_R[src]
Bit 12 - Comparator 2 speed mode
pub fn cmp1out(&self) -> CMP1OUT_R[src]
Bit 7 - Comparator 1 output
pub fn sw1(&self) -> SW1_R[src]
Bit 5 - SW1 analog switch enable
pub fn cmp1en(&self) -> CMP1EN_R[src]
Bit 4 - Comparator 1 enable
pub fn pd400k(&self) -> PD400K_R[src]
Bit 3 - 400 kO pull-down resistor
pub fn pd10k(&self) -> PD10K_R[src]
Bit 2 - 10 kO pull-down resistor
pub fn pu400k(&self) -> PU400K_R[src]
Bit 1 - 400 kO pull-up resistor
pub fn pu10k(&self) -> PU10K_R[src]
Bit 0 - 10 kO pull-up resistor
impl R<u32, Reg<u32, _DR>>[src]
impl R<u32, Reg<u32, _IDR>>[src]
impl R<bool, DMAUDRIE2_A>[src]
pub fn variant(&self) -> DMAUDRIE2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, DMAEN2_A>[src]
pub fn variant(&self) -> DMAEN2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, WAVE2_A>[src]
pub fn variant(&self) -> Variant<u8, WAVE2_A>[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_noise(&self) -> bool[src]
Checks if the value of the field is NOISE
pub fn is_triangle(&self) -> bool[src]
Checks if the value of the field is TRIANGLE
impl R<u8, TSEL2_A>[src]
pub fn variant(&self) -> TSEL2_A[src]
Get enumerated values variant
pub fn is_tim6_trgo(&self) -> bool[src]
Checks if the value of the field is TIM6_TRGO
pub fn is_tim8_trgo(&self) -> bool[src]
Checks if the value of the field is TIM8_TRGO
pub fn is_tim7_trgo(&self) -> bool[src]
Checks if the value of the field is TIM7_TRGO
pub fn is_tim5_trgo(&self) -> bool[src]
Checks if the value of the field is TIM5_TRGO
pub fn is_tim2_trgo(&self) -> bool[src]
Checks if the value of the field is TIM2_TRGO
pub fn is_tim4_trgo(&self) -> bool[src]
Checks if the value of the field is TIM4_TRGO
pub fn is_exti9(&self) -> bool[src]
Checks if the value of the field is EXTI9
pub fn is_software(&self) -> bool[src]
Checks if the value of the field is SOFTWARE
impl R<bool, TEN2_A>[src]
pub fn variant(&self) -> TEN2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, BOFF2_A>[src]
pub fn variant(&self) -> BOFF2_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, EN2_A>[src]
pub fn variant(&self) -> EN2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, WAVE1_A>[src]
pub fn variant(&self) -> Variant<u8, WAVE1_A>[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_noise(&self) -> bool[src]
Checks if the value of the field is NOISE
pub fn is_triangle(&self) -> bool[src]
Checks if the value of the field is TRIANGLE
impl R<u8, TSEL1_A>[src]
pub fn variant(&self) -> Variant<u8, TSEL1_A>[src]
Get enumerated values variant
pub fn is_tim6_trgo(&self) -> bool[src]
Checks if the value of the field is TIM6_TRGO
pub fn is_tim3_trgo(&self) -> bool[src]
Checks if the value of the field is TIM3_TRGO
pub fn is_tim7_trgo(&self) -> bool[src]
Checks if the value of the field is TIM7_TRGO
pub fn is_tim15_trgo(&self) -> bool[src]
Checks if the value of the field is TIM15_TRGO
pub fn is_tim2_trgo(&self) -> bool[src]
Checks if the value of the field is TIM2_TRGO
pub fn is_exti9(&self) -> bool[src]
Checks if the value of the field is EXTI9
pub fn is_software(&self) -> bool[src]
Checks if the value of the field is SOFTWARE
impl R<u32, Reg<u32, _CR>>[src]
pub fn dmaudrie2(&self) -> DMAUDRIE2_R[src]
Bit 29 - DAC channel2 DMA underrun interrupt enable
pub fn dmaen2(&self) -> DMAEN2_R[src]
Bit 28 - DAC channel2 DMA enable
pub fn mamp2(&self) -> MAMP2_R[src]
Bits 24:27 - DAC channel2 mask/amplitude selector
pub fn wave2(&self) -> WAVE2_R[src]
Bits 22:23 - DAC channel2 noise/triangle wave generation enable
pub fn tsel2(&self) -> TSEL2_R[src]
Bits 19:21 - DAC channel2 trigger selection
pub fn ten2(&self) -> TEN2_R[src]
Bit 18 - DAC channel2 trigger enable
pub fn boff2(&self) -> BOFF2_R[src]
Bit 17 - DAC channel2 output buffer disable
pub fn en2(&self) -> EN2_R[src]
Bit 16 - DAC channel2 enable
pub fn dmaudrie1(&self) -> DMAUDRIE1_R[src]
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
pub fn dmaen1(&self) -> DMAEN1_R[src]
Bit 12 - DAC channel1 DMA enable
pub fn mamp1(&self) -> MAMP1_R[src]
Bits 8:11 - DAC channel1 mask/amplitude selector
pub fn wave1(&self) -> WAVE1_R[src]
Bits 6:7 - DAC channel1 noise/triangle wave generation enable
pub fn tsel1(&self) -> TSEL1_R[src]
Bits 3:5 - DAC channel1 trigger selection
pub fn ten1(&self) -> TEN1_R[src]
Bit 2 - DAC channel1 trigger enable
pub fn boff1(&self) -> BOFF1_R[src]
Bit 1 - DAC channel1 output buffer disable
pub fn en1(&self) -> EN1_R[src]
Bit 0 - DAC channel1 enable
impl R<u32, Reg<u32, _DHR12R1>>[src]
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
impl R<u32, Reg<u32, _DHR12L1>>[src]
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
impl R<u32, Reg<u32, _DHR8R1>>[src]
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl R<u32, Reg<u32, _DHR12R2>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 0:11 - DAC channel2 12-bit right-aligned data
impl R<u32, Reg<u32, _DHR12L2>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 4:15 - DAC channel2 12-bit left-aligned data
impl R<u32, Reg<u32, _DHR8R2>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 0:7 - DAC channel2 8-bit right-aligned data
impl R<u32, Reg<u32, _DHR12RD>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 16:27 - DAC channel2 12-bit right-aligned data
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
impl R<u32, Reg<u32, _DHR12LD>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 20:31 - DAC channel2 12-bit left-aligned data
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
impl R<u32, Reg<u32, _DHR8RD>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 8:15 - DAC channel2 8-bit right-aligned data
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl R<u32, Reg<u32, _DOR1>>[src]
pub fn dacc1dor(&self) -> DACC1DOR_R[src]
Bits 0:11 - DAC channel1 data output
impl R<u32, Reg<u32, _DOR2>>[src]
pub fn dacc2dor(&self) -> DACC2DOR_R[src]
Bits 0:11 - DAC channel2 data output
impl R<bool, DMAUDR2_A>[src]
pub fn variant(&self) -> DMAUDR2_A[src]
Get enumerated values variant
pub fn is_no_underrun(&self) -> bool[src]
Checks if the value of the field is NOUNDERRUN
pub fn is_underrun(&self) -> bool[src]
Checks if the value of the field is UNDERRUN
impl R<u32, Reg<u32, _SR>>[src]
pub fn dmaudr2(&self) -> DMAUDR2_R[src]
Bit 29 - DAC channel2 DMA underrun flag
pub fn dmaudr1(&self) -> DMAUDR1_R[src]
Bit 13 - DAC channel1 DMA underrun flag
impl R<u32, Reg<u32, _ISR>>[src]
pub fn teif7(&self) -> TEIF7_R[src]
Bit 27 - Channel x transfer error flag (x = 1 ..7)
pub fn htif7(&self) -> HTIF7_R[src]
Bit 26 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif7(&self) -> TCIF7_R[src]
Bit 25 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif7(&self) -> GIF7_R[src]
Bit 24 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif6(&self) -> TEIF6_R[src]
Bit 23 - Channel x transfer error flag (x = 1 ..7)
pub fn htif6(&self) -> HTIF6_R[src]
Bit 22 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif6(&self) -> TCIF6_R[src]
Bit 21 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif6(&self) -> GIF6_R[src]
Bit 20 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif5(&self) -> TEIF5_R[src]
Bit 19 - Channel x transfer error flag (x = 1 ..7)
pub fn htif5(&self) -> HTIF5_R[src]
Bit 18 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif5(&self) -> TCIF5_R[src]
Bit 17 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif5(&self) -> GIF5_R[src]
Bit 16 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif4(&self) -> TEIF4_R[src]
Bit 15 - Channel x transfer error flag (x = 1 ..7)
pub fn htif4(&self) -> HTIF4_R[src]
Bit 14 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif4(&self) -> TCIF4_R[src]
Bit 13 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif4(&self) -> GIF4_R[src]
Bit 12 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif3(&self) -> TEIF3_R[src]
Bit 11 - Channel x transfer error flag (x = 1 ..7)
pub fn htif3(&self) -> HTIF3_R[src]
Bit 10 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif3(&self) -> TCIF3_R[src]
Bit 9 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif3(&self) -> GIF3_R[src]
Bit 8 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif2(&self) -> TEIF2_R[src]
Bit 7 - Channel x transfer error flag (x = 1 ..7)
pub fn htif2(&self) -> HTIF2_R[src]
Bit 6 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif2(&self) -> TCIF2_R[src]
Bit 5 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif2(&self) -> GIF2_R[src]
Bit 4 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif1(&self) -> TEIF1_R[src]
Bit 3 - Channel x transfer error flag (x = 1 ..7)
pub fn htif1(&self) -> HTIF1_R[src]
Bit 2 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif1(&self) -> TCIF1_R[src]
Bit 1 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif1(&self) -> GIF1_R[src]
Bit 0 - Channel x global interrupt flag (x = 1 ..7)
impl R<u32, Reg<u32, _CCR1>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR1>>[src]
impl R<u32, Reg<u32, _CPAR1>>[src]
impl R<u32, Reg<u32, _CMAR1>>[src]
impl R<u32, Reg<u32, _CCR2>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR2>>[src]
impl R<u32, Reg<u32, _CPAR2>>[src]
impl R<u32, Reg<u32, _CMAR2>>[src]
impl R<u32, Reg<u32, _CCR3>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR3>>[src]
impl R<u32, Reg<u32, _CPAR3>>[src]
impl R<u32, Reg<u32, _CMAR3>>[src]
impl R<u32, Reg<u32, _CCR4>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR4>>[src]
impl R<u32, Reg<u32, _CPAR4>>[src]
impl R<u32, Reg<u32, _CMAR4>>[src]
impl R<u32, Reg<u32, _CCR5>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR5>>[src]
impl R<u32, Reg<u32, _CPAR5>>[src]
impl R<u32, Reg<u32, _CMAR5>>[src]
impl R<u32, Reg<u32, _CCR6>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR6>>[src]
impl R<u32, Reg<u32, _CPAR6>>[src]
impl R<u32, Reg<u32, _CMAR6>>[src]
impl R<u32, Reg<u32, _CCR7>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR7>>[src]
impl R<u32, Reg<u32, _CPAR7>>[src]
impl R<u32, Reg<u32, _CMAR7>>[src]
impl R<bool, MR0_A>[src]
pub fn variant(&self) -> MR0_A[src]
Get enumerated values variant
pub fn is_masked(&self) -> bool[src]
Checks if the value of the field is MASKED
pub fn is_unmasked(&self) -> bool[src]
Checks if the value of the field is UNMASKED
impl R<u32, Reg<u32, _IMR>>[src]
pub fn mr0(&self) -> MR0_R[src]
Bit 0 - Interrupt mask on line x
pub fn mr1(&self) -> MR1_R[src]
Bit 1 - Interrupt mask on line x
pub fn mr2(&self) -> MR2_R[src]
Bit 2 - Interrupt mask on line x
pub fn mr3(&self) -> MR3_R[src]
Bit 3 - Interrupt mask on line x
pub fn mr4(&self) -> MR4_R[src]
Bit 4 - Interrupt mask on line x
pub fn mr5(&self) -> MR5_R[src]
Bit 5 - Interrupt mask on line x
pub fn mr6(&self) -> MR6_R[src]
Bit 6 - Interrupt mask on line x
pub fn mr7(&self) -> MR7_R[src]
Bit 7 - Interrupt mask on line x
pub fn mr8(&self) -> MR8_R[src]
Bit 8 - Interrupt mask on line x
pub fn mr9(&self) -> MR9_R[src]
Bit 9 - Interrupt mask on line x
pub fn mr10(&self) -> MR10_R[src]
Bit 10 - Interrupt mask on line x
pub fn mr11(&self) -> MR11_R[src]
Bit 11 - Interrupt mask on line x
pub fn mr12(&self) -> MR12_R[src]
Bit 12 - Interrupt mask on line x
pub fn mr13(&self) -> MR13_R[src]
Bit 13 - Interrupt mask on line x
pub fn mr14(&self) -> MR14_R[src]
Bit 14 - Interrupt mask on line x
pub fn mr15(&self) -> MR15_R[src]
Bit 15 - Interrupt mask on line x
pub fn mr16(&self) -> MR16_R[src]
Bit 16 - Interrupt mask on line x
pub fn mr17(&self) -> MR17_R[src]
Bit 17 - Interrupt mask on line x
pub fn mr18(&self) -> MR18_R[src]
Bit 18 - Interrupt mask on line x
pub fn mr19(&self) -> MR19_R[src]
Bit 19 - Interrupt mask on line x
pub fn mr20(&self) -> MR20_R[src]
Bit 20 - Interrupt mask on line x
pub fn mr21(&self) -> MR21_R[src]
Bit 21 - Interrupt mask on line x
pub fn mr22(&self) -> MR22_R[src]
Bit 22 - Interrupt mask on line x
impl R<bool, MR0_A>[src]
pub fn variant(&self) -> MR0_A[src]
Get enumerated values variant
pub fn is_masked(&self) -> bool[src]
Checks if the value of the field is MASKED
pub fn is_unmasked(&self) -> bool[src]
Checks if the value of the field is UNMASKED
impl R<u32, Reg<u32, _EMR>>[src]
pub fn mr0(&self) -> MR0_R[src]
Bit 0 - Event mask on line x
pub fn mr1(&self) -> MR1_R[src]
Bit 1 - Event mask on line x
pub fn mr2(&self) -> MR2_R[src]
Bit 2 - Event mask on line x
pub fn mr3(&self) -> MR3_R[src]
Bit 3 - Event mask on line x
pub fn mr4(&self) -> MR4_R[src]
Bit 4 - Event mask on line x
pub fn mr5(&self) -> MR5_R[src]
Bit 5 - Event mask on line x
pub fn mr6(&self) -> MR6_R[src]
Bit 6 - Event mask on line x
pub fn mr7(&self) -> MR7_R[src]
Bit 7 - Event mask on line x
pub fn mr8(&self) -> MR8_R[src]
Bit 8 - Event mask on line x
pub fn mr9(&self) -> MR9_R[src]
Bit 9 - Event mask on line x
pub fn mr10(&self) -> MR10_R[src]
Bit 10 - Event mask on line x
pub fn mr11(&self) -> MR11_R[src]
Bit 11 - Event mask on line x
pub fn mr12(&self) -> MR12_R[src]
Bit 12 - Event mask on line x
pub fn mr13(&self) -> MR13_R[src]
Bit 13 - Event mask on line x
pub fn mr14(&self) -> MR14_R[src]
Bit 14 - Event mask on line x
pub fn mr15(&self) -> MR15_R[src]
Bit 15 - Event mask on line x
pub fn mr16(&self) -> MR16_R[src]
Bit 16 - Event mask on line x
pub fn mr17(&self) -> MR17_R[src]
Bit 17 - Event mask on line x
pub fn mr18(&self) -> MR18_R[src]
Bit 18 - Event mask on line x
pub fn mr19(&self) -> MR19_R[src]
Bit 19 - Event mask on line x
pub fn mr20(&self) -> MR20_R[src]
Bit 20 - Event mask on line x
pub fn mr21(&self) -> MR21_R[src]
Bit 21 - Event mask on line x
pub fn mr22(&self) -> MR22_R[src]
Bit 22 - Event mask on line x
impl R<bool, TR0_A>[src]
pub fn variant(&self) -> TR0_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _RTSR>>[src]
pub fn tr0(&self) -> TR0_R[src]
Bit 0 - Rising edge trigger event configuration bit of line x
pub fn tr1(&self) -> TR1_R[src]
Bit 1 - Rising edge trigger event configuration bit of line x
pub fn tr2(&self) -> TR2_R[src]
Bit 2 - Rising edge trigger event configuration bit of line x
pub fn tr3(&self) -> TR3_R[src]
Bit 3 - Rising edge trigger event configuration bit of line x
pub fn tr4(&self) -> TR4_R[src]
Bit 4 - Rising edge trigger event configuration bit of line x
pub fn tr5(&self) -> TR5_R[src]
Bit 5 - Rising edge trigger event configuration bit of line x
pub fn tr6(&self) -> TR6_R[src]
Bit 6 - Rising edge trigger event configuration bit of line x
pub fn tr7(&self) -> TR7_R[src]
Bit 7 - Rising edge trigger event configuration bit of line x
pub fn tr8(&self) -> TR8_R[src]
Bit 8 - Rising edge trigger event configuration bit of line x
pub fn tr9(&self) -> TR9_R[src]
Bit 9 - Rising edge trigger event configuration bit of line x
pub fn tr10(&self) -> TR10_R[src]
Bit 10 - Rising edge trigger event configuration bit of line x
pub fn tr11(&self) -> TR11_R[src]
Bit 11 - Rising edge trigger event configuration bit of line x
pub fn tr12(&self) -> TR12_R[src]
Bit 12 - Rising edge trigger event configuration bit of line x
pub fn tr13(&self) -> TR13_R[src]
Bit 13 - Rising edge trigger event configuration bit of line x
pub fn tr14(&self) -> TR14_R[src]
Bit 14 - Rising edge trigger event configuration bit of line x
pub fn tr15(&self) -> TR15_R[src]
Bit 15 - Rising edge trigger event configuration bit of line x
pub fn tr16(&self) -> TR16_R[src]
Bit 16 - Rising edge trigger event configuration bit of line x
pub fn tr17(&self) -> TR17_R[src]
Bit 17 - Rising edge trigger event configuration bit of line x
pub fn tr18(&self) -> TR18_R[src]
Bit 18 - Rising edge trigger event configuration bit of line x
pub fn tr19(&self) -> TR19_R[src]
Bit 19 - Rising edge trigger event configuration bit of line x
pub fn tr20(&self) -> TR20_R[src]
Bit 20 - Rising edge trigger event configuration bit of line x
pub fn tr21(&self) -> TR21_R[src]
Bit 21 - Rising edge trigger event configuration bit of line x
pub fn tr22(&self) -> TR22_R[src]
Bit 22 - Rising edge trigger event configuration bit of line x
impl R<bool, TR0_A>[src]
pub fn variant(&self) -> TR0_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _FTSR>>[src]
pub fn tr0(&self) -> TR0_R[src]
Bit 0 - Falling edge trigger event configuration bit of line x
pub fn tr1(&self) -> TR1_R[src]
Bit 1 - Falling edge trigger event configuration bit of line x
pub fn tr2(&self) -> TR2_R[src]
Bit 2 - Falling edge trigger event configuration bit of line x
pub fn tr3(&self) -> TR3_R[src]
Bit 3 - Falling edge trigger event configuration bit of line x
pub fn tr4(&self) -> TR4_R[src]
Bit 4 - Falling edge trigger event configuration bit of line x
pub fn tr5(&self) -> TR5_R[src]
Bit 5 - Falling edge trigger event configuration bit of line x
pub fn tr6(&self) -> TR6_R[src]
Bit 6 - Falling edge trigger event configuration bit of line x
pub fn tr7(&self) -> TR7_R[src]
Bit 7 - Falling edge trigger event configuration bit of line x
pub fn tr8(&self) -> TR8_R[src]
Bit 8 - Falling edge trigger event configuration bit of line x
pub fn tr9(&self) -> TR9_R[src]
Bit 9 - Falling edge trigger event configuration bit of line x
pub fn tr10(&self) -> TR10_R[src]
Bit 10 - Falling edge trigger event configuration bit of line x
pub fn tr11(&self) -> TR11_R[src]
Bit 11 - Falling edge trigger event configuration bit of line x
pub fn tr12(&self) -> TR12_R[src]
Bit 12 - Falling edge trigger event configuration bit of line x
pub fn tr13(&self) -> TR13_R[src]
Bit 13 - Falling edge trigger event configuration bit of line x
pub fn tr14(&self) -> TR14_R[src]
Bit 14 - Falling edge trigger event configuration bit of line x
pub fn tr15(&self) -> TR15_R[src]
Bit 15 - Falling edge trigger event configuration bit of line x
pub fn tr16(&self) -> TR16_R[src]
Bit 16 - Falling edge trigger event configuration bit of line x
pub fn tr17(&self) -> TR17_R[src]
Bit 17 - Falling edge trigger event configuration bit of line x
pub fn tr18(&self) -> TR18_R[src]
Bit 18 - Falling edge trigger event configuration bit of line x
pub fn tr19(&self) -> TR19_R[src]
Bit 19 - Falling edge trigger event configuration bit of line x
pub fn tr20(&self) -> TR20_R[src]
Bit 20 - Falling edge trigger event configuration bit of line x
pub fn tr21(&self) -> TR21_R[src]
Bit 21 - Falling edge trigger event configuration bit of line x
pub fn tr22(&self) -> TR22_R[src]
Bit 22 - Falling edge trigger event configuration bit of line x
impl R<bool, SWIER0_A>[src]
pub fn variant(&self) -> Variant<bool, SWIER0_A>[src]
Get enumerated values variant
pub fn is_pend(&self) -> bool[src]
Checks if the value of the field is PEND
impl R<u32, Reg<u32, _SWIER>>[src]
pub fn swier0(&self) -> SWIER0_R[src]
Bit 0 - Software interrupt on line x
pub fn swier1(&self) -> SWIER1_R[src]
Bit 1 - Software interrupt on line x
pub fn swier2(&self) -> SWIER2_R[src]
Bit 2 - Software interrupt on line x
pub fn swier3(&self) -> SWIER3_R[src]
Bit 3 - Software interrupt on line x
pub fn swier4(&self) -> SWIER4_R[src]
Bit 4 - Software interrupt on line x
pub fn swier5(&self) -> SWIER5_R[src]
Bit 5 - Software interrupt on line x
pub fn swier6(&self) -> SWIER6_R[src]
Bit 6 - Software interrupt on line x
pub fn swier7(&self) -> SWIER7_R[src]
Bit 7 - Software interrupt on line x
pub fn swier8(&self) -> SWIER8_R[src]
Bit 8 - Software interrupt on line x
pub fn swier9(&self) -> SWIER9_R[src]
Bit 9 - Software interrupt on line x
pub fn swier10(&self) -> SWIER10_R[src]
Bit 10 - Software interrupt on line x
pub fn swier11(&self) -> SWIER11_R[src]
Bit 11 - Software interrupt on line x
pub fn swier12(&self) -> SWIER12_R[src]
Bit 12 - Software interrupt on line x
pub fn swier13(&self) -> SWIER13_R[src]
Bit 13 - Software interrupt on line x
pub fn swier14(&self) -> SWIER14_R[src]
Bit 14 - Software interrupt on line x
pub fn swier15(&self) -> SWIER15_R[src]
Bit 15 - Software interrupt on line x
pub fn swier16(&self) -> SWIER16_R[src]
Bit 16 - Software interrupt on line x
pub fn swier17(&self) -> SWIER17_R[src]
Bit 17 - Software interrupt on line x
pub fn swier18(&self) -> SWIER18_R[src]
Bit 18 - Software interrupt on line x
pub fn swier19(&self) -> SWIER19_R[src]
Bit 19 - Software interrupt on line x
pub fn swier20(&self) -> SWIER20_R[src]
Bit 20 - Software interrupt on line x
pub fn swier21(&self) -> SWIER21_R[src]
Bit 21 - Software interrupt on line x
pub fn swier22(&self) -> SWIER22_R[src]
Bit 22 - Software interrupt on line x
impl R<bool, PR0_A>[src]
pub fn variant(&self) -> PR0_A[src]
Get enumerated values variant
pub fn is_not_pending(&self) -> bool[src]
Checks if the value of the field is NOTPENDING
pub fn is_pending(&self) -> bool[src]
Checks if the value of the field is PENDING
impl R<u32, Reg<u32, _PR>>[src]
pub fn pr0(&self) -> PR0_R[src]
Bit 0 - Pending bit
pub fn pr1(&self) -> PR1_R[src]
Bit 1 - Pending bit
pub fn pr2(&self) -> PR2_R[src]
Bit 2 - Pending bit
pub fn pr3(&self) -> PR3_R[src]
Bit 3 - Pending bit
pub fn pr4(&self) -> PR4_R[src]
Bit 4 - Pending bit
pub fn pr5(&self) -> PR5_R[src]
Bit 5 - Pending bit
pub fn pr6(&self) -> PR6_R[src]
Bit 6 - Pending bit
pub fn pr7(&self) -> PR7_R[src]
Bit 7 - Pending bit
pub fn pr8(&self) -> PR8_R[src]
Bit 8 - Pending bit
pub fn pr9(&self) -> PR9_R[src]
Bit 9 - Pending bit
pub fn pr10(&self) -> PR10_R[src]
Bit 10 - Pending bit
pub fn pr11(&self) -> PR11_R[src]
Bit 11 - Pending bit
pub fn pr12(&self) -> PR12_R[src]
Bit 12 - Pending bit
pub fn pr13(&self) -> PR13_R[src]
Bit 13 - Pending bit
pub fn pr14(&self) -> PR14_R[src]
Bit 14 - Pending bit
pub fn pr15(&self) -> PR15_R[src]
Bit 15 - Pending bit
pub fn pr16(&self) -> PR16_R[src]
Bit 16 - Pending bit
pub fn pr17(&self) -> PR17_R[src]
Bit 17 - Pending bit
pub fn pr18(&self) -> PR18_R[src]
Bit 18 - Pending bit
pub fn pr19(&self) -> PR19_R[src]
Bit 19 - Pending bit
pub fn pr20(&self) -> PR20_R[src]
Bit 20 - Pending bit
pub fn pr21(&self) -> PR21_R[src]
Bit 21 - Pending bit
pub fn pr22(&self) -> PR22_R[src]
Bit 22 - Pending bit
impl R<u32, Reg<u32, _ACR>>[src]
pub fn latency(&self) -> LATENCY_R[src]
Bit 0 - Latency
pub fn prften(&self) -> PRFTEN_R[src]
Bit 1 - Prefetch enable
pub fn acc64(&self) -> ACC64_R[src]
Bit 2 - 64-bit access
pub fn sleep_pd(&self) -> SLEEP_PD_R[src]
Bit 3 - Flash mode during Sleep
pub fn run_pd(&self) -> RUN_PD_R[src]
Bit 4 - Flash mode during Run
impl R<u32, Reg<u32, _PECR>>[src]
pub fn pelock(&self) -> PELOCK_R[src]
Bit 0 - FLASH_PECR and data EEPROM lock
pub fn prglock(&self) -> PRGLOCK_R[src]
Bit 1 - Program memory lock
pub fn optlock(&self) -> OPTLOCK_R[src]
Bit 2 - Option bytes block lock
pub fn prog(&self) -> PROG_R[src]
Bit 3 - Program memory selection
pub fn data(&self) -> DATA_R[src]
Bit 4 - Data EEPROM selection
pub fn ftdw(&self) -> FTDW_R[src]
Bit 8 - Fixed time data write for Byte, Half Word and Word programming
pub fn erase(&self) -> ERASE_R[src]
Bit 9 - Page or Double Word erase mode
pub fn fprg(&self) -> FPRG_R[src]
Bit 10 - Half Page/Double Word programming mode
pub fn parallelbank(&self) -> PARALLELBANK_R[src]
Bit 15 - Parallel bank mode
pub fn eopie(&self) -> EOPIE_R[src]
Bit 16 - End of programming interrupt enable
pub fn errie(&self) -> ERRIE_R[src]
Bit 17 - Error interrupt enable
pub fn obl_launch(&self) -> OBL_LAUNCH_R[src]
Bit 18 - Launch the option byte loading
impl R<u32, Reg<u32, _SR>>[src]
pub fn bsy(&self) -> BSY_R[src]
Bit 0 - Write/erase operations in progress
pub fn eop(&self) -> EOP_R[src]
Bit 1 - End of operation
pub fn endhv(&self) -> ENDHV_R[src]
Bit 2 - End of high voltage
pub fn ready(&self) -> READY_R[src]
Bit 3 - Flash memory module ready after low power mode
pub fn wrperr(&self) -> WRPERR_R[src]
Bit 8 - Write protected error
pub fn pgaerr(&self) -> PGAERR_R[src]
Bit 9 - Programming alignment error
pub fn sizerr(&self) -> SIZERR_R[src]
Bit 10 - Size error
pub fn optverr(&self) -> OPTVERR_R[src]
Bit 11 - Option validity error
pub fn optverrusr(&self) -> OPTVERRUSR_R[src]
Bit 12 - Option UserValidity Error
impl R<u32, Reg<u32, _OBR>>[src]
pub fn rdprt(&self) -> RDPRT_R[src]
Bits 0:7 - Read protection
pub fn bor_lev(&self) -> BOR_LEV_R[src]
Bits 16:19 - BOR_LEV
pub fn iwdg_sw(&self) -> IWDG_SW_R[src]
Bit 20 - IWDG_SW
pub fn n_rts_stop(&self) -> NRTS_STOP_R[src]
Bit 21 - nRTS_STOP
pub fn n_rst_stdby(&self) -> NRST_STDBY_R[src]
Bit 22 - nRST_STDBY
pub fn bfb2(&self) -> BFB2_R[src]
Bit 23 - Boot From Bank 2
impl R<u32, Reg<u32, _WRPR1>>[src]
impl R<u32, Reg<u32, _WRPR2>>[src]
impl R<u32, Reg<u32, _WRPR3>>[src]
impl R<bool, CBURSTRW_A>[src]
pub fn variant(&self) -> CBURSTRW_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, ASYNCWAIT_A>[src]
pub fn variant(&self) -> ASYNCWAIT_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, EXTMOD_A>[src]
pub fn variant(&self) -> EXTMOD_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITEN_A>[src]
pub fn variant(&self) -> WAITEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WREN_A>[src]
pub fn variant(&self) -> WREN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITCFG_A>[src]
pub fn variant(&self) -> WAITCFG_A[src]
Get enumerated values variant
pub fn is_before_wait_state(&self) -> bool[src]
Checks if the value of the field is BEFOREWAITSTATE
pub fn is_during_wait_state(&self) -> bool[src]
Checks if the value of the field is DURINGWAITSTATE
impl R<bool, WAITPOL_A>[src]
pub fn variant(&self) -> WAITPOL_A[src]
Get enumerated values variant
pub fn is_active_low(&self) -> bool[src]
Checks if the value of the field is ACTIVELOW
pub fn is_active_high(&self) -> bool[src]
Checks if the value of the field is ACTIVEHIGH
impl R<bool, BURSTEN_A>[src]
pub fn variant(&self) -> BURSTEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, FACCEN_A>[src]
pub fn variant(&self) -> FACCEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, MWID_A>[src]
pub fn variant(&self) -> Variant<u8, MWID_A>[src]
Get enumerated values variant
pub fn is_bits8(&self) -> bool[src]
Checks if the value of the field is BITS8
pub fn is_bits16(&self) -> bool[src]
Checks if the value of the field is BITS16
pub fn is_bits32(&self) -> bool[src]
Checks if the value of the field is BITS32
impl R<u8, MTYP_A>[src]
pub fn variant(&self) -> Variant<u8, MTYP_A>[src]
Get enumerated values variant
pub fn is_sram(&self) -> bool[src]
Checks if the value of the field is SRAM
pub fn is_psram(&self) -> bool[src]
Checks if the value of the field is PSRAM
pub fn is_flash(&self) -> bool[src]
Checks if the value of the field is FLASH
impl R<bool, MUXEN_A>[src]
pub fn variant(&self) -> MUXEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, MBKEN_A>[src]
pub fn variant(&self) -> MBKEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CPSIZE_A>[src]
pub fn variant(&self) -> Variant<u8, CPSIZE_A>[src]
Get enumerated values variant
pub fn is_no_burst_split(&self) -> bool[src]
Checks if the value of the field is NOBURSTSPLIT
pub fn is_bytes128(&self) -> bool[src]
Checks if the value of the field is BYTES128
pub fn is_bytes256(&self) -> bool[src]
Checks if the value of the field is BYTES256
pub fn is_bytes512(&self) -> bool[src]
Checks if the value of the field is BYTES512
pub fn is_bytes1024(&self) -> bool[src]
Checks if the value of the field is BYTES1024
impl R<u32, Reg<u32, _BCR1>>[src]
pub fn cburstrw(&self) -> CBURSTRW_R[src]
Bit 19 - CBURSTRW
pub fn asyncwait(&self) -> ASYNCWAIT_R[src]
Bit 15 - ASYNCWAIT
pub fn extmod(&self) -> EXTMOD_R[src]
Bit 14 - EXTMOD
pub fn waiten(&self) -> WAITEN_R[src]
Bit 13 - WAITEN
pub fn wren(&self) -> WREN_R[src]
Bit 12 - WREN
pub fn waitcfg(&self) -> WAITCFG_R[src]
Bit 11 - WAITCFG
pub fn wrapmod(&self) -> WRAPMOD_R[src]
Bit 10 - WRAPMOD
pub fn waitpol(&self) -> WAITPOL_R[src]
Bit 9 - WAITPOL
pub fn bursten(&self) -> BURSTEN_R[src]
Bit 8 - BURSTEN
pub fn faccen(&self) -> FACCEN_R[src]
Bit 6 - FACCEN
pub fn mwid(&self) -> MWID_R[src]
Bits 4:5 - MWID
pub fn mtyp(&self) -> MTYP_R[src]
Bits 2:3 - MTYP
pub fn muxen(&self) -> MUXEN_R[src]
Bit 1 - MUXEN
pub fn mbken(&self) -> MBKEN_R[src]
Bit 0 - MBKEN
pub fn cpsize(&self) -> CPSIZE_R[src]
Bits 16:18 - CRAM page size
impl R<u8, ACCMOD_A>[src]
pub fn variant(&self) -> ACCMOD_A[src]
Get enumerated values variant
pub fn is_a(&self) -> bool[src]
Checks if the value of the field is A
pub fn is_b(&self) -> bool[src]
Checks if the value of the field is B
pub fn is_c(&self) -> bool[src]
Checks if the value of the field is C
pub fn is_d(&self) -> bool[src]
Checks if the value of the field is D
impl R<u32, Reg<u32, _BTR>>[src]
pub fn accmod(&self) -> ACCMOD_R[src]
Bits 28:29 - ACCMOD
pub fn datlat(&self) -> DATLAT_R[src]
Bits 24:27 - DATLAT
pub fn clkdiv(&self) -> CLKDIV_R[src]
Bits 20:23 - CLKDIV
pub fn busturn(&self) -> BUSTURN_R[src]
Bits 16:19 - BUSTURN
pub fn datast(&self) -> DATAST_R[src]
Bits 8:15 - DATAST
pub fn addhld(&self) -> ADDHLD_R[src]
Bits 4:7 - ADDHLD
pub fn addset(&self) -> ADDSET_R[src]
Bits 0:3 - ADDSET
impl R<bool, CBURSTRW_A>[src]
pub fn variant(&self) -> CBURSTRW_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, ASYNCWAIT_A>[src]
pub fn variant(&self) -> ASYNCWAIT_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, EXTMOD_A>[src]
pub fn variant(&self) -> EXTMOD_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITEN_A>[src]
pub fn variant(&self) -> WAITEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WREN_A>[src]
pub fn variant(&self) -> WREN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITCFG_A>[src]
pub fn variant(&self) -> WAITCFG_A[src]
Get enumerated values variant
pub fn is_before_wait_state(&self) -> bool[src]
Checks if the value of the field is BEFOREWAITSTATE
pub fn is_during_wait_state(&self) -> bool[src]
Checks if the value of the field is DURINGWAITSTATE
impl R<bool, WAITPOL_A>[src]
pub fn variant(&self) -> WAITPOL_A[src]
Get enumerated values variant
pub fn is_active_low(&self) -> bool[src]
Checks if the value of the field is ACTIVELOW
pub fn is_active_high(&self) -> bool[src]
Checks if the value of the field is ACTIVEHIGH
impl R<bool, BURSTEN_A>[src]
pub fn variant(&self) -> BURSTEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, FACCEN_A>[src]
pub fn variant(&self) -> FACCEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, MWID_A>[src]
pub fn variant(&self) -> Variant<u8, MWID_A>[src]
Get enumerated values variant
pub fn is_bits8(&self) -> bool[src]
Checks if the value of the field is BITS8
pub fn is_bits16(&self) -> bool[src]
Checks if the value of the field is BITS16
pub fn is_bits32(&self) -> bool[src]
Checks if the value of the field is BITS32
impl R<u8, MTYP_A>[src]
pub fn variant(&self) -> Variant<u8, MTYP_A>[src]
Get enumerated values variant
pub fn is_sram(&self) -> bool[src]
Checks if the value of the field is SRAM
pub fn is_psram(&self) -> bool[src]
Checks if the value of the field is PSRAM
pub fn is_flash(&self) -> bool[src]
Checks if the value of the field is FLASH
impl R<bool, MUXEN_A>[src]
pub fn variant(&self) -> MUXEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, MBKEN_A>[src]
pub fn variant(&self) -> MBKEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CPSIZE_A>[src]
pub fn variant(&self) -> Variant<u8, CPSIZE_A>[src]
Get enumerated values variant
pub fn is_no_burst_split(&self) -> bool[src]
Checks if the value of the field is NOBURSTSPLIT
pub fn is_bytes128(&self) -> bool[src]
Checks if the value of the field is BYTES128
pub fn is_bytes256(&self) -> bool[src]
Checks if the value of the field is BYTES256
pub fn is_bytes512(&self) -> bool[src]
Checks if the value of the field is BYTES512
pub fn is_bytes1024(&self) -> bool[src]
Checks if the value of the field is BYTES1024
impl R<u32, Reg<u32, _BCR>>[src]
pub fn cburstrw(&self) -> CBURSTRW_R[src]
Bit 19 - CBURSTRW
pub fn asyncwait(&self) -> ASYNCWAIT_R[src]
Bit 15 - ASYNCWAIT
pub fn extmod(&self) -> EXTMOD_R[src]
Bit 14 - EXTMOD
pub fn waiten(&self) -> WAITEN_R[src]
Bit 13 - WAITEN
pub fn wren(&self) -> WREN_R[src]
Bit 12 - WREN
pub fn waitcfg(&self) -> WAITCFG_R[src]
Bit 11 - WAITCFG
pub fn wrapmod(&self) -> WRAPMOD_R[src]
Bit 10 - WRAPMOD
pub fn waitpol(&self) -> WAITPOL_R[src]
Bit 9 - WAITPOL
pub fn bursten(&self) -> BURSTEN_R[src]
Bit 8 - BURSTEN
pub fn faccen(&self) -> FACCEN_R[src]
Bit 6 - FACCEN
pub fn mwid(&self) -> MWID_R[src]
Bits 4:5 - MWID
pub fn mtyp(&self) -> MTYP_R[src]
Bits 2:3 - MTYP
pub fn muxen(&self) -> MUXEN_R[src]
Bit 1 - MUXEN
pub fn mbken(&self) -> MBKEN_R[src]
Bit 0 - MBKEN
pub fn cpsize(&self) -> CPSIZE_R[src]
Bits 16:18 - CRAM page size
impl R<u8, ACCMOD_A>[src]
pub fn variant(&self) -> ACCMOD_A[src]
Get enumerated values variant
pub fn is_a(&self) -> bool[src]
Checks if the value of the field is A
pub fn is_b(&self) -> bool[src]
Checks if the value of the field is B
pub fn is_c(&self) -> bool[src]
Checks if the value of the field is C
pub fn is_d(&self) -> bool[src]
Checks if the value of the field is D
impl R<u32, Reg<u32, _BWTR>>[src]
pub fn accmod(&self) -> ACCMOD_R[src]
Bits 28:29 - ACCMOD
pub fn datlat(&self) -> DATLAT_R[src]
Bits 24:27 - DATLAT
pub fn clkdiv(&self) -> CLKDIV_R[src]
Bits 20:23 - CLKDIV
pub fn datast(&self) -> DATAST_R[src]
Bits 8:15 - DATAST
pub fn addhld(&self) -> ADDHLD_R[src]
Bits 4:7 - ADDHLD
pub fn addset(&self) -> ADDSET_R[src]
Bits 0:3 - ADDSET
pub fn busturn(&self) -> BUSTURN_R[src]
Bits 16:19 - Bus turnaround phase duration
impl R<u8, MODER15_A>[src]
pub fn variant(&self) -> MODER15_A[src]
Get enumerated values variant
pub fn is_input(&self) -> bool[src]
Checks if the value of the field is INPUT
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
pub fn is_alternate(&self) -> bool[src]
Checks if the value of the field is ALTERNATE
pub fn is_analog(&self) -> bool[src]
Checks if the value of the field is ANALOG
impl R<u32, Reg<u32, _MODER>>[src]
pub fn moder15(&self) -> MODER15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&self) -> MODER14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&self) -> MODER13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&self) -> MODER12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&self) -> MODER11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&self) -> MODER10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&self) -> MODER9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&self) -> MODER8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&self) -> MODER7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&self) -> MODER6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&self) -> MODER5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&self) -> MODER4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&self) -> MODER3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&self) -> MODER2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&self) -> MODER1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&self) -> MODER0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, OT15_A>[src]
pub fn variant(&self) -> OT15_A[src]
Get enumerated values variant
pub fn is_push_pull(&self) -> bool[src]
Checks if the value of the field is PUSHPULL
pub fn is_open_drain(&self) -> bool[src]
Checks if the value of the field is OPENDRAIN
impl R<u32, Reg<u32, _OTYPER>>[src]
pub fn ot15(&self) -> OT15_R[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&self) -> OT14_R[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&self) -> OT13_R[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&self) -> OT12_R[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&self) -> OT11_R[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&self) -> OT10_R[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&self) -> OT9_R[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&self) -> OT8_R[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&self) -> OT7_R[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&self) -> OT6_R[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&self) -> OT5_R[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&self) -> OT4_R[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&self) -> OT3_R[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&self) -> OT2_R[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&self) -> OT1_R[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&self) -> OT0_R[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl R<u8, OSPEEDR15_A>[src]
pub fn variant(&self) -> OSPEEDR15_A[src]
Get enumerated values variant
pub fn is_low_speed(&self) -> bool[src]
Checks if the value of the field is LOWSPEED
pub fn is_medium_speed(&self) -> bool[src]
Checks if the value of the field is MEDIUMSPEED
pub fn is_high_speed(&self) -> bool[src]
Checks if the value of the field is HIGHSPEED
pub fn is_very_high_speed(&self) -> bool[src]
Checks if the value of the field is VERYHIGHSPEED
impl R<u32, Reg<u32, _OSPEEDR>>[src]
pub fn ospeedr15(&self) -> OSPEEDR15_R[src]
Bits 30:31 - OSPEEDR15
pub fn ospeedr14(&self) -> OSPEEDR14_R[src]
Bits 28:29 - OSPEEDR14
pub fn ospeedr13(&self) -> OSPEEDR13_R[src]
Bits 26:27 - OSPEEDR13
pub fn ospeedr12(&self) -> OSPEEDR12_R[src]
Bits 24:25 - OSPEEDR12
pub fn ospeedr11(&self) -> OSPEEDR11_R[src]
Bits 22:23 - OSPEEDR11
pub fn ospeedr10(&self) -> OSPEEDR10_R[src]
Bits 20:21 - OSPEEDR10
pub fn ospeedr9(&self) -> OSPEEDR9_R[src]
Bits 18:19 - OSPEEDR9
pub fn ospeedr8(&self) -> OSPEEDR8_R[src]
Bits 16:17 - OSPEEDR8
pub fn ospeedr7(&self) -> OSPEEDR7_R[src]
Bits 14:15 - OSPEEDR7
pub fn ospeedr6(&self) -> OSPEEDR6_R[src]
Bits 12:13 - OSPEEDR6
pub fn ospeedr5(&self) -> OSPEEDR5_R[src]
Bits 10:11 - OSPEEDR5
pub fn ospeedr4(&self) -> OSPEEDR4_R[src]
Bits 8:9 - OSPEEDR4
pub fn ospeedr3(&self) -> OSPEEDR3_R[src]
Bits 6:7 - OSPEEDR3
pub fn ospeedr2(&self) -> OSPEEDR2_R[src]
Bits 4:5 - OSPEEDR2
pub fn ospeedr1(&self) -> OSPEEDR1_R[src]
Bits 2:3 - OSPEEDR1
pub fn ospeedr0(&self) -> OSPEEDR0_R[src]
Bits 0:1 - OSPEEDR0
impl R<u8, PUPDR15_A>[src]
pub fn variant(&self) -> Variant<u8, PUPDR15_A>[src]
Get enumerated values variant
pub fn is_floating(&self) -> bool[src]
Checks if the value of the field is FLOATING
pub fn is_pull_up(&self) -> bool[src]
Checks if the value of the field is PULLUP
pub fn is_pull_down(&self) -> bool[src]
Checks if the value of the field is PULLDOWN
impl R<u32, Reg<u32, _PUPDR>>[src]
pub fn pupdr15(&self) -> PUPDR15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&self) -> PUPDR14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&self) -> PUPDR13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&self) -> PUPDR12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&self) -> PUPDR11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&self) -> PUPDR10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&self) -> PUPDR9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&self) -> PUPDR8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&self) -> PUPDR7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&self) -> PUPDR6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&self) -> PUPDR5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&self) -> PUPDR4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&self) -> PUPDR3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&self) -> PUPDR2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&self) -> PUPDR1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&self) -> PUPDR0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, IDR15_A>[src]
pub fn variant(&self) -> IDR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _IDR>>[src]
pub fn idr15(&self) -> IDR15_R[src]
Bit 15 - Port input data (y = 0..15)
pub fn idr14(&self) -> IDR14_R[src]
Bit 14 - Port input data (y = 0..15)
pub fn idr13(&self) -> IDR13_R[src]
Bit 13 - Port input data (y = 0..15)
pub fn idr12(&self) -> IDR12_R[src]
Bit 12 - Port input data (y = 0..15)
pub fn idr11(&self) -> IDR11_R[src]
Bit 11 - Port input data (y = 0..15)
pub fn idr10(&self) -> IDR10_R[src]
Bit 10 - Port input data (y = 0..15)
pub fn idr9(&self) -> IDR9_R[src]
Bit 9 - Port input data (y = 0..15)
pub fn idr8(&self) -> IDR8_R[src]
Bit 8 - Port input data (y = 0..15)
pub fn idr7(&self) -> IDR7_R[src]
Bit 7 - Port input data (y = 0..15)
pub fn idr6(&self) -> IDR6_R[src]
Bit 6 - Port input data (y = 0..15)
pub fn idr5(&self) -> IDR5_R[src]
Bit 5 - Port input data (y = 0..15)
pub fn idr4(&self) -> IDR4_R[src]
Bit 4 - Port input data (y = 0..15)
pub fn idr3(&self) -> IDR3_R[src]
Bit 3 - Port input data (y = 0..15)
pub fn idr2(&self) -> IDR2_R[src]
Bit 2 - Port input data (y = 0..15)
pub fn idr1(&self) -> IDR1_R[src]
Bit 1 - Port input data (y = 0..15)
pub fn idr0(&self) -> IDR0_R[src]
Bit 0 - Port input data (y = 0..15)
impl R<bool, ODR15_A>[src]
pub fn variant(&self) -> ODR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _ODR>>[src]
pub fn odr15(&self) -> ODR15_R[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&self) -> ODR14_R[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&self) -> ODR13_R[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&self) -> ODR12_R[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&self) -> ODR11_R[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&self) -> ODR10_R[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&self) -> ODR9_R[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&self) -> ODR8_R[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&self) -> ODR7_R[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&self) -> ODR6_R[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&self) -> ODR5_R[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&self) -> ODR4_R[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&self) -> ODR3_R[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&self) -> ODR2_R[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&self) -> ODR1_R[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&self) -> ODR0_R[src]
Bit 0 - Port output data (y = 0..15)
impl R<bool, LCKK_A>[src]
pub fn variant(&self) -> LCKK_A[src]
Get enumerated values variant
pub fn is_not_active(&self) -> bool[src]
Checks if the value of the field is NOTACTIVE
pub fn is_active(&self) -> bool[src]
Checks if the value of the field is ACTIVE
impl R<bool, LCK15_A>[src]
pub fn variant(&self) -> LCK15_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, LCK9_A>[src]
pub fn variant(&self) -> LCK9_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<u32, Reg<u32, _LCKR>>[src]
pub fn lckk(&self) -> LCKK_R[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&self) -> LCK15_R[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&self) -> LCK14_R[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&self) -> LCK13_R[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&self) -> LCK12_R[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&self) -> LCK11_R[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&self) -> LCK10_R[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&self) -> LCK9_R[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&self) -> LCK8_R[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&self) -> LCK7_R[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&self) -> LCK6_R[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&self) -> LCK5_R[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&self) -> LCK4_R[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&self) -> LCK3_R[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&self) -> LCK2_R[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&self) -> LCK1_R[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&self) -> LCK0_R[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl R<u8, AFRL7_A>[src]
pub fn variant(&self) -> AFRL7_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRL>>[src]
pub fn afrl7(&self) -> AFRL7_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&self) -> AFRL6_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&self) -> AFRL5_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&self) -> AFRL4_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&self) -> AFRL3_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&self) -> AFRL2_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&self) -> AFRL1_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&self) -> AFRL0_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl R<u8, AFRH15_A>[src]
pub fn variant(&self) -> AFRH15_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRH>>[src]
pub fn afrh15(&self) -> AFRH15_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&self) -> AFRH14_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&self) -> AFRH13_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&self) -> AFRH12_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&self) -> AFRH11_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&self) -> AFRH10_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&self) -> AFRH9_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&self) -> AFRH8_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl R<u8, MODER15_A>[src]
pub fn variant(&self) -> MODER15_A[src]
Get enumerated values variant
pub fn is_input(&self) -> bool[src]
Checks if the value of the field is INPUT
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
pub fn is_alternate(&self) -> bool[src]
Checks if the value of the field is ALTERNATE
pub fn is_analog(&self) -> bool[src]
Checks if the value of the field is ANALOG
impl R<u32, Reg<u32, _MODER>>[src]
pub fn moder15(&self) -> MODER15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&self) -> MODER14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&self) -> MODER13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&self) -> MODER12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&self) -> MODER11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&self) -> MODER10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&self) -> MODER9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&self) -> MODER8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&self) -> MODER7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&self) -> MODER6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&self) -> MODER5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&self) -> MODER4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&self) -> MODER3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&self) -> MODER2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&self) -> MODER1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&self) -> MODER0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, OT15_A>[src]
pub fn variant(&self) -> OT15_A[src]
Get enumerated values variant
pub fn is_push_pull(&self) -> bool[src]
Checks if the value of the field is PUSHPULL
pub fn is_open_drain(&self) -> bool[src]
Checks if the value of the field is OPENDRAIN
impl R<u32, Reg<u32, _OTYPER>>[src]
pub fn ot15(&self) -> OT15_R[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&self) -> OT14_R[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&self) -> OT13_R[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&self) -> OT12_R[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&self) -> OT11_R[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&self) -> OT10_R[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&self) -> OT9_R[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&self) -> OT8_R[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&self) -> OT7_R[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&self) -> OT6_R[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&self) -> OT5_R[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&self) -> OT4_R[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&self) -> OT3_R[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&self) -> OT2_R[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&self) -> OT1_R[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&self) -> OT0_R[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl R<u8, OSPEEDR15_A>[src]
pub fn variant(&self) -> OSPEEDR15_A[src]
Get enumerated values variant
pub fn is_low_speed(&self) -> bool[src]
Checks if the value of the field is LOWSPEED
pub fn is_medium_speed(&self) -> bool[src]
Checks if the value of the field is MEDIUMSPEED
pub fn is_high_speed(&self) -> bool[src]
Checks if the value of the field is HIGHSPEED
pub fn is_very_high_speed(&self) -> bool[src]
Checks if the value of the field is VERYHIGHSPEED
impl R<u32, Reg<u32, _OSPEEDR>>[src]
pub fn ospeedr15(&self) -> OSPEEDR15_R[src]
Bits 30:31 - OSPEEDR15
pub fn ospeedr14(&self) -> OSPEEDR14_R[src]
Bits 28:29 - OSPEEDR14
pub fn ospeedr13(&self) -> OSPEEDR13_R[src]
Bits 26:27 - OSPEEDR13
pub fn ospeedr12(&self) -> OSPEEDR12_R[src]
Bits 24:25 - OSPEEDR12
pub fn ospeedr11(&self) -> OSPEEDR11_R[src]
Bits 22:23 - OSPEEDR11
pub fn ospeedr10(&self) -> OSPEEDR10_R[src]
Bits 20:21 - OSPEEDR10
pub fn ospeedr9(&self) -> OSPEEDR9_R[src]
Bits 18:19 - OSPEEDR9
pub fn ospeedr8(&self) -> OSPEEDR8_R[src]
Bits 16:17 - OSPEEDR8
pub fn ospeedr7(&self) -> OSPEEDR7_R[src]
Bits 14:15 - OSPEEDR7
pub fn ospeedr6(&self) -> OSPEEDR6_R[src]
Bits 12:13 - OSPEEDR6
pub fn ospeedr5(&self) -> OSPEEDR5_R[src]
Bits 10:11 - OSPEEDR5
pub fn ospeedr4(&self) -> OSPEEDR4_R[src]
Bits 8:9 - OSPEEDR4
pub fn ospeedr3(&self) -> OSPEEDR3_R[src]
Bits 6:7 - OSPEEDR3
pub fn ospeedr2(&self) -> OSPEEDR2_R[src]
Bits 4:5 - OSPEEDR2
pub fn ospeedr1(&self) -> OSPEEDR1_R[src]
Bits 2:3 - OSPEEDR1
pub fn ospeedr0(&self) -> OSPEEDR0_R[src]
Bits 0:1 - OSPEEDR0
impl R<u8, PUPDR15_A>[src]
pub fn variant(&self) -> Variant<u8, PUPDR15_A>[src]
Get enumerated values variant
pub fn is_floating(&self) -> bool[src]
Checks if the value of the field is FLOATING
pub fn is_pull_up(&self) -> bool[src]
Checks if the value of the field is PULLUP
pub fn is_pull_down(&self) -> bool[src]
Checks if the value of the field is PULLDOWN
impl R<u32, Reg<u32, _PUPDR>>[src]
pub fn pupdr15(&self) -> PUPDR15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&self) -> PUPDR14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&self) -> PUPDR13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&self) -> PUPDR12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&self) -> PUPDR11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&self) -> PUPDR10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&self) -> PUPDR9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&self) -> PUPDR8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&self) -> PUPDR7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&self) -> PUPDR6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&self) -> PUPDR5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&self) -> PUPDR4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&self) -> PUPDR3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&self) -> PUPDR2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&self) -> PUPDR1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&self) -> PUPDR0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, IDR15_A>[src]
pub fn variant(&self) -> IDR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _IDR>>[src]
pub fn idr15(&self) -> IDR15_R[src]
Bit 15 - Port input data (y = 0..15)
pub fn idr14(&self) -> IDR14_R[src]
Bit 14 - Port input data (y = 0..15)
pub fn idr13(&self) -> IDR13_R[src]
Bit 13 - Port input data (y = 0..15)
pub fn idr12(&self) -> IDR12_R[src]
Bit 12 - Port input data (y = 0..15)
pub fn idr11(&self) -> IDR11_R[src]
Bit 11 - Port input data (y = 0..15)
pub fn idr10(&self) -> IDR10_R[src]
Bit 10 - Port input data (y = 0..15)
pub fn idr9(&self) -> IDR9_R[src]
Bit 9 - Port input data (y = 0..15)
pub fn idr8(&self) -> IDR8_R[src]
Bit 8 - Port input data (y = 0..15)
pub fn idr7(&self) -> IDR7_R[src]
Bit 7 - Port input data (y = 0..15)
pub fn idr6(&self) -> IDR6_R[src]
Bit 6 - Port input data (y = 0..15)
pub fn idr5(&self) -> IDR5_R[src]
Bit 5 - Port input data (y = 0..15)
pub fn idr4(&self) -> IDR4_R[src]
Bit 4 - Port input data (y = 0..15)
pub fn idr3(&self) -> IDR3_R[src]
Bit 3 - Port input data (y = 0..15)
pub fn idr2(&self) -> IDR2_R[src]
Bit 2 - Port input data (y = 0..15)
pub fn idr1(&self) -> IDR1_R[src]
Bit 1 - Port input data (y = 0..15)
pub fn idr0(&self) -> IDR0_R[src]
Bit 0 - Port input data (y = 0..15)
impl R<bool, ODR15_A>[src]
pub fn variant(&self) -> ODR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _ODR>>[src]
pub fn odr15(&self) -> ODR15_R[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&self) -> ODR14_R[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&self) -> ODR13_R[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&self) -> ODR12_R[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&self) -> ODR11_R[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&self) -> ODR10_R[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&self) -> ODR9_R[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&self) -> ODR8_R[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&self) -> ODR7_R[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&self) -> ODR6_R[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&self) -> ODR5_R[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&self) -> ODR4_R[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&self) -> ODR3_R[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&self) -> ODR2_R[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&self) -> ODR1_R[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&self) -> ODR0_R[src]
Bit 0 - Port output data (y = 0..15)
impl R<bool, LCKK_A>[src]
pub fn variant(&self) -> LCKK_A[src]
Get enumerated values variant
pub fn is_not_active(&self) -> bool[src]
Checks if the value of the field is NOTACTIVE
pub fn is_active(&self) -> bool[src]
Checks if the value of the field is ACTIVE
impl R<bool, LCK15_A>[src]
pub fn variant(&self) -> LCK15_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, LCK9_A>[src]
pub fn variant(&self) -> LCK9_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<u32, Reg<u32, _LCKR>>[src]
pub fn lckk(&self) -> LCKK_R[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&self) -> LCK15_R[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&self) -> LCK14_R[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&self) -> LCK13_R[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&self) -> LCK12_R[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&self) -> LCK11_R[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&self) -> LCK10_R[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&self) -> LCK9_R[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&self) -> LCK8_R[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&self) -> LCK7_R[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&self) -> LCK6_R[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&self) -> LCK5_R[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&self) -> LCK4_R[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&self) -> LCK3_R[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&self) -> LCK2_R[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&self) -> LCK1_R[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&self) -> LCK0_R[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl R<u8, AFRL7_A>[src]
pub fn variant(&self) -> AFRL7_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRL>>[src]
pub fn afrl7(&self) -> AFRL7_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&self) -> AFRL6_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&self) -> AFRL5_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&self) -> AFRL4_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&self) -> AFRL3_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&self) -> AFRL2_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&self) -> AFRL1_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&self) -> AFRL0_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl R<u8, AFRH15_A>[src]
pub fn variant(&self) -> AFRH15_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRH>>[src]
pub fn afrh15(&self) -> AFRH15_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&self) -> AFRH14_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&self) -> AFRH13_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&self) -> AFRH12_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&self) -> AFRH11_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&self) -> AFRH10_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&self) -> AFRH9_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&self) -> AFRH8_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl R<u8, MODER15_A>[src]
pub fn variant(&self) -> MODER15_A[src]
Get enumerated values variant
pub fn is_input(&self) -> bool[src]
Checks if the value of the field is INPUT
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
pub fn is_alternate(&self) -> bool[src]
Checks if the value of the field is ALTERNATE
pub fn is_analog(&self) -> bool[src]
Checks if the value of the field is ANALOG
impl R<u32, Reg<u32, _MODER>>[src]
pub fn moder15(&self) -> MODER15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&self) -> MODER14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&self) -> MODER13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&self) -> MODER12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&self) -> MODER11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&self) -> MODER10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&self) -> MODER9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&self) -> MODER8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&self) -> MODER7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&self) -> MODER6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&self) -> MODER5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&self) -> MODER4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&self) -> MODER3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&self) -> MODER2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&self) -> MODER1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&self) -> MODER0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, OT15_A>[src]
pub fn variant(&self) -> OT15_A[src]
Get enumerated values variant
pub fn is_push_pull(&self) -> bool[src]
Checks if the value of the field is PUSHPULL
pub fn is_open_drain(&self) -> bool[src]
Checks if the value of the field is OPENDRAIN
impl R<u32, Reg<u32, _OTYPER>>[src]
pub fn ot15(&self) -> OT15_R[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&self) -> OT14_R[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&self) -> OT13_R[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&self) -> OT12_R[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&self) -> OT11_R[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&self) -> OT10_R[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&self) -> OT9_R[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&self) -> OT8_R[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&self) -> OT7_R[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&self) -> OT6_R[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&self) -> OT5_R[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&self) -> OT4_R[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&self) -> OT3_R[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&self) -> OT2_R[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&self) -> OT1_R[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&self) -> OT0_R[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl R<u8, OSPEEDR15_A>[src]
pub fn variant(&self) -> OSPEEDR15_A[src]
Get enumerated values variant
pub fn is_low_speed(&self) -> bool[src]
Checks if the value of the field is LOWSPEED
pub fn is_medium_speed(&self) -> bool[src]
Checks if the value of the field is MEDIUMSPEED
pub fn is_high_speed(&self) -> bool[src]
Checks if the value of the field is HIGHSPEED
pub fn is_very_high_speed(&self) -> bool[src]
Checks if the value of the field is VERYHIGHSPEED
impl R<u32, Reg<u32, _OSPEEDR>>[src]
pub fn ospeedr15(&self) -> OSPEEDR15_R[src]
Bits 30:31 - OSPEEDR15
pub fn ospeedr14(&self) -> OSPEEDR14_R[src]
Bits 28:29 - OSPEEDR14
pub fn ospeedr13(&self) -> OSPEEDR13_R[src]
Bits 26:27 - OSPEEDR13
pub fn ospeedr12(&self) -> OSPEEDR12_R[src]
Bits 24:25 - OSPEEDR12
pub fn ospeedr11(&self) -> OSPEEDR11_R[src]
Bits 22:23 - OSPEEDR11
pub fn ospeedr10(&self) -> OSPEEDR10_R[src]
Bits 20:21 - OSPEEDR10
pub fn ospeedr9(&self) -> OSPEEDR9_R[src]
Bits 18:19 - OSPEEDR9
pub fn ospeedr8(&self) -> OSPEEDR8_R[src]
Bits 16:17 - OSPEEDR8
pub fn ospeedr7(&self) -> OSPEEDR7_R[src]
Bits 14:15 - OSPEEDR7
pub fn ospeedr6(&self) -> OSPEEDR6_R[src]
Bits 12:13 - OSPEEDR6
pub fn ospeedr5(&self) -> OSPEEDR5_R[src]
Bits 10:11 - OSPEEDR5
pub fn ospeedr4(&self) -> OSPEEDR4_R[src]
Bits 8:9 - OSPEEDR4
pub fn ospeedr3(&self) -> OSPEEDR3_R[src]
Bits 6:7 - OSPEEDR3
pub fn ospeedr2(&self) -> OSPEEDR2_R[src]
Bits 4:5 - OSPEEDR2
pub fn ospeedr1(&self) -> OSPEEDR1_R[src]
Bits 2:3 - OSPEEDR1
pub fn ospeedr0(&self) -> OSPEEDR0_R[src]
Bits 0:1 - OSPEEDR0
impl R<u8, PUPDR15_A>[src]
pub fn variant(&self) -> Variant<u8, PUPDR15_A>[src]
Get enumerated values variant
pub fn is_floating(&self) -> bool[src]
Checks if the value of the field is FLOATING
pub fn is_pull_up(&self) -> bool[src]
Checks if the value of the field is PULLUP
pub fn is_pull_down(&self) -> bool[src]
Checks if the value of the field is PULLDOWN
impl R<u32, Reg<u32, _PUPDR>>[src]
pub fn pupdr15(&self) -> PUPDR15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&self) -> PUPDR14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&self) -> PUPDR13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&self) -> PUPDR12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&self) -> PUPDR11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&self) -> PUPDR10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&self) -> PUPDR9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&self) -> PUPDR8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&self) -> PUPDR7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&self) -> PUPDR6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&self) -> PUPDR5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&self) -> PUPDR4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&self) -> PUPDR3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&self) -> PUPDR2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&self) -> PUPDR1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&self) -> PUPDR0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, IDR15_A>[src]
pub fn variant(&self) -> IDR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _IDR>>[src]
pub fn idr15(&self) -> IDR15_R[src]
Bit 15 - Port input data (y = 0..15)
pub fn idr14(&self) -> IDR14_R[src]
Bit 14 - Port input data (y = 0..15)
pub fn idr13(&self) -> IDR13_R[src]
Bit 13 - Port input data (y = 0..15)
pub fn idr12(&self) -> IDR12_R[src]
Bit 12 - Port input data (y = 0..15)
pub fn idr11(&self) -> IDR11_R[src]
Bit 11 - Port input data (y = 0..15)
pub fn idr10(&self) -> IDR10_R[src]
Bit 10 - Port input data (y = 0..15)
pub fn idr9(&self) -> IDR9_R[src]
Bit 9 - Port input data (y = 0..15)
pub fn idr8(&self) -> IDR8_R[src]
Bit 8 - Port input data (y = 0..15)
pub fn idr7(&self) -> IDR7_R[src]
Bit 7 - Port input data (y = 0..15)
pub fn idr6(&self) -> IDR6_R[src]
Bit 6 - Port input data (y = 0..15)
pub fn idr5(&self) -> IDR5_R[src]
Bit 5 - Port input data (y = 0..15)
pub fn idr4(&self) -> IDR4_R[src]
Bit 4 - Port input data (y = 0..15)
pub fn idr3(&self) -> IDR3_R[src]
Bit 3 - Port input data (y = 0..15)
pub fn idr2(&self) -> IDR2_R[src]
Bit 2 - Port input data (y = 0..15)
pub fn idr1(&self) -> IDR1_R[src]
Bit 1 - Port input data (y = 0..15)
pub fn idr0(&self) -> IDR0_R[src]
Bit 0 - Port input data (y = 0..15)
impl R<bool, ODR15_A>[src]
pub fn variant(&self) -> ODR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _ODR>>[src]
pub fn odr15(&self) -> ODR15_R[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&self) -> ODR14_R[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&self) -> ODR13_R[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&self) -> ODR12_R[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&self) -> ODR11_R[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&self) -> ODR10_R[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&self) -> ODR9_R[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&self) -> ODR8_R[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&self) -> ODR7_R[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&self) -> ODR6_R[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&self) -> ODR5_R[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&self) -> ODR4_R[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&self) -> ODR3_R[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&self) -> ODR2_R[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&self) -> ODR1_R[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&self) -> ODR0_R[src]
Bit 0 - Port output data (y = 0..15)
impl R<bool, LCKK_A>[src]
pub fn variant(&self) -> LCKK_A[src]
Get enumerated values variant
pub fn is_not_active(&self) -> bool[src]
Checks if the value of the field is NOTACTIVE
pub fn is_active(&self) -> bool[src]
Checks if the value of the field is ACTIVE
impl R<bool, LCK15_A>[src]
pub fn variant(&self) -> LCK15_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, LCK9_A>[src]
pub fn variant(&self) -> LCK9_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<u32, Reg<u32, _LCKR>>[src]
pub fn lckk(&self) -> LCKK_R[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&self) -> LCK15_R[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&self) -> LCK14_R[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&self) -> LCK13_R[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&self) -> LCK12_R[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&self) -> LCK11_R[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&self) -> LCK10_R[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&self) -> LCK9_R[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&self) -> LCK8_R[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&self) -> LCK7_R[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&self) -> LCK6_R[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&self) -> LCK5_R[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&self) -> LCK4_R[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&self) -> LCK3_R[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&self) -> LCK2_R[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&self) -> LCK1_R[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&self) -> LCK0_R[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl R<u8, AFRL7_A>[src]
pub fn variant(&self) -> AFRL7_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRL>>[src]
pub fn afrl7(&self) -> AFRL7_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&self) -> AFRL6_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&self) -> AFRL5_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&self) -> AFRL4_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&self) -> AFRL3_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&self) -> AFRL2_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&self) -> AFRL1_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&self) -> AFRL0_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl R<u8, AFRH15_A>[src]
pub fn variant(&self) -> AFRH15_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRH>>[src]
pub fn afrh15(&self) -> AFRH15_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&self) -> AFRH14_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&self) -> AFRH13_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&self) -> AFRH12_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&self) -> AFRH11_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&self) -> AFRH10_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&self) -> AFRH9_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&self) -> AFRH8_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl R<bool, SWRST_A>[src]
pub fn variant(&self) -> SWRST_A[src]
Get enumerated values variant
pub fn is_not_reset(&self) -> bool[src]
Checks if the value of the field is NOTRESET
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<bool, ALERT_A>[src]
pub fn variant(&self) -> ALERT_A[src]
Get enumerated values variant
pub fn is_release(&self) -> bool[src]
Checks if the value of the field is RELEASE
pub fn is_drive(&self) -> bool[src]
Checks if the value of the field is DRIVE
impl R<bool, PEC_A>[src]
pub fn variant(&self) -> PEC_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, POS_A>[src]
pub fn variant(&self) -> POS_A[src]
Get enumerated values variant
pub fn is_current(&self) -> bool[src]
Checks if the value of the field is CURRENT
pub fn is_next(&self) -> bool[src]
Checks if the value of the field is NEXT
impl R<bool, ACK_A>[src]
pub fn variant(&self) -> ACK_A[src]
Get enumerated values variant
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_ack(&self) -> bool[src]
Checks if the value of the field is ACK
impl R<bool, STOP_A>[src]
pub fn variant(&self) -> STOP_A[src]
Get enumerated values variant
pub fn is_no_stop(&self) -> bool[src]
Checks if the value of the field is NOSTOP
pub fn is_stop(&self) -> bool[src]
Checks if the value of the field is STOP
impl R<bool, START_A>[src]
pub fn variant(&self) -> START_A[src]
Get enumerated values variant
pub fn is_no_start(&self) -> bool[src]
Checks if the value of the field is NOSTART
pub fn is_start(&self) -> bool[src]
Checks if the value of the field is START
impl R<bool, NOSTRETCH_A>[src]
pub fn variant(&self) -> NOSTRETCH_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, ENGC_A>[src]
pub fn variant(&self) -> ENGC_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ENPEC_A>[src]
pub fn variant(&self) -> ENPEC_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ENARP_A>[src]
pub fn variant(&self) -> ENARP_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, SMBTYPE_A>[src]
pub fn variant(&self) -> SMBTYPE_A[src]
Get enumerated values variant
pub fn is_device(&self) -> bool[src]
Checks if the value of the field is DEVICE
pub fn is_host(&self) -> bool[src]
Checks if the value of the field is HOST
impl R<bool, SMBUS_A>[src]
pub fn variant(&self) -> SMBUS_A[src]
Get enumerated values variant
pub fn is_i2c(&self) -> bool[src]
Checks if the value of the field is I2C
pub fn is_smbus(&self) -> bool[src]
Checks if the value of the field is SMBUS
impl R<bool, PE_A>[src]
pub fn variant(&self) -> PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn swrst(&self) -> SWRST_R[src]
Bit 15 - Software reset
pub fn alert(&self) -> ALERT_R[src]
Bit 13 - SMBus alert
pub fn pec(&self) -> PEC_R[src]
Bit 12 - Packet error checking
pub fn pos(&self) -> POS_R[src]
Bit 11 - Acknowledge/PEC Position (for data reception)
pub fn ack(&self) -> ACK_R[src]
Bit 10 - Acknowledge enable
pub fn stop(&self) -> STOP_R[src]
Bit 9 - Stop generation
pub fn start(&self) -> START_R[src]
Bit 8 - Start generation
pub fn nostretch(&self) -> NOSTRETCH_R[src]
Bit 7 - Clock stretching disable (Slave mode)
pub fn engc(&self) -> ENGC_R[src]
Bit 6 - General call enable
pub fn enpec(&self) -> ENPEC_R[src]
Bit 5 - PEC enable
pub fn enarp(&self) -> ENARP_R[src]
Bit 4 - ARP enable
pub fn smbtype(&self) -> SMBTYPE_R[src]
Bit 3 - SMBus type
pub fn smbus(&self) -> SMBUS_R[src]
Bit 1 - SMBus mode
pub fn pe(&self) -> PE_R[src]
Bit 0 - Peripheral enable
impl R<bool, LAST_A>[src]
pub fn variant(&self) -> LAST_A[src]
Get enumerated values variant
pub fn is_not_last(&self) -> bool[src]
Checks if the value of the field is NOTLAST
pub fn is_last(&self) -> bool[src]
Checks if the value of the field is LAST
impl R<bool, DMAEN_A>[src]
pub fn variant(&self) -> DMAEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ITBUFEN_A>[src]
pub fn variant(&self) -> ITBUFEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ITEVTEN_A>[src]
pub fn variant(&self) -> ITEVTEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ITERREN_A>[src]
pub fn variant(&self) -> ITERREN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR2>>[src]
pub fn last(&self) -> LAST_R[src]
Bit 12 - DMA last transfer
pub fn dmaen(&self) -> DMAEN_R[src]
Bit 11 - DMA requests enable
pub fn itbufen(&self) -> ITBUFEN_R[src]
Bit 10 - Buffer interrupt enable
pub fn itevten(&self) -> ITEVTEN_R[src]
Bit 9 - Event interrupt enable
pub fn iterren(&self) -> ITERREN_R[src]
Bit 8 - Error interrupt enable
pub fn freq(&self) -> FREQ_R[src]
Bits 0:5 - Peripheral clock frequency
impl R<bool, ADDMODE_A>[src]
pub fn variant(&self) -> ADDMODE_A[src]
Get enumerated values variant
pub fn is_add7(&self) -> bool[src]
Checks if the value of the field is ADD7
pub fn is_add10(&self) -> bool[src]
Checks if the value of the field is ADD10
impl R<u32, Reg<u32, _OAR1>>[src]
pub fn addmode(&self) -> ADDMODE_R[src]
Bit 15 - ADDMODE
pub fn add(&self) -> ADD_R[src]
Bits 0:9 - Interface address
impl R<bool, ENDUAL_A>[src]
pub fn variant(&self) -> ENDUAL_A[src]
Get enumerated values variant
pub fn is_single(&self) -> bool[src]
Checks if the value of the field is SINGLE
pub fn is_dual(&self) -> bool[src]
Checks if the value of the field is DUAL
impl R<u32, Reg<u32, _OAR2>>[src]
pub fn add2(&self) -> ADD2_R[src]
Bits 1:7 - Interface address
pub fn endual(&self) -> ENDUAL_R[src]
Bit 0 - Dual addressing mode enable
impl R<u32, Reg<u32, _DR>>[src]
impl R<bool, SMBALERT_A>[src]
pub fn variant(&self) -> SMBALERT_A[src]
Get enumerated values variant
pub fn is_no_alert(&self) -> bool[src]
Checks if the value of the field is NOALERT
pub fn is_alert(&self) -> bool[src]
Checks if the value of the field is ALERT
impl R<bool, TIMEOUT_A>[src]
pub fn variant(&self) -> TIMEOUT_A[src]
Get enumerated values variant
pub fn is_no_timeout(&self) -> bool[src]
Checks if the value of the field is NOTIMEOUT
pub fn is_timeout(&self) -> bool[src]
Checks if the value of the field is TIMEOUT
impl R<bool, PECERR_A>[src]
pub fn variant(&self) -> PECERR_A[src]
Get enumerated values variant
pub fn is_no_error(&self) -> bool[src]
Checks if the value of the field is NOERROR
pub fn is_error(&self) -> bool[src]
Checks if the value of the field is ERROR
impl R<bool, OVR_A>[src]
pub fn variant(&self) -> OVR_A[src]
Get enumerated values variant
pub fn is_no_overrun(&self) -> bool[src]
Checks if the value of the field is NOOVERRUN
pub fn is_overrun(&self) -> bool[src]
Checks if the value of the field is OVERRUN
impl R<bool, AF_A>[src]
pub fn variant(&self) -> AF_A[src]
Get enumerated values variant
pub fn is_no_failure(&self) -> bool[src]
Checks if the value of the field is NOFAILURE
pub fn is_failure(&self) -> bool[src]
Checks if the value of the field is FAILURE
impl R<bool, ARLO_A>[src]
pub fn variant(&self) -> ARLO_A[src]
Get enumerated values variant
pub fn is_no_lost(&self) -> bool[src]
Checks if the value of the field is NOLOST
pub fn is_lost(&self) -> bool[src]
Checks if the value of the field is LOST
impl R<bool, BERR_A>[src]
pub fn variant(&self) -> BERR_A[src]
Get enumerated values variant
pub fn is_no_error(&self) -> bool[src]
Checks if the value of the field is NOERROR
pub fn is_error(&self) -> bool[src]
Checks if the value of the field is ERROR
impl R<bool, TXE_A>[src]
pub fn variant(&self) -> TXE_A[src]
Get enumerated values variant
pub fn is_not_empty(&self) -> bool[src]
Checks if the value of the field is NOTEMPTY
pub fn is_empty(&self) -> bool[src]
Checks if the value of the field is EMPTY
impl R<bool, RXNE_A>[src]
pub fn variant(&self) -> RXNE_A[src]
Get enumerated values variant
pub fn is_empty(&self) -> bool[src]
Checks if the value of the field is EMPTY
pub fn is_not_empty(&self) -> bool[src]
Checks if the value of the field is NOTEMPTY
impl R<bool, STOPF_A>[src]
pub fn variant(&self) -> STOPF_A[src]
Get enumerated values variant
pub fn is_no_stop(&self) -> bool[src]
Checks if the value of the field is NOSTOP
pub fn is_stop(&self) -> bool[src]
Checks if the value of the field is STOP
impl R<bool, BTF_A>[src]
pub fn variant(&self) -> BTF_A[src]
Get enumerated values variant
pub fn is_not_finished(&self) -> bool[src]
Checks if the value of the field is NOTFINISHED
pub fn is_finished(&self) -> bool[src]
Checks if the value of the field is FINISHED
impl R<bool, ADDR_A>[src]
pub fn variant(&self) -> ADDR_A[src]
Get enumerated values variant
pub fn is_not_match(&self) -> bool[src]
Checks if the value of the field is NOTMATCH
pub fn is_match_(&self) -> bool[src]
Checks if the value of the field is MATCH
impl R<bool, SB_A>[src]
pub fn variant(&self) -> SB_A[src]
Get enumerated values variant
pub fn is_no_start(&self) -> bool[src]
Checks if the value of the field is NOSTART
pub fn is_start(&self) -> bool[src]
Checks if the value of the field is START
impl R<u32, Reg<u32, _SR1>>[src]
pub fn smbalert(&self) -> SMBALERT_R[src]
Bit 15 - SMBus alert
pub fn timeout(&self) -> TIMEOUT_R[src]
Bit 14 - Timeout or Tlow error
pub fn pecerr(&self) -> PECERR_R[src]
Bit 12 - PEC Error in reception
pub fn ovr(&self) -> OVR_R[src]
Bit 11 - Overrun/Underrun
pub fn af(&self) -> AF_R[src]
Bit 10 - Acknowledge failure
pub fn arlo(&self) -> ARLO_R[src]
Bit 9 - Arbitration lost (master mode)
pub fn berr(&self) -> BERR_R[src]
Bit 8 - Bus error
pub fn tx_e(&self) -> TXE_R[src]
Bit 7 - Data register empty (transmitters)
pub fn rx_ne(&self) -> RXNE_R[src]
Bit 6 - Data register not empty (receivers)
pub fn stopf(&self) -> STOPF_R[src]
Bit 4 - Stop detection (slave mode)
pub fn add10(&self) -> ADD10_R[src]
Bit 3 - 10-bit header sent (Master mode)
pub fn btf(&self) -> BTF_R[src]
Bit 2 - Byte transfer finished
pub fn addr(&self) -> ADDR_R[src]
Bit 1 - Address sent (master mode)/matched (slave mode)
pub fn sb(&self) -> SB_R[src]
Bit 0 - Start bit (Master mode)
impl R<u32, Reg<u32, _SR2>>[src]
pub fn pec(&self) -> PEC_R[src]
Bits 8:15 - acket error checking register
pub fn dualf(&self) -> DUALF_R[src]
Bit 7 - Dual flag (Slave mode)
pub fn smbhost(&self) -> SMBHOST_R[src]
Bit 6 - SMBus host header (Slave mode)
pub fn smbdefault(&self) -> SMBDEFAULT_R[src]
Bit 5 - SMBus device default address (Slave mode)
pub fn gencall(&self) -> GENCALL_R[src]
Bit 4 - General call address (Slave mode)
pub fn tra(&self) -> TRA_R[src]
Bit 2 - Transmitter/receiver
pub fn busy(&self) -> BUSY_R[src]
Bit 1 - Bus busy
pub fn msl(&self) -> MSL_R[src]
Bit 0 - Master/slave
impl R<bool, F_S_A>[src]
pub fn variant(&self) -> F_S_A[src]
Get enumerated values variant
pub fn is_standard(&self) -> bool[src]
Checks if the value of the field is STANDARD
pub fn is_fast(&self) -> bool[src]
Checks if the value of the field is FAST
impl R<bool, DUTY_A>[src]
pub fn variant(&self) -> DUTY_A[src]
Get enumerated values variant
pub fn is_duty2_1(&self) -> bool[src]
Checks if the value of the field is DUTY2_1
pub fn is_duty16_9(&self) -> bool[src]
Checks if the value of the field is DUTY16_9
impl R<u32, Reg<u32, _CCR>>[src]
pub fn f_s(&self) -> F_S_R[src]
Bit 15 - I2C master mode selection
pub fn duty(&self) -> DUTY_R[src]
Bit 14 - Fast mode duty cycle
pub fn ccr(&self) -> CCR_R[src]
Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)
impl R<u32, Reg<u32, _TRISE>>[src]
impl R<u8, PR_A>[src]
pub fn variant(&self) -> PR_A[src]
Get enumerated values variant
pub fn is_divide_by4(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY4
pub fn is_divide_by8(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY8
pub fn is_divide_by16(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY16
pub fn is_divide_by32(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY32
pub fn is_divide_by64(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY64
pub fn is_divide_by128(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY128
pub fn is_divide_by256(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY256
pub fn is_divide_by256bis(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY256BIS
impl R<u32, Reg<u32, _PR>>[src]
impl R<u32, Reg<u32, _RLR>>[src]
impl R<u32, Reg<u32, _SR>>[src]
pub fn rvu(&self) -> RVU_R[src]
Bit 1 - Watchdog counter reload value update
pub fn pvu(&self) -> PVU_R[src]
Bit 0 - Watchdog prescaler value update
impl R<u32, Reg<u32, _CR>>[src]
pub fn mux_seg(&self) -> MUX_SEG_R[src]
Bit 7 - Mux segment enable
pub fn bias(&self) -> BIAS_R[src]
Bits 5:6 - Bias selector
pub fn duty(&self) -> DUTY_R[src]
Bits 2:4 - Duty selection
pub fn vsel(&self) -> VSEL_R[src]
Bit 1 - Voltage source selection
pub fn lcden(&self) -> LCDEN_R[src]
Bit 0 - LCD controller enable
impl R<u32, Reg<u32, _FCR>>[src]
pub fn ps(&self) -> PS_R[src]
Bits 22:25 - PS 16-bit prescaler
pub fn div(&self) -> DIV_R[src]
Bits 18:21 - DIV clock divider
pub fn blink(&self) -> BLINK_R[src]
Bits 16:17 - Blink mode selection
pub fn blinkf(&self) -> BLINKF_R[src]
Bits 13:15 - Blink frequency selection
pub fn cc(&self) -> CC_R[src]
Bits 10:12 - Contrast control
pub fn dead(&self) -> DEAD_R[src]
Bits 7:9 - Dead time duration
pub fn pon(&self) -> PON_R[src]
Bits 4:6 - Pulse ON duration
pub fn uddie(&self) -> UDDIE_R[src]
Bit 3 - Update display done interrupt enable
pub fn sofie(&self) -> SOFIE_R[src]
Bit 1 - Start of frame interrupt enable
pub fn hd(&self) -> HD_R[src]
Bit 0 - High drive enable
impl R<u32, Reg<u32, _SR>>[src]
pub fn fcrsf(&self) -> FCRSF_R[src]
Bit 5 - LCD Frame Control Register Synchronization flag
pub fn rdy(&self) -> RDY_R[src]
Bit 4 - Ready flag
pub fn udd(&self) -> UDD_R[src]
Bit 3 - Update Display Done
pub fn udr(&self) -> UDR_R[src]
Bit 2 - Update display request
pub fn sof(&self) -> SOF_R[src]
Bit 1 - Start of frame flag
pub fn ens(&self) -> ENS_R[src]
Bit 0 - LCD enabled status
impl R<u32, Reg<u32, _RAM_COM0>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM1>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM2>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM3>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM4>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM5>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM6>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM7>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _CSR>>[src]
pub fn opa3calout(&self) -> OPA3CALOUT_R[src]
Bit 31 - OPAMP3 calibration output
pub fn opa2calout(&self) -> OPA2CALOUT_R[src]
Bit 30 - OPAMP2 calibration output
pub fn opa1calout(&self) -> OPA1CALOUT_R[src]
Bit 29 - OPAMP1 calibration output
pub fn aop_range(&self) -> AOP_RANGE_R[src]
Bit 28 - Power range selection
pub fn s7sel2(&self) -> S7SEL2_R[src]
Bit 27 - Switch 7 for OPAMP2 enable
pub fn anawsel3(&self) -> ANAWSEL3_R[src]
Bit 26 - Switch SanA enable for OPAMP3
pub fn anawsel2(&self) -> ANAWSEL2_R[src]
Bit 25 - Switch SanA enable for OPAMP2
pub fn anawsel1(&self) -> ANAWSEL1_R[src]
Bit 24 - Switch SanA enable for OPAMP1
pub fn opa3lpm(&self) -> OPA3LPM_R[src]
Bit 23 - OPAMP3 low power mode
pub fn opa3cal_h(&self) -> OPA3CAL_H_R[src]
Bit 22 - OPAMP3 offset calibration for N differential pair
pub fn opa3cal_l(&self) -> OPA3CAL_L_R[src]
Bit 21 - OPAMP3 offset Calibration for P differential pair
pub fn s6sel3(&self) -> S6SEL3_R[src]
Bit 20 - Switch 6 for OPAMP3 enable
pub fn s5sel3(&self) -> S5SEL3_R[src]
Bit 19 - Switch 5 for OPAMP3 enable
pub fn s4sel3(&self) -> S4SEL3_R[src]
Bit 18 - Switch 4 for OPAMP3 enable
pub fn s3sel3(&self) -> S3SEL3_R[src]
Bit 17 - Switch 3 for OPAMP3 Enable
pub fn opa3pd(&self) -> OPA3PD_R[src]
Bit 16 - OPAMP3 power down
pub fn opa2lpm(&self) -> OPA2LPM_R[src]
Bit 15 - OPAMP2 low power mode
pub fn opa2cal_h(&self) -> OPA2CAL_H_R[src]
Bit 14 - OPAMP2 offset calibration for N differential pair
pub fn opa2cal_l(&self) -> OPA2CAL_L_R[src]
Bit 13 - OPAMP2 offset Calibration for P differential pair
pub fn s6sel2(&self) -> S6SEL2_R[src]
Bit 12 - Switch 6 for OPAMP2 enable
pub fn s5sel2(&self) -> S5SEL2_R[src]
Bit 11 - Switch 5 for OPAMP2 enable
pub fn s4sel2(&self) -> S4SEL2_R[src]
Bit 10 - Switch 4 for OPAMP2 enable
pub fn s3sel2(&self) -> S3SEL2_R[src]
Bit 9 - Switch 3 for OPAMP2 enable
pub fn opa2pd(&self) -> OPA2PD_R[src]
Bit 8 - OPAMP2 power down
pub fn opa1lpm(&self) -> OPA1LPM_R[src]
Bit 7 - OPAMP1 low power mode
pub fn opa1cal_h(&self) -> OPA1CAL_H_R[src]
Bit 6 - OPAMP1 offset calibration for N differential pair
pub fn opa1cal_l(&self) -> OPA1CAL_L_R[src]
Bit 5 - OPAMP1 offset calibration for P differential pair
pub fn s6sel1(&self) -> S6SEL1_R[src]
Bit 4 - Switch 6 for OPAMP1 enable
pub fn s5sel1(&self) -> S5SEL1_R[src]
Bit 3 - Switch 5 for OPAMP1 enable
pub fn s4sel1(&self) -> S4SEL1_R[src]
Bit 2 - Switch 4 for OPAMP1 enable
pub fn s3sel1(&self) -> S3SEL1_R[src]
Bit 1 - Switch 3 for OPAMP1 enable
pub fn opa1pd(&self) -> OPA1PD_R[src]
Bit 0 - OPAMP1 power down
impl R<u32, Reg<u32, _OTR>>[src]
pub fn ot_user(&self) -> OT_USER_R[src]
Bit 31 - Select user or factory trimming value
pub fn ao3_opt_offset_trim(&self) -> AO3_OPT_OFFSET_TRIM_R[src]
Bits 20:29 - OPAMP3, 10-bit offset trim value for normal mode
pub fn ao2_opt_offset_trim(&self) -> AO2_OPT_OFFSET_TRIM_R[src]
Bits 10:19 - OPAMP2, 10-bit offset trim value for normal mode
pub fn ao1_opt_offset_trim(&self) -> AO1_OPT_OFFSET_TRIM_R[src]
Bits 0:9 - OPAMP1, 10-bit offset trim value for normal mode
impl R<u32, Reg<u32, _LPOTR>>[src]
pub fn ao3_opt_offset_trim_lp(&self) -> AO3_OPT_OFFSET_TRIM_LP_R[src]
Bits 20:29 - OPAMP3, 10-bit offset trim value for low power mode
pub fn ao2_opt_offset_trim_lp(&self) -> AO2_OPT_OFFSET_TRIM_LP_R[src]
Bits 10:19 - OPAMP2, 10-bit offset trim value for low power mode
pub fn ao1_opt_offset_trim_lp(&self) -> AO1_OPT_OFFSET_TRIM_LP_R[src]
Bits 0:9 - OPAMP1, 10-bit offset trim value for low power mode
impl R<bool, PDDS_A>[src]
pub fn variant(&self) -> PDDS_A[src]
Get enumerated values variant
pub fn is_stop_mode(&self) -> bool[src]
Checks if the value of the field is STOP_MODE
pub fn is_standby_mode(&self) -> bool[src]
Checks if the value of the field is STANDBY_MODE
impl R<u32, Reg<u32, _CR>>[src]
pub fn lprun(&self) -> LPRUN_R[src]
Bit 14 - Low power run mode
pub fn vos(&self) -> VOS_R[src]
Bits 11:12 - Voltage scaling range selection
pub fn fwu(&self) -> FWU_R[src]
Bit 10 - Fast wakeup
pub fn ulp(&self) -> ULP_R[src]
Bit 9 - Ultralow power mode
pub fn dbp(&self) -> DBP_R[src]
Bit 8 - Disable backup domain write protection
pub fn pls(&self) -> PLS_R[src]
Bits 5:7 - PVD level selection
pub fn pvde(&self) -> PVDE_R[src]
Bit 4 - Power voltage detector enable
pub fn csbf(&self) -> CSBF_R[src]
Bit 3 - Clear standby flag
pub fn cwuf(&self) -> CWUF_R[src]
Bit 2 - Clear wakeup flag
pub fn pdds(&self) -> PDDS_R[src]
Bit 1 - Power down deepsleep
pub fn lpsdsr(&self) -> LPSDSR_R[src]
Bit 0 - Low-power deep sleep
impl R<u32, Reg<u32, _CSR>>[src]
pub fn ewup3(&self) -> EWUP3_R[src]
Bit 10 - Enable WKUP pin 3
pub fn ewup2(&self) -> EWUP2_R[src]
Bit 9 - Enable WKUP pin 2
pub fn ewup1(&self) -> EWUP1_R[src]
Bit 8 - Enable WKUP pin 1
pub fn reglpf(&self) -> REGLPF_R[src]
Bit 5 - Regulator LP flag
pub fn vosf(&self) -> VOSF_R[src]
Bit 4 - Voltage Scaling select flag
pub fn vrefintrdyf(&self) -> VREFINTRDYF_R[src]
Bit 3 - Internal voltage reference (VREFINT) ready flag
pub fn pvdo(&self) -> PVDO_R[src]
Bit 2 - PVD output
pub fn sbf(&self) -> SBF_R[src]
Bit 1 - Standby flag
pub fn wuf(&self) -> WUF_R[src]
Bit 0 - Wakeup flag
impl R<u32, Reg<u32, _CR>>[src]
pub fn rtcpre1(&self) -> RTCPRE1_R[src]
Bit 30 - TC/LCD prescaler
pub fn rtcpre0(&self) -> RTCPRE0_R[src]
Bit 29 - RTCPRE0
pub fn csson(&self) -> CSSON_R[src]
Bit 28 - Clock security system enable
pub fn pllrdy(&self) -> PLLRDY_R[src]
Bit 25 - PLL clock ready flag
pub fn pllon(&self) -> PLLON_R[src]
Bit 24 - PLL enable
pub fn hsebyp(&self) -> HSEBYP_R[src]
Bit 18 - HSE clock bypass
pub fn hserdy(&self) -> HSERDY_R[src]
Bit 17 - HSE clock ready flag
pub fn hseon(&self) -> HSEON_R[src]
Bit 16 - HSE clock enable
pub fn msirdy(&self) -> MSIRDY_R[src]
Bit 9 - MSI clock ready flag
pub fn msion(&self) -> MSION_R[src]
Bit 8 - MSI clock enable
pub fn hsirdy(&self) -> HSIRDY_R[src]
Bit 1 - Internal high-speed clock ready flag
pub fn hsion(&self) -> HSION_R[src]
Bit 0 - Internal high-speed clock enable
impl R<u32, Reg<u32, _ICSCR>>[src]
pub fn msitrim(&self) -> MSITRIM_R[src]
Bits 24:31 - MSI clock trimming
pub fn msical(&self) -> MSICAL_R[src]
Bits 16:23 - MSI clock calibration
pub fn msirange(&self) -> MSIRANGE_R[src]
Bits 13:15 - MSI clock ranges
pub fn hsitrim(&self) -> HSITRIM_R[src]
Bits 8:12 - High speed internal clock trimming
pub fn hsical(&self) -> HSICAL_R[src]
Bits 0:7 - nternal high speed clock calibration
impl R<u32, Reg<u32, _CFGR>>[src]
pub fn mcopre(&self) -> MCOPRE_R[src]
Bits 28:30 - Microcontroller clock output prescaler
pub fn mcosel(&self) -> MCOSEL_R[src]
Bits 24:26 - Microcontroller clock output selection
pub fn plldiv(&self) -> PLLDIV_R[src]
Bits 22:23 - PLL output division
pub fn pllmul(&self) -> PLLMUL_R[src]
Bits 18:21 - PLL multiplication factor
pub fn pllsrc(&self) -> PLLSRC_R[src]
Bit 16 - PLL entry clock source
pub fn ppre2(&self) -> PPRE2_R[src]
Bits 11:13 - APB high-speed prescaler (APB2)
pub fn ppre1(&self) -> PPRE1_R[src]
Bits 8:10 - APB low-speed prescaler (APB1)
pub fn hpre(&self) -> HPRE_R[src]
Bits 4:7 - AHB prescaler
pub fn sws(&self) -> SWS_R[src]
Bits 2:3 - System clock switch status
pub fn sw(&self) -> SW_R[src]
Bits 0:1 - System clock switch
impl R<u32, Reg<u32, _CIR>>[src]
pub fn msirdyie(&self) -> MSIRDYIE_R[src]
Bit 13 - MSI ready interrupt enable
pub fn pllrdyie(&self) -> PLLRDYIE_R[src]
Bit 12 - PLL ready interrupt enable
pub fn hserdyie(&self) -> HSERDYIE_R[src]
Bit 11 - HSE ready interrupt enable
pub fn hsirdyie(&self) -> HSIRDYIE_R[src]
Bit 10 - HSI ready interrupt enable
pub fn lserdyie(&self) -> LSERDYIE_R[src]
Bit 9 - LSE ready interrupt enable
pub fn lsirdyie(&self) -> LSIRDYIE_R[src]
Bit 8 - LSI ready interrupt enable
pub fn cssf(&self) -> CSSF_R[src]
Bit 7 - Clock security system interrupt flag
pub fn msirdyf(&self) -> MSIRDYF_R[src]
Bit 5 - MSI ready interrupt flag
pub fn pllrdyf(&self) -> PLLRDYF_R[src]
Bit 4 - PLL ready interrupt flag
pub fn hserdyf(&self) -> HSERDYF_R[src]
Bit 3 - HSE ready interrupt flag
pub fn hsirdyf(&self) -> HSIRDYF_R[src]
Bit 2 - HSI ready interrupt flag
pub fn lserdyf(&self) -> LSERDYF_R[src]
Bit 1 - LSE ready interrupt flag
pub fn lsirdyf(&self) -> LSIRDYF_R[src]
Bit 0 - LSI ready interrupt flag
impl R<u32, Reg<u32, _AHBRSTR>>[src]
pub fn fsmcrst(&self) -> FSMCRST_R[src]
Bit 30 - FSMC reset
pub fn dma2rst(&self) -> DMA2RST_R[src]
Bit 25 - DMA2 reset
pub fn dma1rst(&self) -> DMA1RST_R[src]
Bit 24 - DMA1 reset
pub fn flitfrst(&self) -> FLITFRST_R[src]
Bit 15 - FLITF reset
pub fn crcrst(&self) -> CRCRST_R[src]
Bit 12 - CRC reset
pub fn gpiogrst(&self) -> GPIOGRST_R[src]
Bit 7 - IO port G reset
pub fn gpiofrst(&self) -> GPIOFRST_R[src]
Bit 6 - IO port F reset
pub fn gpiohrst(&self) -> GPIOHRST_R[src]
Bit 5 - IO port H reset
pub fn gpioerst(&self) -> GPIOERST_R[src]
Bit 4 - IO port E reset
pub fn gpiodrst(&self) -> GPIODRST_R[src]
Bit 3 - IO port D reset
pub fn gpiocrst(&self) -> GPIOCRST_R[src]
Bit 2 - IO port C reset
pub fn gpiobrst(&self) -> GPIOBRST_R[src]
Bit 1 - IO port B reset
pub fn gpioarst(&self) -> GPIOARST_R[src]
Bit 0 - IO port A reset
impl R<u32, Reg<u32, _APB2RSTR>>[src]
pub fn usart1rst(&self) -> USART1RST_R[src]
Bit 14 - USART1RST
pub fn spi1rst(&self) -> SPI1RST_R[src]
Bit 12 - SPI1RST
pub fn sdiorst(&self) -> SDIORST_R[src]
Bit 11 - SDIORST
pub fn adc1rst(&self) -> ADC1RST_R[src]
Bit 9 - ADC1RST
pub fn tm11rst(&self) -> TM11RST_R[src]
Bit 4 - TM11RST
pub fn tm10rst(&self) -> TM10RST_R[src]
Bit 3 - TM10RST
pub fn tim9rst(&self) -> TIM9RST_R[src]
Bit 2 - TIM9RST
pub fn syscfgrst(&self) -> SYSCFGRST_R[src]
Bit 0 - SYSCFGRST
impl R<u32, Reg<u32, _APB1RSTR>>[src]
pub fn comprst(&self) -> COMPRST_R[src]
Bit 31 - COMP interface reset
pub fn dacrst(&self) -> DACRST_R[src]
Bit 29 - DAC interface reset
pub fn pwrrst(&self) -> PWRRST_R[src]
Bit 28 - Power interface reset
pub fn usbrst(&self) -> USBRST_R[src]
Bit 23 - USB reset
pub fn i2c2rst(&self) -> I2C2RST_R[src]
Bit 22 - I2C 2 reset
pub fn i2c1rst(&self) -> I2C1RST_R[src]
Bit 21 - I2C 1 reset
pub fn uart5rst(&self) -> UART5RST_R[src]
Bit 20 - UART 5 reset
pub fn uart4rst(&self) -> UART4RST_R[src]
Bit 19 - UART 4 reset
pub fn usart3rst(&self) -> USART3RST_R[src]
Bit 18 - USART 3 reset
pub fn usart2rst(&self) -> USART2RST_R[src]
Bit 17 - USART 2 reset
pub fn spi3rst(&self) -> SPI3RST_R[src]
Bit 15 - SPI 3 reset
pub fn spi2rst(&self) -> SPI2RST_R[src]
Bit 14 - SPI 2 reset
pub fn wwdrst(&self) -> WWDRST_R[src]
Bit 11 - Window watchdog reset
pub fn lcdrst(&self) -> LCDRST_R[src]
Bit 9 - LCD reset
pub fn tim7rst(&self) -> TIM7RST_R[src]
Bit 5 - Timer 7 reset
pub fn tim6rst(&self) -> TIM6RST_R[src]
Bit 4 - Timer 6reset
pub fn tim5rst(&self) -> TIM5RST_R[src]
Bit 3 - Timer 5 reset
pub fn tim4rst(&self) -> TIM4RST_R[src]
Bit 2 - Timer 4 reset
pub fn tim3rst(&self) -> TIM3RST_R[src]
Bit 1 - Timer 3 reset
pub fn tim2rst(&self) -> TIM2RST_R[src]
Bit 0 - Timer 2 reset
impl R<u32, Reg<u32, _AHBENR>>[src]
pub fn fsmcen(&self) -> FSMCEN_R[src]
Bit 30 - FSMCEN
pub fn dma2en(&self) -> DMA2EN_R[src]
Bit 25 - DMA2 clock enable
pub fn dma1en(&self) -> DMA1EN_R[src]
Bit 24 - DMA1 clock enable
pub fn flitfen(&self) -> FLITFEN_R[src]
Bit 15 - FLITF clock enable
pub fn crcen(&self) -> CRCEN_R[src]
Bit 12 - CRC clock enable
pub fn gpiopgen(&self) -> GPIOPGEN_R[src]
Bit 7 - IO port G clock enable
pub fn gpiopfen(&self) -> GPIOPFEN_R[src]
Bit 6 - IO port F clock enable
pub fn gpiophen(&self) -> GPIOPHEN_R[src]
Bit 5 - IO port H clock enable
pub fn gpiopeen(&self) -> GPIOPEEN_R[src]
Bit 4 - IO port E clock enable
pub fn gpiopden(&self) -> GPIOPDEN_R[src]
Bit 3 - IO port D clock enable
pub fn gpiopcen(&self) -> GPIOPCEN_R[src]
Bit 2 - IO port C clock enable
pub fn gpiopben(&self) -> GPIOPBEN_R[src]
Bit 1 - IO port B clock enable
pub fn gpiopaen(&self) -> GPIOPAEN_R[src]
Bit 0 - IO port A clock enable
impl R<u32, Reg<u32, _APB2ENR>>[src]
pub fn usart1en(&self) -> USART1EN_R[src]
Bit 14 - USART1 clock enable
pub fn spi1en(&self) -> SPI1EN_R[src]
Bit 12 - SPI 1 clock enable
pub fn sdioen(&self) -> SDIOEN_R[src]
Bit 11 - SDIO clock enable
pub fn adc1en(&self) -> ADC1EN_R[src]
Bit 9 - ADC1 interface clock enable
pub fn tim11en(&self) -> TIM11EN_R[src]
Bit 4 - TIM11 timer clock enable
pub fn tim10en(&self) -> TIM10EN_R[src]
Bit 3 - TIM10 timer clock enable
pub fn tim9en(&self) -> TIM9EN_R[src]
Bit 2 - TIM9 timer clock enable
pub fn syscfgen(&self) -> SYSCFGEN_R[src]
Bit 0 - System configuration controller clock enable
impl R<u32, Reg<u32, _APB1ENR>>[src]
pub fn compen(&self) -> COMPEN_R[src]
Bit 31 - COMP interface clock enable
pub fn dacen(&self) -> DACEN_R[src]
Bit 29 - DAC interface clock enable
pub fn pwren(&self) -> PWREN_R[src]
Bit 28 - Power interface clock enable
pub fn usben(&self) -> USBEN_R[src]
Bit 23 - USB clock enable
pub fn i2c2en(&self) -> I2C2EN_R[src]
Bit 22 - I2C 2 clock enable
pub fn i2c1en(&self) -> I2C1EN_R[src]
Bit 21 - I2C 1 clock enable
pub fn usart5en(&self) -> USART5EN_R[src]
Bit 20 - UART 5 clock enable
pub fn usart4en(&self) -> USART4EN_R[src]
Bit 19 - UART 4 clock enable
pub fn usart3en(&self) -> USART3EN_R[src]
Bit 18 - USART 3 clock enable
pub fn usart2en(&self) -> USART2EN_R[src]
Bit 17 - USART 2 clock enable
pub fn spi3en(&self) -> SPI3EN_R[src]
Bit 15 - SPI 3 clock enable
pub fn spi2en(&self) -> SPI2EN_R[src]
Bit 14 - SPI 2 clock enable
pub fn wwdgen(&self) -> WWDGEN_R[src]
Bit 11 - Window watchdog clock enable
pub fn lcden(&self) -> LCDEN_R[src]
Bit 9 - LCD clock enable
pub fn tim7en(&self) -> TIM7EN_R[src]
Bit 5 - Timer 7 clock enable
pub fn tim6en(&self) -> TIM6EN_R[src]
Bit 4 - Timer 6 clock enable
pub fn tim5en(&self) -> TIM5EN_R[src]
Bit 3 - Timer 5 clock enable
pub fn tim4en(&self) -> TIM4EN_R[src]
Bit 2 - Timer 4 clock enable
pub fn tim3en(&self) -> TIM3EN_R[src]
Bit 1 - Timer 3 clock enable
pub fn tim2en(&self) -> TIM2EN_R[src]
Bit 0 - Timer 2 clock enable
impl R<u32, Reg<u32, _AHBLPENR>>[src]
pub fn dma2lpen(&self) -> DMA2LPEN_R[src]
Bit 25 - DMA2 clock enable during Sleep mode
pub fn dma1lpen(&self) -> DMA1LPEN_R[src]
Bit 24 - DMA1 clock enable during Sleep mode
pub fn sramlpen(&self) -> SRAMLPEN_R[src]
Bit 16 - SRAM clock enable during Sleep mode
pub fn flitflpen(&self) -> FLITFLPEN_R[src]
Bit 15 - FLITF clock enable during Sleep mode
pub fn crclpen(&self) -> CRCLPEN_R[src]
Bit 12 - CRC clock enable during Sleep mode
pub fn gpioglpen(&self) -> GPIOGLPEN_R[src]
Bit 7 - IO port G clock enable during Sleep mode
pub fn gpioflpen(&self) -> GPIOFLPEN_R[src]
Bit 6 - IO port F clock enable during Sleep mode
pub fn gpiohlpen(&self) -> GPIOHLPEN_R[src]
Bit 5 - IO port H clock enable during Sleep mode
pub fn gpioelpen(&self) -> GPIOELPEN_R[src]
Bit 4 - IO port E clock enable during Sleep mode
pub fn gpiodlpen(&self) -> GPIODLPEN_R[src]
Bit 3 - IO port D clock enable during Sleep mode
pub fn gpioclpen(&self) -> GPIOCLPEN_R[src]
Bit 2 - IO port C clock enable during Sleep mode
pub fn gpioblpen(&self) -> GPIOBLPEN_R[src]
Bit 1 - IO port B clock enable during Sleep mode
pub fn gpioalpen(&self) -> GPIOALPEN_R[src]
Bit 0 - IO port A clock enable during Sleep mode
impl R<u32, Reg<u32, _APB2LPENR>>[src]
pub fn usart1lpen(&self) -> USART1LPEN_R[src]
Bit 14 - USART1 clock enable during Sleep mode
pub fn spi1lpen(&self) -> SPI1LPEN_R[src]
Bit 12 - SPI 1 clock enable during Sleep mode
pub fn sdiolpen(&self) -> SDIOLPEN_R[src]
Bit 11 - SDIO clock enable during Sleep mode
pub fn adc1lpen(&self) -> ADC1LPEN_R[src]
Bit 9 - ADC1 interface clock enable during Sleep mode
pub fn tim11lpen(&self) -> TIM11LPEN_R[src]
Bit 4 - TIM11 timer clock enable during Sleep mode
pub fn tim10lpen(&self) -> TIM10LPEN_R[src]
Bit 3 - TIM10 timer clock enable during Sleep mode
pub fn tim9lpen(&self) -> TIM9LPEN_R[src]
Bit 2 - TIM9 timer clock enable during Sleep mode
pub fn syscfglpen(&self) -> SYSCFGLPEN_R[src]
Bit 0 - System configuration controller clock enable during Sleep mode
impl R<u32, Reg<u32, _APB1LPENR>>[src]
pub fn complpen(&self) -> COMPLPEN_R[src]
Bit 31 - COMP interface clock enable during Sleep mode
pub fn daclpen(&self) -> DACLPEN_R[src]
Bit 29 - DAC interface clock enable during Sleep mode
pub fn pwrlpen(&self) -> PWRLPEN_R[src]
Bit 28 - Power interface clock enable during Sleep mode
pub fn usblpen(&self) -> USBLPEN_R[src]
Bit 23 - USB clock enable during Sleep mode
pub fn i2c2lpen(&self) -> I2C2LPEN_R[src]
Bit 22 - I2C 2 clock enable during Sleep mode
pub fn i2c1lpen(&self) -> I2C1LPEN_R[src]
Bit 21 - I2C 1 clock enable during Sleep mode
pub fn usart3lpen(&self) -> USART3LPEN_R[src]
Bit 18 - USART 3 clock enable during Sleep mode
pub fn usart2lpen(&self) -> USART2LPEN_R[src]
Bit 17 - USART 2 clock enable during Sleep mode
pub fn spi2lpen(&self) -> SPI2LPEN_R[src]
Bit 14 - SPI 2 clock enable during Sleep mode
pub fn wwdglpen(&self) -> WWDGLPEN_R[src]
Bit 11 - Window watchdog clock enable during Sleep mode
pub fn lcdlpen(&self) -> LCDLPEN_R[src]
Bit 9 - LCD clock enable during Sleep mode
pub fn tim7lpen(&self) -> TIM7LPEN_R[src]
Bit 5 - Timer 7 clock enable during Sleep mode
pub fn tim6lpen(&self) -> TIM6LPEN_R[src]
Bit 4 - Timer 6 clock enable during Sleep mode
pub fn tim4lpen(&self) -> TIM4LPEN_R[src]
Bit 2 - Timer 4 clock enable during Sleep mode
pub fn tim3lpen(&self) -> TIM3LPEN_R[src]
Bit 1 - Timer 3 clock enable during Sleep mode
pub fn tim2lpen(&self) -> TIM2LPEN_R[src]
Bit 0 - Timer 2 clock enable during Sleep mode
impl R<u32, Reg<u32, _CSR>>[src]
pub fn lpwrstf(&self) -> LPWRSTF_R[src]
Bit 31 - Low-power reset flag
pub fn wwdgrstf(&self) -> WWDGRSTF_R[src]
Bit 30 - Window watchdog reset flag
pub fn iwdgrstf(&self) -> IWDGRSTF_R[src]
Bit 29 - Independent watchdog reset flag
pub fn sftrstf(&self) -> SFTRSTF_R[src]
Bit 28 - Software reset flag
pub fn porrstf(&self) -> PORRSTF_R[src]
Bit 27 - POR/PDR reset flag
pub fn pinrstf(&self) -> PINRSTF_R[src]
Bit 26 - PIN reset flag
pub fn rmvf(&self) -> RMVF_R[src]
Bit 24 - Remove reset flag
pub fn rtcrst(&self) -> RTCRST_R[src]
Bit 23 - RTC software reset
pub fn rtcen(&self) -> RTCEN_R[src]
Bit 22 - RTC clock enable
pub fn rtcsel(&self) -> RTCSEL_R[src]
Bits 16:17 - RTC and LCD clock source selection
pub fn lsebyp(&self) -> LSEBYP_R[src]
Bit 10 - External low-speed oscillator bypass
pub fn lserdy(&self) -> LSERDY_R[src]
Bit 9 - External low-speed oscillator ready
pub fn lseon(&self) -> LSEON_R[src]
Bit 8 - External low-speed oscillator enable
pub fn lsirdy(&self) -> LSIRDY_R[src]
Bit 1 - Internal low-speed oscillator ready
pub fn lsion(&self) -> LSION_R[src]
Bit 0 - Internal low-speed oscillator enable
impl R<u32, Reg<u32, _ICR>>[src]
pub fn ic4(&self) -> IC4_R[src]
Bit 21 - IC4
pub fn ic3(&self) -> IC3_R[src]
Bit 20 - IC3
pub fn ic2(&self) -> IC2_R[src]
Bit 19 - IC2
pub fn ic1(&self) -> IC1_R[src]
Bit 18 - IC1
pub fn tim(&self) -> TIM_R[src]
Bits 16:17 - Timer select bits
pub fn ic4ios(&self) -> IC4IOS_R[src]
Bits 12:15 - Input capture 4 select bits
pub fn ic3ios(&self) -> IC3IOS_R[src]
Bits 8:11 - Input capture 3 select bits
pub fn ic2ios(&self) -> IC2IOS_R[src]
Bits 4:7 - Input capture 2 select bits
pub fn ic1ios(&self) -> IC1IOS_R[src]
Bits 0:3 - Input capture 1 select bits
impl R<u32, Reg<u32, _ASCR1>>[src]
pub fn scm(&self) -> SCM_R[src]
Bit 31 - Switch control mode
pub fn ch30gr11_4(&self) -> CH30GR11_4_R[src]
Bit 30 - Analog switch control
pub fn ch29gr11_3(&self) -> CH29GR11_3_R[src]
Bit 29 - Analog switch control
pub fn ch28gr11_2(&self) -> CH28GR11_2_R[src]
Bit 28 - Analog switch control
pub fn ch27gr11_1(&self) -> CH27GR11_1_R[src]
Bit 27 - Analog switch control
pub fn vcomp(&self) -> VCOMP_R[src]
Bit 26 - ADC analog switch selection for internal node to comparator 1
pub fn ch25(&self) -> CH25_R[src]
Bit 25 - Analog I/O switch control of channel CH25
pub fn ch24(&self) -> CH24_R[src]
Bit 24 - Analog I/O switch control of channel CH24
pub fn ch23(&self) -> CH23_R[src]
Bit 23 - Analog I/O switch control of channel CH23
pub fn ch22(&self) -> CH22_R[src]
Bit 22 - Analog I/O switch control of channel CH22
pub fn ch21gr7_4(&self) -> CH21GR7_4_R[src]
Bit 21 - Analog switch control
pub fn ch20gr7_3(&self) -> CH20GR7_3_R[src]
Bit 20 - Analog switch control
pub fn ch19gr7_2(&self) -> CH19GR7_2_R[src]
Bit 19 - Analog switch control
pub fn ch18gr7_1(&self) -> CH18GR7_1_R[src]
Bit 18 - Analog switch control
pub fn ch31gr7_1(&self) -> CH31GR7_1_R[src]
Bit 16 - Analog switch control
pub fn ch15gr9_2(&self) -> CH15GR9_2_R[src]
Bit 15 - Analog switch control
pub fn ch14gr9_1(&self) -> CH14GR9_1_R[src]
Bit 14 - Analog switch control
pub fn ch13gr8_4(&self) -> CH13GR8_4_R[src]
Bit 13 - Analog switch control
pub fn ch12gr8_3(&self) -> CH12GR8_3_R[src]
Bit 12 - Analog switch control
pub fn ch11gr8_2(&self) -> CH11GR8_2_R[src]
Bit 11 - Analog switch control
pub fn ch10gr8_1(&self) -> CH10GR8_1_R[src]
Bit 10 - Analog switch control
pub fn ch9gr3_2(&self) -> CH9GR3_2_R[src]
Bit 9 - Analog switch control
pub fn ch8gr3_1(&self) -> CH8GR3_1_R[src]
Bit 8 - Analog switch control
pub fn ch7gr2_2(&self) -> CH7GR2_2_R[src]
Bit 7 - Analog switch control
pub fn ch6gr2_1(&self) -> CH6GR2_1_R[src]
Bit 6 - Analog switch control
pub fn comp1_sw1(&self) -> COMP1_SW1_R[src]
Bit 5 - Comparator 1 analog switch
pub fn ch31gr11_5(&self) -> CH31GR11_5_R[src]
Bit 4 - Analog switch control
pub fn ch3gr1_4(&self) -> CH3GR1_4_R[src]
Bit 3 - Analog switch control
pub fn ch2gr1_3(&self) -> CH2GR1_3_R[src]
Bit 2 - Analog switch control
pub fn ch1gr1_2(&self) -> CH1GR1_2_R[src]
Bit 1 - Analog switch control
pub fn ch0gr1_1(&self) -> CH0GR1_1_R[src]
Bit 0 - Analog switch control
impl R<u32, Reg<u32, _ASCR2>>[src]
pub fn gr5_4(&self) -> GR5_4_R[src]
Bit 29 - GR5_4 analog switch control
pub fn gr6_4(&self) -> GR6_4_R[src]
Bit 28 - GR6_4 analog switch control
pub fn gr6_3(&self) -> GR6_3_R[src]
Bit 27 - GR6_3 analog switch control
pub fn gr7_7(&self) -> GR7_7_R[src]
Bit 26 - GR7_7 analog switch control
pub fn gr7_6(&self) -> GR7_6_R[src]
Bit 25 - GR7_6 analog switch control
pub fn gr7_5(&self) -> GR7_5_R[src]
Bit 24 - GR7_5 analog switch control
pub fn gr2_5(&self) -> GR2_5_R[src]
Bit 23 - GR2_5 analog switch control
pub fn gr2_4(&self) -> GR2_4_R[src]
Bit 22 - GR2_4 analog switch control
pub fn gr2_3(&self) -> GR2_3_R[src]
Bit 21 - GR2_3 analog switch control
pub fn gr9_4(&self) -> GR9_4_R[src]
Bit 20 - GR9_4 analog switch control
pub fn gr9_3(&self) -> GR9_3_R[src]
Bit 19 - GR9_3 analog switch control
pub fn gr3_5(&self) -> GR3_5_R[src]
Bit 18 - GR3_5 analog switch control
pub fn gr3_4(&self) -> GR3_4_R[src]
Bit 17 - GR3_4 analog switch control
pub fn gr3_3(&self) -> GR3_3_R[src]
Bit 16 - GR3_3 analog switch control
pub fn gr4_3(&self) -> GR4_3_R[src]
Bit 11 - GR4_3 analog switch control
pub fn gr4_2(&self) -> GR4_2_R[src]
Bit 10 - GR4_2 analog switch control
pub fn gr4_1(&self) -> GR4_1_R[src]
Bit 9 - GR4_1 analog switch control
pub fn gr5_3(&self) -> GR5_3_R[src]
Bit 8 - GR5_3 analog switch control
pub fn gr5_2(&self) -> GR5_2_R[src]
Bit 7 - GR5_2 analog switch control
pub fn gr5_1(&self) -> GR5_1_R[src]
Bit 6 - GR5_1 analog switch control
pub fn gr6_2(&self) -> GR6_2_R[src]
Bit 5 - GR6_2 analog switch control
pub fn gr6_1(&self) -> GR6_1_R[src]
Bit 4 - GR6_1 analog switch control
pub fn gr10_4(&self) -> GR10_4_R[src]
Bit 3 - GR10_4 analog switch control
pub fn gr10_3(&self) -> GR10_3_R[src]
Bit 2 - GR10_3 analog switch control
pub fn gr10_2(&self) -> GR10_2_R[src]
Bit 1 - GR10_2 analog switch control
pub fn gr10_1(&self) -> GR10_1_R[src]
Bit 0 - GR10_1 analog switch control
impl R<u32, Reg<u32, _HYSCR1>>[src]
pub fn pb(&self) -> PB_R[src]
Bits 16:31 - Port B hysteresis control on/off
pub fn pa(&self) -> PA_R[src]
Bits 0:15 - Port A hysteresis control on/off
impl R<u32, Reg<u32, _HYSCR2>>[src]
pub fn pd(&self) -> PD_R[src]
Bits 16:31 - Port D hysteresis control on/off
pub fn pc(&self) -> PC_R[src]
Bits 0:15 - Port C hysteresis control on/off
impl R<u32, Reg<u32, _HYSCR3>>[src]
pub fn pf(&self) -> PF_R[src]
Bits 16:31 - Port F hysteresis control on/off
pub fn pe(&self) -> PE_R[src]
Bits 0:15 - Port E hysteresis control on/off
impl R<u32, Reg<u32, _HYSCR4>>[src]
impl R<u32, Reg<u32, _TR>>[src]
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format
impl R<u32, Reg<u32, _DR>>[src]
pub fn yt(&self) -> YT_R[src]
Bits 20:23 - Year tens in BCD format
pub fn yu(&self) -> YU_R[src]
Bits 16:19 - Year units in BCD format
pub fn wdu(&self) -> WDU_R[src]
Bits 13:15 - Week day units
pub fn mt(&self) -> MT_R[src]
Bit 12 - Month tens in BCD format
pub fn mu(&self) -> MU_R[src]
Bits 8:11 - Month units in BCD format
pub fn dt(&self) -> DT_R[src]
Bits 4:5 - Date tens in BCD format
pub fn du(&self) -> DU_R[src]
Bits 0:3 - Date units in BCD format
impl R<u32, Reg<u32, _CR>>[src]
pub fn coe(&self) -> COE_R[src]
Bit 23 - Calibration output enable
pub fn osel(&self) -> OSEL_R[src]
Bits 21:22 - Output selection
pub fn pol(&self) -> POL_R[src]
Bit 20 - Output polarity
pub fn cosel(&self) -> COSEL_R[src]
Bit 19 - Calibration output selection
pub fn bkp(&self) -> BKP_R[src]
Bit 18 - Backup
pub fn sub1h(&self) -> SUB1H_R[src]
Bit 17 - Subtract 1 hour
pub fn add1h(&self) -> ADD1H_R[src]
Bit 16 - Add 1 hour
pub fn tsie(&self) -> TSIE_R[src]
Bit 15 - Time-stamp interrupt enable
pub fn wutie(&self) -> WUTIE_R[src]
Bit 14 - Wakeup timer interrupt enable
pub fn alrbie(&self) -> ALRBIE_R[src]
Bit 13 - Alarm B interrupt enable
pub fn alraie(&self) -> ALRAIE_R[src]
Bit 12 - Alarm A interrupt enable
pub fn tse(&self) -> TSE_R[src]
Bit 11 - Time stamp enable
pub fn wute(&self) -> WUTE_R[src]
Bit 10 - Wakeup timer enable
pub fn alrbe(&self) -> ALRBE_R[src]
Bit 9 - Alarm B enable
pub fn alrae(&self) -> ALRAE_R[src]
Bit 8 - Alarm A enable
pub fn dce(&self) -> DCE_R[src]
Bit 7 - Coarse digital calibration enable
pub fn fmt(&self) -> FMT_R[src]
Bit 6 - Hour format
pub fn bypshad(&self) -> BYPSHAD_R[src]
Bit 5 - Bypass the shadow registers
pub fn refckon(&self) -> REFCKON_R[src]
Bit 4 - Reference clock detection enable
pub fn tsedge(&self) -> TSEDGE_R[src]
Bit 3 - Time-stamp event active edge
pub fn wcksel(&self) -> WCKSEL_R[src]
Bits 0:2 - WCKSEL
impl R<u32, Reg<u32, _ISR>>[src]
pub fn recalpf(&self) -> RECALPF_R[src]
Bit 16 - Recalibration pending Flag
pub fn tamp3f(&self) -> TAMP3F_R[src]
Bit 15 - TAMPER3 detection flag
pub fn tamp2f(&self) -> TAMP2F_R[src]
Bit 14 - TAMPER2 detection flag
pub fn tamp1f(&self) -> TAMP1F_R[src]
Bit 13 - Tamper detection flag
pub fn tsovf(&self) -> TSOVF_R[src]
Bit 12 - Timestamp overflow flag
pub fn tsf(&self) -> TSF_R[src]
Bit 11 - Timestamp flag
pub fn wutf(&self) -> WUTF_R[src]
Bit 10 - Wakeup timer flag
pub fn alrbf(&self) -> ALRBF_R[src]
Bit 9 - Alarm B flag
pub fn alraf(&self) -> ALRAF_R[src]
Bit 8 - Alarm A flag
pub fn init(&self) -> INIT_R[src]
Bit 7 - Initialization mode
pub fn initf(&self) -> INITF_R[src]
Bit 6 - Initialization flag
pub fn rsf(&self) -> RSF_R[src]
Bit 5 - Registers synchronization flag
pub fn inits(&self) -> INITS_R[src]
Bit 4 - Initialization status flag
pub fn shpf(&self) -> SHPF_R[src]
Bit 3 - Shift operation pending
pub fn wutwf(&self) -> WUTWF_R[src]
Bit 2 - Wakeup timer write flag
pub fn alrbwf(&self) -> ALRBWF_R[src]
Bit 1 - Alarm B write flag
pub fn alrawf(&self) -> ALRAWF_R[src]
Bit 0 - Alarm A write flag
impl R<u32, Reg<u32, _PRER>>[src]
pub fn prediv_a(&self) -> PREDIV_A_R[src]
Bits 16:22 - Asynchronous prescaler factor
pub fn prediv_s(&self) -> PREDIV_S_R[src]
Bits 0:14 - Synchronous prescaler factor
impl R<u32, Reg<u32, _WUTR>>[src]
impl R<u32, Reg<u32, _CALIBR>>[src]
pub fn dcs(&self) -> DCS_R[src]
Bit 7 - Digital calibration sign
pub fn dc(&self) -> DC_R[src]
Bits 0:4 - Digital calibration
impl R<u32, Reg<u32, _ALRMAR>>[src]
pub fn msk4(&self) -> MSK4_R[src]
Bit 31 - Alarm A date mask
pub fn wdsel(&self) -> WDSEL_R[src]
Bit 30 - Week day selection
pub fn dt(&self) -> DT_R[src]
Bits 28:29 - Date tens in BCD format.
pub fn du(&self) -> DU_R[src]
Bits 24:27 - Date units or day in BCD format.
pub fn msk3(&self) -> MSK3_R[src]
Bit 23 - Alarm A hours mask
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format.
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format.
pub fn msk2(&self) -> MSK2_R[src]
Bit 15 - Alarm A minutes mask
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format.
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format.
pub fn msk1(&self) -> MSK1_R[src]
Bit 7 - Alarm A seconds mask
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format.
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format.
impl R<u32, Reg<u32, _ALRMBR>>[src]
pub fn msk4(&self) -> MSK4_R[src]
Bit 31 - Alarm B date mask
pub fn wdsel(&self) -> WDSEL_R[src]
Bit 30 - Week day selection
pub fn dt(&self) -> DT_R[src]
Bits 28:29 - Date tens in BCD format
pub fn du(&self) -> DU_R[src]
Bits 24:27 - Date units or day in BCD format
pub fn msk3(&self) -> MSK3_R[src]
Bit 23 - Alarm B hours mask
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format
pub fn msk2(&self) -> MSK2_R[src]
Bit 15 - Alarm B minutes mask
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format
pub fn msk1(&self) -> MSK1_R[src]
Bit 7 - Alarm B seconds mask
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format
impl R<u32, Reg<u32, _SSR>>[src]
impl R<u32, Reg<u32, _TSTR>>[src]
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format.
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format.
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format.
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format.
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format.
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format.
impl R<u32, Reg<u32, _TSDR>>[src]
pub fn wdu(&self) -> WDU_R[src]
Bits 13:15 - Week day units
pub fn mt(&self) -> MT_R[src]
Bit 12 - Month tens in BCD format
pub fn mu(&self) -> MU_R[src]
Bits 8:11 - Month units in BCD format
pub fn dt(&self) -> DT_R[src]
Bits 4:5 - Date tens in BCD format
pub fn du(&self) -> DU_R[src]
Bits 0:3 - Date units in BCD format
impl R<u32, Reg<u32, _TSSSR>>[src]
impl R<u32, Reg<u32, _CALR>>[src]
pub fn calp(&self) -> CALP_R[src]
Bit 15 - Use an 8-second calibration cycle period
pub fn calw8(&self) -> CALW8_R[src]
Bit 14 - Use a 16-second calibration cycle period
pub fn calw16(&self) -> CALW16_R[src]
Bit 13 - CALW16
pub fn calm(&self) -> CALM_R[src]
Bits 0:8 - Calibration minus
impl R<u32, Reg<u32, _TAFCR>>[src]
pub fn alarmouttype(&self) -> ALARMOUTTYPE_R[src]
Bit 18 - AFO_ALARM output type
pub fn tamppudis(&self) -> TAMPPUDIS_R[src]
Bit 15 - TAMPER pull-up disable
pub fn tampprch(&self) -> TAMPPRCH_R[src]
Bits 13:14 - Tamper precharge duration
pub fn tampflt(&self) -> TAMPFLT_R[src]
Bits 11:12 - Tamper filter count
pub fn tampfreq(&self) -> TAMPFREQ_R[src]
Bits 8:10 - Tamper sampling frequency
pub fn tampts(&self) -> TAMPTS_R[src]
Bit 7 - Activate timestamp on tamper detection event
pub fn tamp3trg(&self) -> TAMP3TRG_R[src]
Bit 6 - TAMPER1 mapping
pub fn tamp3e(&self) -> TAMP3E_R[src]
Bit 5 - TIMESTAMP mapping
pub fn tamp2trg(&self) -> TAMP2TRG_R[src]
Bit 4 - Active level for tamper 2
pub fn tamp2e(&self) -> TAMP2E_R[src]
Bit 3 - Tamper 2 detection enable
pub fn tampie(&self) -> TAMPIE_R[src]
Bit 2 - Tamper interrupt enable
pub fn tamp1etrg(&self) -> TAMP1ETRG_R[src]
Bit 1 - Active level for tamper 1
pub fn tamp1e(&self) -> TAMP1E_R[src]
Bit 0 - Tamper 1 detection enable
impl R<u32, Reg<u32, _ALRMASSR>>[src]
pub fn maskss(&self) -> MASKSS_R[src]
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&self) -> SS_R[src]
Bits 0:14 - Sub seconds value
impl R<u32, Reg<u32, _ALRMBSSR>>[src]
pub fn maskss(&self) -> MASKSS_R[src]
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&self) -> SS_R[src]
Bits 0:14 - Sub seconds value
impl R<u32, Reg<u32, _BKPR>>[src]
impl R<u32, Reg<u32, _POWER>>[src]
impl R<u32, Reg<u32, _CLKCR>>[src]
pub fn hwfc_en(&self) -> HWFC_EN_R[src]
Bit 14 - HW Flow Control enable
pub fn negedge(&self) -> NEGEDGE_R[src]
Bit 13 - SDIO_CK dephasing selection bit
pub fn widbus(&self) -> WIDBUS_R[src]
Bits 11:12 - Wide bus mode enable bit
pub fn bypass(&self) -> BYPASS_R[src]
Bit 10 - Clock divider bypass enable bit
pub fn pwrsav(&self) -> PWRSAV_R[src]
Bit 9 - Power saving configuration bit
pub fn clken(&self) -> CLKEN_R[src]
Bit 8 - Clock enable bit
pub fn clkdiv(&self) -> CLKDIV_R[src]
Bits 0:7 - Clock divide factor
impl R<u32, Reg<u32, _ARG>>[src]
impl R<u32, Reg<u32, _CMD>>[src]
pub fn ce_atacmd(&self) -> CE_ATACMD_R[src]
Bit 14 - CE-ATA command
pub fn n_ien(&self) -> NIEN_R[src]
Bit 13 - not Interrupt Enable
pub fn encmdcompl(&self) -> ENCMDCOMPL_R[src]
Bit 12 - Enable CMD completion
pub fn sdiosuspend(&self) -> SDIOSUSPEND_R[src]
Bit 11 - SD I/O suspend command
pub fn cpsmen(&self) -> CPSMEN_R[src]
Bit 10 - Command path state machine (CPSM) Enable bit
pub fn waitpend(&self) -> WAITPEND_R[src]
Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).
pub fn waitint(&self) -> WAITINT_R[src]
Bit 8 - CPSM waits for interrupt request
pub fn waitresp(&self) -> WAITRESP_R[src]
Bits 6:7 - Wait for response bits
pub fn cmdindex(&self) -> CMDINDEX_R[src]
Bits 0:5 - Command index
impl R<u32, Reg<u32, _RESPCMD>>[src]
impl R<u32, Reg<u32, _RESP1>>[src]
pub fn cardstatus1(&self) -> CARDSTATUS1_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _RESP2>>[src]
pub fn cardstatus2(&self) -> CARDSTATUS2_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _RESP3>>[src]
pub fn cardstatus3(&self) -> CARDSTATUS3_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _RESP4>>[src]
pub fn cardstatus4(&self) -> CARDSTATUS4_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _DTIMER>>[src]
pub fn datatime(&self) -> DATATIME_R[src]
Bits 0:31 - Data timeout period
impl R<u32, Reg<u32, _DLEN>>[src]
pub fn datalength(&self) -> DATALENGTH_R[src]
Bits 0:24 - Data length value
impl R<u32, Reg<u32, _DCTRL>>[src]
pub fn sdioen(&self) -> SDIOEN_R[src]
Bit 11 - SD I/O enable functions
pub fn rwmod(&self) -> RWMOD_R[src]
Bit 10 - Read wait mode
pub fn rwstop(&self) -> RWSTOP_R[src]
Bit 9 - Read wait stop
pub fn rwstart(&self) -> RWSTART_R[src]
Bit 8 - Read wait start
pub fn dblocksize(&self) -> DBLOCKSIZE_R[src]
Bits 4:7 - Data block size
pub fn dmaen(&self) -> DMAEN_R[src]
Bit 3 - DMA enable bit
pub fn dtmode(&self) -> DTMODE_R[src]
Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
pub fn dtdir(&self) -> DTDIR_R[src]
Bit 1 - Data transfer direction selection
pub fn dten(&self) -> DTEN_R[src]
Bit 0 - Data transfer enabled bit
impl R<u32, Reg<u32, _DCOUNT>>[src]
pub fn datacount(&self) -> DATACOUNT_R[src]
Bits 0:24 - Data count value
impl R<u32, Reg<u32, _STA>>[src]
pub fn ceataend(&self) -> CEATAEND_R[src]
Bit 23 - CE-ATA command completion signal received for CMD61
pub fn sdioit(&self) -> SDIOIT_R[src]
Bit 22 - SDIO interrupt received
pub fn rxdavl(&self) -> RXDAVL_R[src]
Bit 21 - Data available in receive FIFO
pub fn txdavl(&self) -> TXDAVL_R[src]
Bit 20 - Data available in transmit FIFO
pub fn rxfifoe(&self) -> RXFIFOE_R[src]
Bit 19 - Receive FIFO empty
pub fn txfifoe(&self) -> TXFIFOE_R[src]
Bit 18 - Transmit FIFO empty
pub fn rxfifof(&self) -> RXFIFOF_R[src]
Bit 17 - Receive FIFO full
pub fn txfifof(&self) -> TXFIFOF_R[src]
Bit 16 - Transmit FIFO full
pub fn rxfifohf(&self) -> RXFIFOHF_R[src]
Bit 15 - Receive FIFO half full: there are at least 8 words in the FIFO
pub fn txfifohe(&self) -> TXFIFOHE_R[src]
Bit 14 - Transmit FIFO half empty: at least 8 words can be written into the FIFO
pub fn rxact(&self) -> RXACT_R[src]
Bit 13 - Data receive in progress
pub fn txact(&self) -> TXACT_R[src]
Bit 12 - Data transmit in progress
pub fn cmdact(&self) -> CMDACT_R[src]
Bit 11 - Command transfer in progress
pub fn dbckend(&self) -> DBCKEND_R[src]
Bit 10 - Data block sent/received (CRC check passed)
pub fn stbiterr(&self) -> STBITERR_R[src]
Bit 9 - Start bit not detected on all data signals in wide bus mode
pub fn dataend(&self) -> DATAEND_R[src]
Bit 8 - Data end (data counter, SDIDCOUNT, is zero)
pub fn cmdsent(&self) -> CMDSENT_R[src]
Bit 7 - Command sent (no response required)
pub fn cmdrend(&self) -> CMDREND_R[src]
Bit 6 - Command response received (CRC check passed)
pub fn rxoverr(&self) -> RXOVERR_R[src]
Bit 5 - Received FIFO overrun error
pub fn txunderr(&self) -> TXUNDERR_R[src]
Bit 4 - Transmit FIFO underrun error
pub fn dtimeout(&self) -> DTIMEOUT_R[src]
Bit 3 - Data timeout
pub fn ctimeout(&self) -> CTIMEOUT_R[src]
Bit 2 - Command response timeout
pub fn dcrcfail(&self) -> DCRCFAIL_R[src]
Bit 1 - Data block sent/received (CRC check failed)
pub fn ccrcfail(&self) -> CCRCFAIL_R[src]
Bit 0 - Command response received (CRC check failed)
impl R<u32, Reg<u32, _ICR>>[src]
pub fn ceataendc(&self) -> CEATAENDC_R[src]
Bit 23 - CEATAEND flag clear bit
pub fn sdioitc(&self) -> SDIOITC_R[src]
Bit 22 - SDIOIT flag clear bit
pub fn dbckendc(&self) -> DBCKENDC_R[src]
Bit 10 - DBCKEND flag clear bit
pub fn stbiterrc(&self) -> STBITERRC_R[src]
Bit 9 - STBITERR flag clear bit
pub fn dataendc(&self) -> DATAENDC_R[src]
Bit 8 - DATAEND flag clear bit
pub fn cmdsentc(&self) -> CMDSENTC_R[src]
Bit 7 - CMDSENT flag clear bit
pub fn cmdrendc(&self) -> CMDRENDC_R[src]
Bit 6 - CMDREND flag clear bit
pub fn rxoverrc(&self) -> RXOVERRC_R[src]
Bit 5 - RXOVERR flag clear bit
pub fn txunderrc(&self) -> TXUNDERRC_R[src]
Bit 4 - TXUNDERR flag clear bit
pub fn dtimeoutc(&self) -> DTIMEOUTC_R[src]
Bit 3 - DTIMEOUT flag clear bit
pub fn ctimeoutc(&self) -> CTIMEOUTC_R[src]
Bit 2 - CTIMEOUT flag clear bit
pub fn dcrcfailc(&self) -> DCRCFAILC_R[src]
Bit 1 - DCRCFAIL flag clear bit
pub fn ccrcfailc(&self) -> CCRCFAILC_R[src]
Bit 0 - CCRCFAIL flag clear bit
impl R<u32, Reg<u32, _MASK>>[src]
pub fn ceataendie(&self) -> CEATAENDIE_R[src]
Bit 23 - CE-ATA command completion signal received interrupt enable
pub fn sdioitie(&self) -> SDIOITIE_R[src]
Bit 22 - SDIO mode interrupt received interrupt enable
pub fn rxdavlie(&self) -> RXDAVLIE_R[src]
Bit 21 - Data available in Rx FIFO interrupt enable
pub fn txdavlie(&self) -> TXDAVLIE_R[src]
Bit 20 - Data available in Tx FIFO interrupt enable
pub fn rxfifoeie(&self) -> RXFIFOEIE_R[src]
Bit 19 - Rx FIFO empty interrupt enable
pub fn txfifoeie(&self) -> TXFIFOEIE_R[src]
Bit 18 - Tx FIFO empty interrupt enable
pub fn rxfifofie(&self) -> RXFIFOFIE_R[src]
Bit 17 - Rx FIFO full interrupt enable
pub fn txfifofie(&self) -> TXFIFOFIE_R[src]
Bit 16 - Tx FIFO full interrupt enable
pub fn rxfifohfie(&self) -> RXFIFOHFIE_R[src]
Bit 15 - Rx FIFO half full interrupt enable
pub fn txfifoheie(&self) -> TXFIFOHEIE_R[src]
Bit 14 - Tx FIFO half empty interrupt enable
pub fn rxactie(&self) -> RXACTIE_R[src]
Bit 13 - Data receive acting interrupt enable
pub fn txactie(&self) -> TXACTIE_R[src]
Bit 12 - Data transmit acting interrupt enable
pub fn cmdactie(&self) -> CMDACTIE_R[src]
Bit 11 - Command acting interrupt enable
pub fn dbckendie(&self) -> DBCKENDIE_R[src]
Bit 10 - Data block end interrupt enable
pub fn stbiterrie(&self) -> STBITERRIE_R[src]
Bit 9 - Start bit error interrupt enable
pub fn dataendie(&self) -> DATAENDIE_R[src]
Bit 8 - Data end interrupt enable
pub fn cmdsentie(&self) -> CMDSENTIE_R[src]
Bit 7 - Command sent interrupt enable
pub fn cmdrendie(&self) -> CMDRENDIE_R[src]
Bit 6 - Command response received interrupt enable
pub fn rxoverrie(&self) -> RXOVERRIE_R[src]
Bit 5 - Rx FIFO overrun error interrupt enable
pub fn txunderrie(&self) -> TXUNDERRIE_R[src]
Bit 4 - Tx FIFO underrun error interrupt enable
pub fn dtimeoutie(&self) -> DTIMEOUTIE_R[src]
Bit 3 - Data timeout interrupt enable
pub fn ctimeoutie(&self) -> CTIMEOUTIE_R[src]
Bit 2 - Command timeout interrupt enable
pub fn dcrcfailie(&self) -> DCRCFAILIE_R[src]
Bit 1 - Data CRC fail interrupt enable
pub fn ccrcfailie(&self) -> CCRCFAILIE_R[src]
Bit 0 - Command CRC fail interrupt enable
impl R<u32, Reg<u32, _FIFOCNT>>[src]
pub fn fifocount(&self) -> FIFOCOUNT_R[src]
Bits 0:23 - Remaining number of words to be written to or read from the FIFO.
impl R<u32, Reg<u32, _FIFO>>[src]
pub fn fif0data(&self) -> FIF0DATA_R[src]
Bits 0:31 - FIF0Data
impl R<u32, Reg<u32, _CR1>>[src]
pub fn bidimode(&self) -> BIDIMODE_R[src]
Bit 15 - Bidirectional data mode enable
pub fn bidioe(&self) -> BIDIOE_R[src]
Bit 14 - Output enable in bidirectional mode
pub fn crcen(&self) -> CRCEN_R[src]
Bit 13 - Hardware CRC calculation enable
pub fn crcnext(&self) -> CRCNEXT_R[src]
Bit 12 - CRC transfer next
pub fn dff(&self) -> DFF_R[src]
Bit 11 - Data frame format
pub fn rxonly(&self) -> RXONLY_R[src]
Bit 10 - Receive only
pub fn ssm(&self) -> SSM_R[src]
Bit 9 - Software slave management
pub fn ssi(&self) -> SSI_R[src]
Bit 8 - Internal slave select
pub fn lsbfirst(&self) -> LSBFIRST_R[src]
Bit 7 - Frame format
pub fn spe(&self) -> SPE_R[src]
Bit 6 - SPI enable
pub fn br(&self) -> BR_R[src]
Bits 3:5 - Baud rate control
pub fn mstr(&self) -> MSTR_R[src]
Bit 2 - Master selection
pub fn cpol(&self) -> CPOL_R[src]
Bit 1 - Clock polarity
pub fn cpha(&self) -> CPHA_R[src]
Bit 0 - Clock phase
impl R<u32, Reg<u32, _CR2>>[src]
pub fn txeie(&self) -> TXEIE_R[src]
Bit 7 - Tx buffer empty interrupt enable
pub fn rxneie(&self) -> RXNEIE_R[src]
Bit 6 - RX buffer not empty interrupt enable
pub fn errie(&self) -> ERRIE_R[src]
Bit 5 - Error interrupt enable
pub fn frf(&self) -> FRF_R[src]
Bit 4 - Frame format
pub fn ssoe(&self) -> SSOE_R[src]
Bit 2 - SS output enable
pub fn txdmaen(&self) -> TXDMAEN_R[src]
Bit 1 - Tx buffer DMA enable
pub fn rxdmaen(&self) -> RXDMAEN_R[src]
Bit 0 - Rx buffer DMA enable
impl R<u32, Reg<u32, _SR>>[src]
pub fn tifrfe(&self) -> TIFRFE_R[src]
Bit 8 - TI frame format error
pub fn bsy(&self) -> BSY_R[src]
Bit 7 - Busy flag
pub fn ovr(&self) -> OVR_R[src]
Bit 6 - Overrun flag
pub fn modf(&self) -> MODF_R[src]
Bit 5 - Mode fault
pub fn crcerr(&self) -> CRCERR_R[src]
Bit 4 - CRC error flag
pub fn udr(&self) -> UDR_R[src]
Bit 3 - Underrun flag
pub fn chside(&self) -> CHSIDE_R[src]
Bit 2 - Channel side
pub fn txe(&self) -> TXE_R[src]
Bit 1 - Transmit buffer empty
pub fn rxne(&self) -> RXNE_R[src]
Bit 0 - Receive buffer not empty
impl R<u32, Reg<u32, _DR>>[src]
impl R<u32, Reg<u32, _CRCPR>>[src]
impl R<u32, Reg<u32, _RXCRCR>>[src]
impl R<u32, Reg<u32, _TXCRCR>>[src]
impl R<u32, Reg<u32, _I2SCFGR>>[src]
pub fn i2smod(&self) -> I2SMOD_R[src]
Bit 11 - I2S mode selection
pub fn i2se(&self) -> I2SE_R[src]
Bit 10 - I2S Enable
pub fn i2scfg(&self) -> I2SCFG_R[src]
Bits 8:9 - I2S configuration mode
pub fn pcmsync(&self) -> PCMSYNC_R[src]
Bit 7 - PCM frame synchronization
pub fn i2sstd(&self) -> I2SSTD_R[src]
Bits 4:5 - I2S standard selection
pub fn ckpol(&self) -> CKPOL_R[src]
Bit 3 - Steady state clock polarity
pub fn datlen(&self) -> DATLEN_R[src]
Bits 1:2 - Data length to be transferred
pub fn chlen(&self) -> CHLEN_R[src]
Bit 0 - Channel length (number of bits per audio channel)
impl R<u32, Reg<u32, _I2SPR>>[src]
pub fn mckoe(&self) -> MCKOE_R[src]
Bit 9 - Master clock output enable
pub fn odd(&self) -> ODD_R[src]
Bit 8 - Odd factor for the prescaler
pub fn i2sdiv(&self) -> I2SDIV_R[src]
Bits 0:7 - I2S Linear prescaler
impl R<u32, Reg<u32, _MEMRMP>>[src]
pub fn mem_mode(&self) -> MEM_MODE_R[src]
Bits 0:1 - MEM_MODE
pub fn boot_mode(&self) -> BOOT_MODE_R[src]
Bits 8:9 - BOOT_MODE
impl R<u32, Reg<u32, _PMC>>[src]
pub fn usb_pu(&self) -> USB_PU_R[src]
Bit 0 - USB pull-up
pub fn lcd_capa(&self) -> LCD_CAPA_R[src]
Bits 1:5 - USB pull-up enable on DP line
impl R<u32, Reg<u32, _EXTICR1>>[src]
pub fn exti3(&self) -> EXTI3_R[src]
Bits 12:15 - EXTI x configuration (x = 0 to 3)
pub fn exti2(&self) -> EXTI2_R[src]
Bits 8:11 - EXTI x configuration (x = 0 to 3)
pub fn exti1(&self) -> EXTI1_R[src]
Bits 4:7 - EXTI x configuration (x = 0 to 3)
pub fn exti0(&self) -> EXTI0_R[src]
Bits 0:3 - EXTI x configuration (x = 0 to 3)
impl R<u32, Reg<u32, _EXTICR2>>[src]
pub fn exti7(&self) -> EXTI7_R[src]
Bits 12:15 - EXTI x configuration (x = 4 to 7)
pub fn exti6(&self) -> EXTI6_R[src]
Bits 8:11 - EXTI x configuration (x = 4 to 7)
pub fn exti5(&self) -> EXTI5_R[src]
Bits 4:7 - EXTI x configuration (x = 4 to 7)
pub fn exti4(&self) -> EXTI4_R[src]
Bits 0:3 - EXTI x configuration (x = 4 to 7)
impl R<u32, Reg<u32, _EXTICR3>>[src]
pub fn exti11(&self) -> EXTI11_R[src]
Bits 12:15 - EXTI x configuration (x = 8 to 11)
pub fn exti10(&self) -> EXTI10_R[src]
Bits 8:11 - EXTI10
pub fn exti9(&self) -> EXTI9_R[src]
Bits 4:7 - EXTI x configuration (x = 8 to 11)
pub fn exti8(&self) -> EXTI8_R[src]
Bits 0:3 - EXTI x configuration (x = 8 to 11)
impl R<u32, Reg<u32, _EXTICR4>>[src]
pub fn exti15(&self) -> EXTI15_R[src]
Bits 12:15 - EXTI x configuration (x = 12 to 15)
pub fn exti14(&self) -> EXTI14_R[src]
Bits 8:11 - EXTI14
pub fn exti13(&self) -> EXTI13_R[src]
Bits 4:7 - EXTI13
pub fn exti12(&self) -> EXTI12_R[src]
Bits 0:3 - EXTI12
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CKD_A>[src]
pub fn variant(&self) -> Variant<u8, CKD_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
impl R<u32, Reg<u32, _CR1>>[src]
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn opm(&self) -> OPM_R[src]
Bit 3 - One-pulse mode
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn ckd(&self) -> CKD_R[src]
Bits 8:9 - Clock division
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
pub fn cc1ie(&self) -> CC1IE_R[src]
Bit 1 - Capture/Compare 1 interrupt enable
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
pub fn uif(&self) -> UIF_R[src]
Bit 0 - Update interrupt flag
pub fn cc1if(&self) -> CC1IF_R[src]
Bit 1 - Capture/Compare 1 interrupt flag
pub fn cc1of(&self) -> CC1OF_R[src]
Bit 9 - Capture/compare 1 overcapture flag
impl R<u32, Reg<u32, _CCMR1_OUTPUT>>[src]
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
pub fn oc1fe(&self) -> OC1FE_R[src]
Bit 2 - Output compare 1 fast enable
pub fn oc1pe(&self) -> OC1PE_R[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1m(&self) -> OC1M_R[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1ce(&self) -> OC1CE_R[src]
Bit 7 - Output compare 1 clear enable
impl R<u32, Reg<u32, _CCMR1_INPUT>>[src]
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
pub fn ic1psc(&self) -> IC1PSC_R[src]
Bits 2:3 - Input capture 1 prescaler
pub fn ic1f(&self) -> IC1F_R[src]
Bits 4:7 - Input capture 1 filter
impl R<u32, Reg<u32, _CCER>>[src]
pub fn cc1np(&self) -> CC1NP_R[src]
Bit 3 - Capture/Compare 1 complementary output Polarity
pub fn cc1p(&self) -> CC1P_R[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&self) -> CC1E_R[src]
Bit 0 - Capture/Compare 1 output enable
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u32, Reg<u32, _CCR>>[src]
impl R<u32, Reg<u32, _OR>>[src]
pub fn ti1_rmp(&self) -> TI1_RMP_R[src]
Bits 0:1 - Timer 10 input 1 remap
pub fn etr_rmp(&self) -> ETR_RMP_R[src]
Bit 2 - Timer10 ETR remap
pub fn ti1_rmp_ri(&self) -> TI1_RMP_RI_R[src]
Bit 3 - Timer10 Input 1 remap for Routing Interface (RI)
impl R<u32, Reg<u32, _CR2>>[src]
impl R<u32, Reg<u32, _SMCR>>[src]
pub fn etf(&self) -> ETF_R[src]
Bits 8:11 - External trigger filter
pub fn etps(&self) -> ETPS_R[src]
Bits 12:13 - External trigger prescaler
pub fn ece(&self) -> ECE_R[src]
Bit 14 - External clock enable
pub fn etp(&self) -> ETP_R[src]
Bit 15 - External trigger polarity
impl R<u8, CKD_A>[src]
pub fn variant(&self) -> Variant<u8, CKD_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ckd(&self) -> CKD_R[src]
Bits 8:9 - Clock division
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
pub fn opm(&self) -> OPM_R[src]
Bit 3 - One-pulse mode
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
pub fn cc1ie(&self) -> CC1IE_R[src]
Bit 1 - Capture/Compare 1 interrupt enable
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
pub fn cc1of(&self) -> CC1OF_R[src]
Bit 9 - Capture/compare 1 overcapture flag
pub fn cc1if(&self) -> CC1IF_R[src]
Bit 1 - Capture/Compare 1 interrupt flag
pub fn uif(&self) -> UIF_R[src]
Bit 0 - Update interrupt flag
impl R<u32, Reg<u32, _CCMR1_OUTPUT>>[src]
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
pub fn oc1fe(&self) -> OC1FE_R[src]
Bit 2 - Output compare 1 fast enable
pub fn oc1pe(&self) -> OC1PE_R[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1m(&self) -> OC1M_R[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1ce(&self) -> OC1CE_R[src]
Bit 7 - Output compare 1 clear enable
impl R<u32, Reg<u32, _CCMR1_INPUT>>[src]
pub fn ic1f(&self) -> IC1F_R[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&self) -> IC1PSC_R[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u32, Reg<u32, _CCER>>[src]
pub fn cc1np(&self) -> CC1NP_R[src]
Bit 3 - Capture/Compare 1 complementary output Polarity
pub fn cc1p(&self) -> CC1P_R[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&self) -> CC1E_R[src]
Bit 0 - Capture/Compare 1 output enable
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u32, Reg<u32, _CCR>>[src]
impl R<u32, Reg<u32, _OR>>[src]
pub fn ti1_rmp(&self) -> TI1_RMP_R[src]
Bits 0:1 - TIM11 Input 1 remapping capability
pub fn etr_rmp(&self) -> ETR_RMP_R[src]
Bit 2 - Timer11 ETR remap
pub fn ti1_rmp_ri(&self) -> TI1_RMP_RI_R[src]
Bit 3 - Timer11 Input 1 remap for Routing Interface (RI)
impl R<u32, Reg<u32, _SMCR>>[src]
pub fn etf(&self) -> ETF_R[src]
Bits 8:11 - External trigger filter
pub fn etps(&self) -> ETPS_R[src]
Bits 12:13 - External trigger prescaler
pub fn ece(&self) -> ECE_R[src]
Bit 14 - External clock enable
pub fn etp(&self) -> ETP_R[src]
Bit 15 - External trigger polarity
impl R<u8, CKD_A>[src]
pub fn variant(&self) -> Variant<u8, CKD_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CMS_A>[src]
pub fn variant(&self) -> CMS_A[src]
Get enumerated values variant
pub fn is_edge_aligned(&self) -> bool[src]
Checks if the value of the field is EDGEALIGNED
pub fn is_center_aligned1(&self) -> bool[src]
Checks if the value of the field is CENTERALIGNED1
pub fn is_center_aligned2(&self) -> bool[src]
Checks if the value of the field is CENTERALIGNED2
pub fn is_center_aligned3(&self) -> bool[src]
Checks if the value of the field is CENTERALIGNED3
impl R<bool, DIR_A>[src]
pub fn variant(&self) -> DIR_A[src]
Get enumerated values variant
pub fn is_up(&self) -> bool[src]
Checks if the value of the field is UP
pub fn is_down(&self) -> bool[src]
Checks if the value of the field is DOWN
impl R<bool, OPM_A>[src]
pub fn variant(&self) -> OPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ckd(&self) -> CKD_R[src]
Bits 8:9 - Clock division
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&self) -> CMS_R[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Direction
pub fn opm(&self) -> OPM_R[src]
Bit 3 - One-pulse mode
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
impl R<bool, TI1S_A>[src]
pub fn variant(&self) -> TI1S_A[src]
Get enumerated values variant
pub fn is_normal(&self) -> bool[src]
Checks if the value of the field is NORMAL
pub fn is_xor(&self) -> bool[src]
Checks if the value of the field is XOR
impl R<u8, MMS_A>[src]
pub fn variant(&self) -> MMS_A[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
pub fn is_enable(&self) -> bool[src]
Checks if the value of the field is ENABLE
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
pub fn is_compare_pulse(&self) -> bool[src]
Checks if the value of the field is COMPAREPULSE
pub fn is_compare_oc1(&self) -> bool[src]
Checks if the value of the field is COMPAREOC1
pub fn is_compare_oc2(&self) -> bool[src]
Checks if the value of the field is COMPAREOC2
pub fn is_compare_oc3(&self) -> bool[src]
Checks if the value of the field is COMPAREOC3
pub fn is_compare_oc4(&self) -> bool[src]
Checks if the value of the field is COMPAREOC4
impl R<bool, CCDS_A>[src]
pub fn variant(&self) -> CCDS_A[src]
Get enumerated values variant
pub fn is_on_compare(&self) -> bool[src]
Checks if the value of the field is ONCOMPARE
pub fn is_on_update(&self) -> bool[src]
Checks if the value of the field is ONUPDATE
impl R<u32, Reg<u32, _CR2>>[src]
pub fn ti1s(&self) -> TI1S_R[src]
Bit 7 - TI1 selection
pub fn mms(&self) -> MMS_R[src]
Bits 4:6 - Master mode selection
pub fn ccds(&self) -> CCDS_R[src]
Bit 3 - Capture/compare DMA selection
impl R<bool, ETP_A>[src]
pub fn variant(&self) -> ETP_A[src]
Get enumerated values variant
pub fn is_not_inverted(&self) -> bool[src]
Checks if the value of the field is NOTINVERTED
pub fn is_inverted(&self) -> bool[src]
Checks if the value of the field is INVERTED
impl R<bool, ECE_A>[src]
pub fn variant(&self) -> ECE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, ETPS_A>[src]
pub fn variant(&self) -> ETPS_A[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
pub fn is_div8(&self) -> bool[src]
Checks if the value of the field is DIV8
impl R<u8, ETF_A>[src]
pub fn variant(&self) -> ETF_A[src]
Get enumerated values variant
pub fn is_no_filter(&self) -> bool[src]
Checks if the value of the field is NOFILTER
pub fn is_fck_int_n2(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N2
pub fn is_fck_int_n4(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N4
pub fn is_fck_int_n8(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N8
pub fn is_fdts_div2_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N6
pub fn is_fdts_div2_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N8
pub fn is_fdts_div4_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N6
pub fn is_fdts_div4_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N8
pub fn is_fdts_div8_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N6
pub fn is_fdts_div8_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N8
pub fn is_fdts_div16_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N5
pub fn is_fdts_div16_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N6
pub fn is_fdts_div16_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N8
pub fn is_fdts_div32_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N5
pub fn is_fdts_div32_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N6
pub fn is_fdts_div32_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N8
impl R<bool, MSM_A>[src]
pub fn variant(&self) -> MSM_A[src]
Get enumerated values variant
pub fn is_no_sync(&self) -> bool[src]
Checks if the value of the field is NOSYNC
pub fn is_sync(&self) -> bool[src]
Checks if the value of the field is SYNC
impl R<u8, TS_A>[src]
pub fn variant(&self) -> Variant<u8, TS_A>[src]
Get enumerated values variant
pub fn is_itr0(&self) -> bool[src]
Checks if the value of the field is ITR0
pub fn is_itr1(&self) -> bool[src]
Checks if the value of the field is ITR1
pub fn is_itr2(&self) -> bool[src]
Checks if the value of the field is ITR2
pub fn is_ti1f_ed(&self) -> bool[src]
Checks if the value of the field is TI1F_ED
pub fn is_ti1fp1(&self) -> bool[src]
Checks if the value of the field is TI1FP1
pub fn is_ti2fp2(&self) -> bool[src]
Checks if the value of the field is TI2FP2
pub fn is_etrf(&self) -> bool[src]
Checks if the value of the field is ETRF
impl R<u8, SMS_A>[src]
pub fn variant(&self) -> SMS_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_encoder_mode_1(&self) -> bool[src]
Checks if the value of the field is ENCODER_MODE_1
pub fn is_encoder_mode_2(&self) -> bool[src]
Checks if the value of the field is ENCODER_MODE_2
pub fn is_encoder_mode_3(&self) -> bool[src]
Checks if the value of the field is ENCODER_MODE_3
pub fn is_reset_mode(&self) -> bool[src]
Checks if the value of the field is RESET_MODE
pub fn is_gated_mode(&self) -> bool[src]
Checks if the value of the field is GATED_MODE
pub fn is_trigger_mode(&self) -> bool[src]
Checks if the value of the field is TRIGGER_MODE
pub fn is_ext_clock_mode(&self) -> bool[src]
Checks if the value of the field is EXT_CLOCK_MODE
impl R<u32, Reg<u32, _SMCR>>[src]
pub fn etp(&self) -> ETP_R[src]
Bit 15 - External trigger polarity
pub fn ece(&self) -> ECE_R[src]
Bit 14 - External clock enable
pub fn etps(&self) -> ETPS_R[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&self) -> ETF_R[src]
Bits 8:11 - External trigger filter
pub fn msm(&self) -> MSM_R[src]
Bit 7 - Master/Slave mode
pub fn ts(&self) -> TS_R[src]
Bits 4:6 - Trigger selection
pub fn occs(&self) -> OCCS_R[src]
Bit 3 - OCREF clear selection
pub fn sms(&self) -> SMS_R[src]
Bits 0:2 - Slave mode selection
impl R<bool, TDE_A>[src]
pub fn variant(&self) -> TDE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC4DE_A>[src]
pub fn variant(&self) -> CC4DE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, UDE_A>[src]
pub fn variant(&self) -> UDE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, TIE_A>[src]
pub fn variant(&self) -> TIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC4IE_A>[src]
pub fn variant(&self) -> CC4IE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn tde(&self) -> TDE_R[src]
Bit 14 - Trigger DMA request enable
pub fn cc4de(&self) -> CC4DE_R[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&self) -> CC3DE_R[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&self) -> CC2DE_R[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&self) -> CC1DE_R[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&self) -> UDE_R[src]
Bit 8 - Update DMA request enable
pub fn tie(&self) -> TIE_R[src]
Bit 6 - Trigger interrupt enable
pub fn cc4ie(&self) -> CC4IE_R[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&self) -> CC3IE_R[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&self) -> CC2IE_R[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&self) -> CC1IE_R[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
impl R<bool, CC4OF_A>[src]
pub fn variant(&self) -> Variant<bool, CC4OF_A>[src]
Get enumerated values variant
pub fn is_overcapture(&self) -> bool[src]
Checks if the value of the field is OVERCAPTURE
impl R<bool, TIF_A>[src]
pub fn variant(&self) -> TIF_A[src]
Get enumerated values variant
pub fn is_no_trigger(&self) -> bool[src]
Checks if the value of the field is NOTRIGGER
pub fn is_trigger(&self) -> bool[src]
Checks if the value of the field is TRIGGER
impl R<bool, CC4IF_A>[src]
pub fn variant(&self) -> Variant<bool, CC4IF_A>[src]
Get enumerated values variant
pub fn is_match_(&self) -> bool[src]
Checks if the value of the field is MATCH
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
pub fn cc4of(&self) -> CC4OF_R[src]
Bit 12 - Capture/compare 1 overcapture flag
pub fn cc3of(&self) -> CC3OF_R[src]
Bit 11 - Capture/compare 3 overcapture flag
pub fn cc2of(&self) -> CC2OF_R[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&self) -> CC1OF_R[src]
Bit 9 - Capture/compare 1 overcapture flag
pub fn tif(&self) -> TIF_R[src]
Bit 6 - Trigger interrupt flag
pub fn cc4if(&self) -> CC4IF_R[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&self) -> CC3IF_R[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&self) -> CC2IF_R[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&self) -> CC1IF_R[src]
Bit 1 - Capture/Compare 1 interrupt flag
pub fn uif(&self) -> UIF_R[src]
Bit 0 - Update interrupt flag
impl R<bool, TG_A>[src]
pub fn variant(&self) -> Variant<bool, TG_A>[src]
Get enumerated values variant
pub fn is_trigger(&self) -> bool[src]
Checks if the value of the field is TRIGGER
impl R<bool, CC4G_A>[src]
pub fn variant(&self) -> Variant<bool, CC4G_A>[src]
Get enumerated values variant
pub fn is_trigger(&self) -> bool[src]
Checks if the value of the field is TRIGGER
impl R<bool, UG_A>[src]
pub fn variant(&self) -> Variant<bool, UG_A>[src]
Get enumerated values variant
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
impl R<u32, Reg<u32, _EGR>>[src]
pub fn tg(&self) -> TG_R[src]
Bit 6 - Trigger generation
pub fn cc4g(&self) -> CC4G_R[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&self) -> CC3G_R[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&self) -> CC2G_R[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&self) -> CC1G_R[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&self) -> UG_R[src]
Bit 0 - Update generation
impl R<u8, OC2M_A>[src]
pub fn variant(&self) -> OC2M_A[src]
Get enumerated values variant
pub fn is_frozen(&self) -> bool[src]
Checks if the value of the field is FROZEN
pub fn is_active_on_match(&self) -> bool[src]
Checks if the value of the field is ACTIVEONMATCH
pub fn is_inactive_on_match(&self) -> bool[src]
Checks if the value of the field is INACTIVEONMATCH
pub fn is_toggle(&self) -> bool[src]
Checks if the value of the field is TOGGLE
pub fn is_force_inactive(&self) -> bool[src]
Checks if the value of the field is FORCEINACTIVE
pub fn is_force_active(&self) -> bool[src]
Checks if the value of the field is FORCEACTIVE
pub fn is_pwm_mode1(&self) -> bool[src]
Checks if the value of the field is PWMMODE1
pub fn is_pwm_mode2(&self) -> bool[src]
Checks if the value of the field is PWMMODE2
impl R<bool, OC2PE_A>[src]
pub fn variant(&self) -> OC2PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC2S_A>[src]
pub fn variant(&self) -> Variant<bool, CC2S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<bool, OC1PE_A>[src]
pub fn variant(&self) -> OC1PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CC1S_A>[src]
pub fn variant(&self) -> Variant<u8, CC1S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<u32, Reg<u32, _CCMR1_OUTPUT>>[src]
pub fn oc2ce(&self) -> OC2CE_R[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&self) -> OC2M_R[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&self) -> OC2PE_R[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&self) -> OC2FE_R[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&self) -> CC2S_R[src]
Bit 8 - Capture/Compare 2 selection
pub fn oc1ce(&self) -> OC1CE_R[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&self) -> OC1M_R[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&self) -> OC1PE_R[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&self) -> OC1FE_R[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u8, CC2S_A>[src]
pub fn variant(&self) -> Variant<u8, CC2S_A>[src]
Get enumerated values variant
pub fn is_ti2(&self) -> bool[src]
Checks if the value of the field is TI2
pub fn is_ti1(&self) -> bool[src]
Checks if the value of the field is TI1
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u8, IC1F_A>[src]
pub fn variant(&self) -> IC1F_A[src]
Get enumerated values variant
pub fn is_no_filter(&self) -> bool[src]
Checks if the value of the field is NOFILTER
pub fn is_fck_int_n2(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N2
pub fn is_fck_int_n4(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N4
pub fn is_fck_int_n8(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N8
pub fn is_fdts_div2_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N6
pub fn is_fdts_div2_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N8
pub fn is_fdts_div4_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N6
pub fn is_fdts_div4_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N8
pub fn is_fdts_div8_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N6
pub fn is_fdts_div8_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N8
pub fn is_fdts_div16_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N5
pub fn is_fdts_div16_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N6
pub fn is_fdts_div16_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N8
pub fn is_fdts_div32_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N5
pub fn is_fdts_div32_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N6
pub fn is_fdts_div32_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N8
impl R<u8, CC1S_A>[src]
pub fn variant(&self) -> Variant<u8, CC1S_A>[src]
Get enumerated values variant
pub fn is_ti1(&self) -> bool[src]
Checks if the value of the field is TI1
pub fn is_ti2(&self) -> bool[src]
Checks if the value of the field is TI2
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u32, Reg<u32, _CCMR1_INPUT>>[src]
pub fn ic2f(&self) -> IC2F_R[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&self) -> IC2PSC_R[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&self) -> CC2S_R[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&self) -> IC1F_R[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&self) -> IC1PSC_R[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u8, OC4M_A>[src]
pub fn variant(&self) -> OC4M_A[src]
Get enumerated values variant
pub fn is_frozen(&self) -> bool[src]
Checks if the value of the field is FROZEN
pub fn is_active_on_match(&self) -> bool[src]
Checks if the value of the field is ACTIVEONMATCH
pub fn is_inactive_on_match(&self) -> bool[src]
Checks if the value of the field is INACTIVEONMATCH
pub fn is_toggle(&self) -> bool[src]
Checks if the value of the field is TOGGLE
pub fn is_force_inactive(&self) -> bool[src]
Checks if the value of the field is FORCEINACTIVE
pub fn is_force_active(&self) -> bool[src]
Checks if the value of the field is FORCEACTIVE
pub fn is_pwm_mode1(&self) -> bool[src]
Checks if the value of the field is PWMMODE1
pub fn is_pwm_mode2(&self) -> bool[src]
Checks if the value of the field is PWMMODE2
impl R<bool, OC4PE_A>[src]
pub fn variant(&self) -> OC4PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC4S_A>[src]
pub fn variant(&self) -> Variant<bool, CC4S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<bool, OC3PE_A>[src]
pub fn variant(&self) -> OC3PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CC3S_A>[src]
pub fn variant(&self) -> Variant<u8, CC3S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<u32, Reg<u32, _CCMR2_OUTPUT>>[src]
pub fn oc4ce(&self) -> OC4CE_R[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&self) -> OC4M_R[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&self) -> OC4PE_R[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&self) -> OC4FE_R[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&self) -> CC4S_R[src]
Bit 8 - Capture/Compare 4 selection
pub fn oc3ce(&self) -> OC3CE_R[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&self) -> OC3M_R[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&self) -> OC3PE_R[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&self) -> OC3FE_R[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&self) -> CC3S_R[src]
Bits 0:1 - Capture/Compare 3 selection
impl R<u8, CC4S_A>[src]
pub fn variant(&self) -> Variant<u8, CC4S_A>[src]
Get enumerated values variant
pub fn is_ti4(&self) -> bool[src]
Checks if the value of the field is TI4
pub fn is_ti3(&self) -> bool[src]
Checks if the value of the field is TI3
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u8, CC3S_A>[src]
pub fn variant(&self) -> Variant<u8, CC3S_A>[src]
Get enumerated values variant
pub fn is_ti3(&self) -> bool[src]
Checks if the value of the field is TI3
pub fn is_ti4(&self) -> bool[src]
Checks if the value of the field is TI4
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u32, Reg<u32, _CCMR2_INPUT>>[src]
pub fn ic4f(&self) -> IC4F_R[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&self) -> IC4PSC_R[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&self) -> CC4S_R[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&self) -> IC3F_R[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&self) -> IC3PSC_R[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&self) -> CC3S_R[src]
Bits 0:1 - Capture/compare 3 selection
impl R<u32, Reg<u32, _CCER>>[src]
pub fn cc4np(&self) -> CC4NP_R[src]
Bit 15 - Capture/Compare 4 output Polarity
pub fn cc4p(&self) -> CC4P_R[src]
Bit 13 - Capture/Compare 4 output Polarity
pub fn cc4e(&self) -> CC4E_R[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&self) -> CC3NP_R[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3p(&self) -> CC3P_R[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&self) -> CC3E_R[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&self) -> CC2NP_R[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&self) -> CC2P_R[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&self) -> CC2E_R[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&self) -> CC1NP_R[src]
Bit 3 - Capture/Compare 1 complementary output Polarity
pub fn cc1p(&self) -> CC1P_R[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&self) -> CC1E_R[src]
Bit 0 - Capture/Compare 1 output enable
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u32, Reg<u32, _CCR>>[src]
impl R<u32, Reg<u32, _DCR>>[src]
pub fn dbl(&self) -> DBL_R[src]
Bits 8:12 - DMA burst length
pub fn dba(&self) -> DBA_R[src]
Bits 0:4 - DMA base address
impl R<u32, Reg<u32, _DMAR>>[src]
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, OPM_A>[src]
pub fn variant(&self) -> OPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&self) -> OPM_R[src]
Bit 3 - One-pulse mode
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
impl R<u8, MMS_A>[src]
pub fn variant(&self) -> Variant<u8, MMS_A>[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
pub fn is_enable(&self) -> bool[src]
Checks if the value of the field is ENABLE
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
impl R<u32, Reg<u32, _CR2>>[src]
impl R<bool, UDE_A>[src]
pub fn variant(&self) -> UDE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn ude(&self) -> UDE_R[src]
Bit 8 - Update DMA request enable
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
pub fn psc(&self) -> PSC_R[src]
Bits 0:15 - Prescaler valueThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u8, CKD_A>[src]
pub fn variant(&self) -> Variant<u8, CKD_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, OPM_A>[src]
pub fn variant(&self) -> OPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ckd(&self) -> CKD_R[src]
Bits 8:9 - Clock division
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&self) -> OPM_R[src]
Bit 3 - One-pulse mode
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
impl R<u32, Reg<u32, _CR2>>[src]
impl R<u32, Reg<u32, _SMCR>>[src]
pub fn msm(&self) -> MSM_R[src]
Bit 7 - Master/Slave mode
pub fn ts(&self) -> TS_R[src]
Bits 4:6 - Trigger selection
pub fn sms(&self) -> SMS_R[src]
Bits 0:2 - Slave mode selection
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn tie(&self) -> TIE_R[src]
Bit 6 - Trigger interrupt enable
pub fn cc2ie(&self) -> CC2IE_R[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&self) -> CC1IE_R[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
pub fn cc2of(&self) -> CC2OF_R[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&self) -> CC1OF_R[src]
Bit 9 - Capture/compare 1 overcapture flag
pub fn tif(&self) -> TIF_R[src]
Bit 6 - Trigger interrupt flag
pub fn cc2if(&self) -> CC2IF_R[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&self) -> CC1IF_R[src]
Bit 1 - Capture/Compare 1 interrupt flag
pub fn uif(&self) -> UIF_R[src]
Bit 0 - Update interrupt flag
impl R<bool, UG_A>[src]
pub fn variant(&self) -> Variant<bool, UG_A>[src]
Get enumerated values variant
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
impl R<u32, Reg<u32, _EGR>>[src]
pub fn tg(&self) -> TG_R[src]
Bit 6 - Trigger generation
pub fn cc2g(&self) -> CC2G_R[src]
Bit 2 - Capture/Compare 2 generation
pub fn cc1g(&self) -> CC1G_R[src]
Bit 1 - Capture/Compare 1 generation
pub fn ug(&self) -> UG_R[src]
Bit 0 - Update generation
impl R<u32, Reg<u32, _CCMR1_OUTPUT>>[src]
pub fn oc2ce(&self) -> OC2CE_R[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&self) -> OC2M_R[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&self) -> OC2PE_R[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&self) -> OC2FE_R[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&self) -> CC2S_R[src]
Bit 8 - Capture/Compare 2 selection
pub fn oc1ce(&self) -> OC1CE_R[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&self) -> OC1M_R[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&self) -> OC1PE_R[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&self) -> OC1FE_R[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u32, Reg<u32, _CCMR1_INPUT>>[src]
pub fn ic2f(&self) -> IC2F_R[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&self) -> IC2PSC_R[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&self) -> CC2S_R[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&self) -> IC1F_R[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&self) -> IC1PSC_R[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u32, Reg<u32, _CCR>>[src]
impl R<u32, Reg<u32, _OR>>[src]
impl R<u32, Reg<u32, _SR>>[src]
pub fn cts(&self) -> CTS_R[src]
Bit 9 - CTS flag
pub fn lbd(&self) -> LBD_R[src]
Bit 8 - LIN break detection flag
pub fn txe(&self) -> TXE_R[src]
Bit 7 - Transmit data register empty
pub fn tc(&self) -> TC_R[src]
Bit 6 - Transmission complete
pub fn rxne(&self) -> RXNE_R[src]
Bit 5 - Read data register not empty
pub fn idle(&self) -> IDLE_R[src]
Bit 4 - IDLE line detected
pub fn ore(&self) -> ORE_R[src]
Bit 3 - Overrun error
pub fn nf(&self) -> NF_R[src]
Bit 2 - Noise detected flag
pub fn fe(&self) -> FE_R[src]
Bit 1 - Framing error
pub fn pe(&self) -> PE_R[src]
Bit 0 - Parity error
impl R<u32, Reg<u32, _DR>>[src]
impl R<u32, Reg<u32, _BRR>>[src]
pub fn div_mantissa(&self) -> DIV_MANTISSA_R[src]
Bits 4:15 - mantissa of USARTDIV
pub fn div_fraction(&self) -> DIV_FRACTION_R[src]
Bits 0:3 - fraction of USARTDIV
impl R<u32, Reg<u32, _CR1>>[src]
pub fn over8(&self) -> OVER8_R[src]
Bit 15 - Oversampling mode
pub fn ue(&self) -> UE_R[src]
Bit 13 - USART enable
pub fn m(&self) -> M_R[src]
Bit 12 - Word length
pub fn wake(&self) -> WAKE_R[src]
Bit 11 - Wakeup method
pub fn pce(&self) -> PCE_R[src]
Bit 10 - Parity control enable
pub fn ps(&self) -> PS_R[src]
Bit 9 - Parity selection
pub fn peie(&self) -> PEIE_R[src]
Bit 8 - PE interrupt enable
pub fn txeie(&self) -> TXEIE_R[src]
Bit 7 - TXE interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 6 - Transmission complete interrupt enable
pub fn rxneie(&self) -> RXNEIE_R[src]
Bit 5 - RXNE interrupt enable
pub fn idleie(&self) -> IDLEIE_R[src]
Bit 4 - IDLE interrupt enable
pub fn te(&self) -> TE_R[src]
Bit 3 - Transmitter enable
pub fn re(&self) -> RE_R[src]
Bit 2 - Receiver enable
pub fn rwu(&self) -> RWU_R[src]
Bit 1 - Receiver wakeup
pub fn sbk(&self) -> SBK_R[src]
Bit 0 - Send break
impl R<u32, Reg<u32, _CR2>>[src]
pub fn linen(&self) -> LINEN_R[src]
Bit 14 - LIN mode enable
pub fn stop(&self) -> STOP_R[src]
Bits 12:13 - STOP bits
pub fn clken(&self) -> CLKEN_R[src]
Bit 11 - Clock enable
pub fn cpol(&self) -> CPOL_R[src]
Bit 10 - Clock polarity
pub fn cpha(&self) -> CPHA_R[src]
Bit 9 - Clock phase
pub fn lbcl(&self) -> LBCL_R[src]
Bit 8 - Last bit clock pulse
pub fn lbdie(&self) -> LBDIE_R[src]
Bit 6 - LIN break detection interrupt enable
pub fn lbdl(&self) -> LBDL_R[src]
Bit 5 - lin break detection length
pub fn add(&self) -> ADD_R[src]
Bits 0:3 - Address of the USART node
impl R<u32, Reg<u32, _CR3>>[src]
pub fn onebit(&self) -> ONEBIT_R[src]
Bit 11 - One sample bit method enable
pub fn ctsie(&self) -> CTSIE_R[src]
Bit 10 - CTS interrupt enable
pub fn ctse(&self) -> CTSE_R[src]
Bit 9 - CTS enable
pub fn rtse(&self) -> RTSE_R[src]
Bit 8 - RTS enable
pub fn dmat(&self) -> DMAT_R[src]
Bit 7 - DMA enable transmitter
pub fn dmar(&self) -> DMAR_R[src]
Bit 6 - DMA enable receiver
pub fn scen(&self) -> SCEN_R[src]
Bit 5 - Smartcard mode enable
pub fn nack(&self) -> NACK_R[src]
Bit 4 - Smartcard NACK enable
pub fn hdsel(&self) -> HDSEL_R[src]
Bit 3 - Half-duplex selection
pub fn irlp(&self) -> IRLP_R[src]
Bit 2 - IrDA low-power
pub fn iren(&self) -> IREN_R[src]
Bit 1 - IrDA mode enable
pub fn eie(&self) -> EIE_R[src]
Bit 0 - Error interrupt enable
impl R<u32, Reg<u32, _GTPR>>[src]
pub fn gt(&self) -> GT_R[src]
Bits 8:15 - Guard time value
pub fn psc(&self) -> PSC_R[src]
Bits 0:7 - Prescaler value
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP0R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP1R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP2R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP3R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP4R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP5R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP6R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP7R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<bool, FRES_A>[src]
pub fn variant(&self) -> FRES_A[src]
Get enumerated values variant
pub fn is_no_reset(&self) -> bool[src]
Checks if the value of the field is NORESET
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<bool, PDWN_A>[src]
pub fn variant(&self) -> PDWN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, LPMODE_A>[src]
pub fn variant(&self) -> LPMODE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, FSUSP_A>[src]
pub fn variant(&self) -> FSUSP_A[src]
Get enumerated values variant
pub fn is_no_effect(&self) -> bool[src]
Checks if the value of the field is NOEFFECT
pub fn is_suspend(&self) -> bool[src]
Checks if the value of the field is SUSPEND
impl R<bool, RESUME_A>[src]
pub fn variant(&self) -> Variant<bool, RESUME_A>[src]
Get enumerated values variant
pub fn is_requested(&self) -> bool[src]
Checks if the value of the field is REQUESTED
impl R<bool, ESOFM_A>[src]
pub fn variant(&self) -> ESOFM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, SOFM_A>[src]
pub fn variant(&self) -> SOFM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, RESETM_A>[src]
pub fn variant(&self) -> RESETM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, SUSPM_A>[src]
pub fn variant(&self) -> SUSPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WKUPM_A>[src]
pub fn variant(&self) -> WKUPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ERRM_A>[src]
pub fn variant(&self) -> ERRM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, PMAOVRM_A>[src]
pub fn variant(&self) -> PMAOVRM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CTRM_A>[src]
pub fn variant(&self) -> CTRM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CNTR>>[src]
pub fn fres(&self) -> FRES_R[src]
Bit 0 - Force USB Reset
pub fn pdwn(&self) -> PDWN_R[src]
Bit 1 - Power down
pub fn lpmode(&self) -> LPMODE_R[src]
Bit 2 - Low-power mode
pub fn fsusp(&self) -> FSUSP_R[src]
Bit 3 - Force suspend
pub fn resume(&self) -> RESUME_R[src]
Bit 4 - Resume request
pub fn esofm(&self) -> ESOFM_R[src]
Bit 8 - Expected start of frame interrupt mask
pub fn sofm(&self) -> SOFM_R[src]
Bit 9 - Start of frame interrupt mask
pub fn resetm(&self) -> RESETM_R[src]
Bit 10 - USB reset interrupt mask
pub fn suspm(&self) -> SUSPM_R[src]
Bit 11 - Suspend mode interrupt mask
pub fn wkupm(&self) -> WKUPM_R[src]
Bit 12 - Wakeup interrupt mask
pub fn errm(&self) -> ERRM_R[src]
Bit 13 - Error interrupt mask
pub fn pmaovrm(&self) -> PMAOVRM_R[src]
Bit 14 - Packet memory area over / underrun interrupt mask
pub fn ctrm(&self) -> CTRM_R[src]
Bit 15 - Correct transfer interrupt mask
impl R<bool, DIR_A>[src]
pub fn variant(&self) -> DIR_A[src]
Get enumerated values variant
pub fn is_to(&self) -> bool[src]
Checks if the value of the field is TO
pub fn is_from(&self) -> bool[src]
Checks if the value of the field is FROM
impl R<bool, ESOF_A>[src]
pub fn variant(&self) -> Variant<bool, ESOF_A>[src]
Get enumerated values variant
pub fn is_expected_start_of_frame(&self) -> bool[src]
Checks if the value of the field is EXPECTEDSTARTOFFRAME
impl R<bool, SOF_A>[src]
pub fn variant(&self) -> Variant<bool, SOF_A>[src]
Get enumerated values variant
pub fn is_start_of_frame(&self) -> bool[src]
Checks if the value of the field is STARTOFFRAME
impl R<bool, RESET_A>[src]
pub fn variant(&self) -> Variant<bool, RESET_A>[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<bool, SUSP_A>[src]
pub fn variant(&self) -> Variant<bool, SUSP_A>[src]
Get enumerated values variant
pub fn is_suspend(&self) -> bool[src]
Checks if the value of the field is SUSPEND
impl R<bool, WKUP_A>[src]
pub fn variant(&self) -> Variant<bool, WKUP_A>[src]
Get enumerated values variant
pub fn is_wakeup(&self) -> bool[src]
Checks if the value of the field is WAKEUP
impl R<bool, ERR_A>[src]
pub fn variant(&self) -> Variant<bool, ERR_A>[src]
Get enumerated values variant
pub fn is_error(&self) -> bool[src]
Checks if the value of the field is ERROR
impl R<bool, PMAOVR_A>[src]
pub fn variant(&self) -> Variant<bool, PMAOVR_A>[src]
Get enumerated values variant
pub fn is_overrun(&self) -> bool[src]
Checks if the value of the field is OVERRUN
impl R<bool, CTR_A>[src]
pub fn variant(&self) -> Variant<bool, CTR_A>[src]
Get enumerated values variant
pub fn is_completed(&self) -> bool[src]
Checks if the value of the field is COMPLETED
impl R<u32, Reg<u32, _ISTR>>[src]
pub fn ep_id(&self) -> EP_ID_R[src]
Bits 0:3 - Endpoint Identifier
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Direction of transaction
pub fn esof(&self) -> ESOF_R[src]
Bit 8 - Expected start frame
pub fn sof(&self) -> SOF_R[src]
Bit 9 - start of frame
pub fn reset(&self) -> RESET_R[src]
Bit 10 - reset request
pub fn susp(&self) -> SUSP_R[src]
Bit 11 - Suspend mode request
pub fn wkup(&self) -> WKUP_R[src]
Bit 12 - Wakeup
pub fn err(&self) -> ERR_R[src]
Bit 13 - Error
pub fn pmaovr(&self) -> PMAOVR_R[src]
Bit 14 - Packet memory area over / underrun
pub fn ctr(&self) -> CTR_R[src]
Bit 15 - Correct transfer
impl R<bool, LCK_A>[src]
pub fn variant(&self) -> Variant<bool, LCK_A>[src]
Get enumerated values variant
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, RXDM_A>[src]
pub fn variant(&self) -> Variant<bool, RXDM_A>[src]
Get enumerated values variant
pub fn is_received(&self) -> bool[src]
Checks if the value of the field is RECEIVED
impl R<bool, RXDP_A>[src]
pub fn variant(&self) -> Variant<bool, RXDP_A>[src]
Get enumerated values variant
pub fn is_received(&self) -> bool[src]
Checks if the value of the field is RECEIVED
impl R<u32, Reg<u32, _FNR>>[src]
pub fn fn_(&self) -> FN_R[src]
Bits 0:10 - Frame number
pub fn lsof(&self) -> LSOF_R[src]
Bits 11:12 - Lost SOF
pub fn lck(&self) -> LCK_R[src]
Bit 13 - Locked
pub fn rxdm(&self) -> RXDM_R[src]
Bit 14 - Receive data - line status
pub fn rxdp(&self) -> RXDP_R[src]
Bit 15 - Receive data + line status
impl R<bool, EF_A>[src]
pub fn variant(&self) -> EF_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DADDR>>[src]
pub fn add(&self) -> ADD_R[src]
Bits 0:6 - Device address
pub fn ef(&self) -> EF_R[src]
Bit 7 - Enable function
impl R<u32, Reg<u32, _BTABLE>>[src]
impl R<u32, Reg<u32, _CR>>[src]
impl R<u8, WDGTB_A>[src]
pub fn variant(&self) -> WDGTB_A[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
pub fn is_div8(&self) -> bool[src]
Checks if the value of the field is DIV8
impl R<u32, Reg<u32, _CFR>>[src]
pub fn w(&self) -> W_R[src]
Bits 0:6 - 7-bit window value
pub fn wdgtb(&self) -> WDGTB_R[src]
Bits 7:8 - Timer base
impl R<bool, EWIF_A>[src]
pub fn variant(&self) -> EWIF_A[src]
Get enumerated values variant
pub fn is_pending(&self) -> bool[src]
Checks if the value of the field is PENDING
pub fn is_finished(&self) -> bool[src]
Checks if the value of the field is FINISHED
impl R<u32, Reg<u32, _SR>>[src]
impl R<u32, Reg<u32, _SR>>[src]
pub fn jcnr(&self) -> JCNR_R[src]
Bit 9 - Injected channel not ready
pub fn rcnr(&self) -> RCNR_R[src]
Bit 8 - Regular channel not ready
pub fn adons(&self) -> ADONS_R[src]
Bit 6 - ADC ON status
pub fn ovr(&self) -> OVR_R[src]
Bit 5 - Overrun
pub fn strt(&self) -> STRT_R[src]
Bit 4 - Regular channel start flag
pub fn jstrt(&self) -> JSTRT_R[src]
Bit 3 - Injected channel start flag
pub fn jeoc(&self) -> JEOC_R[src]
Bit 2 - Injected channel end of conversion
pub fn eoc(&self) -> EOC_R[src]
Bit 1 - Regular channel end of conversion
pub fn awd(&self) -> AWD_R[src]
Bit 0 - Analog watchdog flag
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ovrie(&self) -> OVRIE_R[src]
Bit 26 - Overrun interrupt enable
pub fn res(&self) -> RES_R[src]
Bits 24:25 - Resolution
pub fn awden(&self) -> AWDEN_R[src]
Bit 23 - Analog watchdog enable on regular channels
pub fn jawden(&self) -> JAWDEN_R[src]
Bit 22 - Analog watchdog enable on injected channels
pub fn pdi(&self) -> PDI_R[src]
Bit 17 - Power down during the idle phase
pub fn pdd(&self) -> PDD_R[src]
Bit 16 - Power down during the delay phase
pub fn discnum(&self) -> DISCNUM_R[src]
Bits 13:15 - Discontinuous mode channel count
pub fn jdiscen(&self) -> JDISCEN_R[src]
Bit 12 - Discontinuous mode on injected channels
pub fn discen(&self) -> DISCEN_R[src]
Bit 11 - Discontinuous mode on regular channels
pub fn jauto(&self) -> JAUTO_R[src]
Bit 10 - Automatic injected group conversion
pub fn awdsgl(&self) -> AWDSGL_R[src]
Bit 9 - Enable the watchdog on a single channel in scan mode
pub fn scan(&self) -> SCAN_R[src]
Bit 8 - Scan mode
pub fn jeocie(&self) -> JEOCIE_R[src]
Bit 7 - Interrupt enable for injected channels
pub fn awdie(&self) -> AWDIE_R[src]
Bit 6 - Analog watchdog interrupt enable
pub fn eocie(&self) -> EOCIE_R[src]
Bit 5 - Interrupt enable for EOC
pub fn awdch(&self) -> AWDCH_R[src]
Bits 0:4 - Analog watchdog channel select bits
impl R<u32, Reg<u32, _CR2>>[src]
pub fn swstart(&self) -> SWSTART_R[src]
Bit 30 - Start conversion of regular channels
pub fn exten(&self) -> EXTEN_R[src]
Bits 28:29 - External trigger enable for regular channels
pub fn extsel(&self) -> EXTSEL_R[src]
Bits 24:27 - External event select for regular group
pub fn jswstart(&self) -> JSWSTART_R[src]
Bit 22 - Start conversion of injected channels
pub fn jexten(&self) -> JEXTEN_R[src]
Bits 20:21 - External trigger enable for injected channels
pub fn jextsel(&self) -> JEXTSEL_R[src]
Bits 16:19 - External event select for injected group
pub fn align(&self) -> ALIGN_R[src]
Bit 11 - Data alignment
pub fn eocs(&self) -> EOCS_R[src]
Bit 10 - End of conversion selection
pub fn dds(&self) -> DDS_R[src]
Bit 9 - DMA disable selection
pub fn dma(&self) -> DMA_R[src]
Bit 8 - Direct memory access mode
pub fn dels(&self) -> DELS_R[src]
Bits 4:6 - Delay selection
pub fn adc_cfg(&self) -> ADC_CFG_R[src]
Bit 2 - ADC configuration
pub fn cont(&self) -> CONT_R[src]
Bit 1 - Continuous conversion
pub fn adon(&self) -> ADON_R[src]
Bit 0 - A/D Converter ON / OFF
impl R<u32, Reg<u32, _SMPR1>>[src]
impl R<u32, Reg<u32, _SMPR2>>[src]
impl R<u32, Reg<u32, _SMPR3>>[src]
impl R<u32, Reg<u32, _JOFR1>>[src]
pub fn joffset1(&self) -> JOFFSET1_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _JOFR2>>[src]
pub fn joffset2(&self) -> JOFFSET2_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _JOFR3>>[src]
pub fn joffset3(&self) -> JOFFSET3_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _JOFR4>>[src]
pub fn joffset4(&self) -> JOFFSET4_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _HTR>>[src]
impl R<u32, Reg<u32, _LTR>>[src]
impl R<u32, Reg<u32, _SQR1>>[src]
pub fn l(&self) -> L_R[src]
Bits 20:23 - Regular channel sequence length
pub fn sq28(&self) -> SQ28_R[src]
Bits 15:19 - 28th conversion in regular sequence
pub fn sq27(&self) -> SQ27_R[src]
Bits 10:14 - 27th conversion in regular sequence
pub fn sq26(&self) -> SQ26_R[src]
Bits 5:9 - 26th conversion in regular sequence
pub fn sq25(&self) -> SQ25_R[src]
Bits 0:4 - 25th conversion in regular sequence
impl R<u32, Reg<u32, _SQR2>>[src]
pub fn sq24(&self) -> SQ24_R[src]
Bits 25:29 - 24th conversion in regular sequence
pub fn sq23(&self) -> SQ23_R[src]
Bits 20:24 - 23rd conversion in regular sequence
pub fn sq22(&self) -> SQ22_R[src]
Bits 15:19 - 22nd conversion in regular sequence
pub fn sq21(&self) -> SQ21_R[src]
Bits 10:14 - 21st conversion in regular sequence
pub fn sq20(&self) -> SQ20_R[src]
Bits 5:9 - 20th conversion in regular sequence
pub fn sq19(&self) -> SQ19_R[src]
Bits 0:4 - 19th conversion in regular sequence
impl R<u32, Reg<u32, _SQR3>>[src]
pub fn sq18(&self) -> SQ18_R[src]
Bits 25:29 - 18th conversion in regular sequence
pub fn sq17(&self) -> SQ17_R[src]
Bits 20:24 - 17th conversion in regular sequence
pub fn sq16(&self) -> SQ16_R[src]
Bits 15:19 - 16th conversion in regular sequence
pub fn sq15(&self) -> SQ15_R[src]
Bits 10:14 - 15th conversion in regular sequence
pub fn sq14(&self) -> SQ14_R[src]
Bits 5:9 - 14th conversion in regular sequence
pub fn sq13(&self) -> SQ13_R[src]
Bits 0:4 - 13th conversion in regular sequence
impl R<u32, Reg<u32, _SQR4>>[src]
pub fn sq12(&self) -> SQ12_R[src]
Bits 25:29 - 12th conversion in regular sequence
pub fn sq11(&self) -> SQ11_R[src]
Bits 20:24 - 11th conversion in regular sequence
pub fn sq10(&self) -> SQ10_R[src]
Bits 15:19 - 10th conversion in regular sequence
pub fn sq9(&self) -> SQ9_R[src]
Bits 10:14 - 9th conversion in regular sequence
pub fn sq8(&self) -> SQ8_R[src]
Bits 5:9 - 8th conversion in regular sequence
pub fn sq7(&self) -> SQ7_R[src]
Bits 0:4 - 7th conversion in regular sequence
impl R<u32, Reg<u32, _SQR5>>[src]
pub fn sq6(&self) -> SQ6_R[src]
Bits 25:29 - 6th conversion in regular sequence
pub fn sq5(&self) -> SQ5_R[src]
Bits 20:24 - 5th conversion in regular sequence
pub fn sq4(&self) -> SQ4_R[src]
Bits 15:19 - 4th conversion in regular sequence
pub fn sq3(&self) -> SQ3_R[src]
Bits 10:14 - 3rd conversion in regular sequence
pub fn sq2(&self) -> SQ2_R[src]
Bits 5:9 - 2nd conversion in regular sequence
pub fn sq1(&self) -> SQ1_R[src]
Bits 0:4 - 1st conversion in regular sequence
impl R<u32, Reg<u32, _JSQR>>[src]
pub fn jl(&self) -> JL_R[src]
Bits 20:21 - Injected sequence length
pub fn jsq4(&self) -> JSQ4_R[src]
Bits 15:19 - 4th conversion in injected sequence
pub fn jsq3(&self) -> JSQ3_R[src]
Bits 10:14 - 3rd conversion in injected sequence
pub fn jsq2(&self) -> JSQ2_R[src]
Bits 5:9 - 2nd conversion in injected sequence
pub fn jsq1(&self) -> JSQ1_R[src]
Bits 0:4 - 1st conversion in injected sequence
impl R<u32, Reg<u32, _JDR1>>[src]
impl R<u32, Reg<u32, _JDR2>>[src]
impl R<u32, Reg<u32, _JDR3>>[src]
impl R<u32, Reg<u32, _JDR4>>[src]
impl R<u32, Reg<u32, _DR>>[src]
pub fn regular_data(&self) -> REGULARDATA_R[src]
Bits 0:15 - Regular data
impl R<u32, Reg<u32, _SMPR0>>[src]
impl R<u32, Reg<u32, _CSR>>[src]
pub fn awd1(&self) -> AWD1_R[src]
Bit 0 - Analog watchdog flag of the ADC
pub fn eoc1(&self) -> EOC1_R[src]
Bit 1 - End of conversion of the ADC
pub fn jeoc1(&self) -> JEOC1_R[src]
Bit 2 - Injected channel end of conversion of the ADC
pub fn jstrt1(&self) -> JSTRT1_R[src]
Bit 3 - Injected channel Start flag of the ADC
pub fn strt1(&self) -> STRT1_R[src]
Bit 4 - Regular channel Start flag of the ADC
pub fn ovr1(&self) -> OVR1_R[src]
Bit 5 - Overrun flag of the ADC
pub fn adons1(&self) -> ADONS1_R[src]
Bit 6 - ADON Status of ADC1
impl R<u32, Reg<u32, _CCR>>[src]
pub fn adcpre(&self) -> ADCPRE_R[src]
Bits 16:17 - ADC prescaler
pub fn tsvrefe(&self) -> TSVREFE_R[src]
Bit 23 - Temperature sensor and VREFINT enable
impl R<u32, Reg<u32, _IDCODE>>[src]
pub fn dev_id(&self) -> DEV_ID_R[src]
Bits 0:11 - Device identifier
pub fn rev_id(&self) -> REV_ID_R[src]
Bits 16:31 - Revision identifie
impl R<u32, Reg<u32, _CR>>[src]
pub fn dbg_sleep(&self) -> DBG_SLEEP_R[src]
Bit 0 - Debug Sleep mode
pub fn dbg_stop(&self) -> DBG_STOP_R[src]
Bit 1 - Debug Stop mode
pub fn dbg_standby(&self) -> DBG_STANDBY_R[src]
Bit 2 - Debug Standby mode
pub fn trace_ioen(&self) -> TRACE_IOEN_R[src]
Bit 5 - Trace pin assignment control
pub fn trace_mode(&self) -> TRACE_MODE_R[src]
Bits 6:7 - Trace pin assignment control
impl R<u32, Reg<u32, _APB1_FZ>>[src]
pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R[src]
Bit 0 - TIM2 counter stopped when core is halted
pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R[src]
Bit 1 - TIM3 counter stopped when core is halted
pub fn dbg_tim4_stop(&self) -> DBG_TIM4_STOP_R[src]
Bit 2 - TIM4 counter stopped when core is halted
pub fn dbg_tim5_stop(&self) -> DBG_TIM5_STOP_R[src]
Bit 3 - TIM5 counter stopped when core is halted
pub fn dbg_tim6_stop(&self) -> DBG_TIM6_STOP_R[src]
Bit 4 - TIM6 counter stopped when core is halted
pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R[src]
Bit 5 - TIM7 counter stopped when core is halted
pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R[src]
Bit 10 - Debug RTC stopped when core is halted
pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R[src]
Bit 11 - Debug window watchdog stopped when core is halted
pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R[src]
Bit 12 - Debug independent watchdog stopped when core is halted
pub fn dbg_i2c1_smbus_timeout(&self) -> DBG_I2C1_SMBUS_TIMEOUT_R[src]
Bit 21 - SMBUS timeout mode stopped when core is halted
pub fn dbg_i2c2_smbus_timeout(&self) -> DBG_I2C2_SMBUS_TIMEOUT_R[src]
Bit 22 - SMBUS timeout mode stopped when core is halted
impl R<u32, Reg<u32, _APB2_FZ>>[src]
pub fn dbg_tim9_stop(&self) -> DBG_TIM9_STOP_R[src]
Bit 2 - TIM counter stopped when core is halted
pub fn dbg_tim10_stop(&self) -> DBG_TIM10_STOP_R[src]
Bit 3 - TIM counter stopped when core is halted
pub fn dbg_tim11_stop(&self) -> DBG_TIM11_STOP_R[src]
Bit 4 - TIM counter stopped when core is halted
impl R<u32, Reg<u32, _ACTRL>>[src]
pub fn disfold(&self) -> DISFOLD_R[src]
Bit 2 - DISFOLD
pub fn fpexcodis(&self) -> FPEXCODIS_R[src]
Bit 10 - FPEXCODIS
pub fn disramode(&self) -> DISRAMODE_R[src]
Bit 11 - DISRAMODE
pub fn disitmatbflush(&self) -> DISITMATBFLUSH_R[src]
Bit 12 - DISITMATBFLUSH
impl R<u32, Reg<u32, _STIR>>[src]
impl R<u32, Reg<u32, _CTRL>>[src]
pub fn enable(&self) -> ENABLE_R[src]
Bit 0 - Counter enable
pub fn tickint(&self) -> TICKINT_R[src]
Bit 1 - SysTick exception request enable
pub fn clksource(&self) -> CLKSOURCE_R[src]
Bit 2 - Clock source selection
pub fn countflag(&self) -> COUNTFLAG_R[src]
Bit 16 - COUNTFLAG
impl R<u32, Reg<u32, _LOAD_>>[src]
impl R<u32, Reg<u32, _VAL>>[src]
impl R<u32, Reg<u32, _CALIB>>[src]
impl R<u32, Reg<u32, _CR>>[src]
pub fn dmaouten(&self) -> DMAOUTEN_R[src]
Bit 12 - Enable DMA management of data output phase
pub fn dmainen(&self) -> DMAINEN_R[src]
Bit 11 - Enable DMA management of data input phase
pub fn errie(&self) -> ERRIE_R[src]
Bit 10 - Error interrupt enable
pub fn ccfie(&self) -> CCFIE_R[src]
Bit 9 - CCF flag interrupt enable
pub fn errc(&self) -> ERRC_R[src]
Bit 8 - Error clear
pub fn ccfc(&self) -> CCFC_R[src]
Bit 7 - Computation Complete Flag Clear
pub fn chmod(&self) -> CHMOD_R[src]
Bits 5:6 - AES chaining mode
pub fn mode(&self) -> MODE_R[src]
Bits 3:4 - AES operating mode
pub fn datatype(&self) -> DATATYPE_R[src]
Bits 1:2 - Data type selection
pub fn en(&self) -> EN_R[src]
Bit 0 - AES enable
impl R<u32, Reg<u32, _SR>>[src]
pub fn wrerr(&self) -> WRERR_R[src]
Bit 2 - Write error flag
pub fn rderr(&self) -> RDERR_R[src]
Bit 1 - Read error flag
pub fn ccf(&self) -> CCF_R[src]
Bit 0 - Computation complete flag
impl R<u32, Reg<u32, _DINR>>[src]
impl R<u32, Reg<u32, _DOUTR>>[src]
impl R<u32, Reg<u32, _KEYR0>>[src]
impl R<u32, Reg<u32, _KEYR1>>[src]
impl R<u32, Reg<u32, _KEYR2>>[src]
impl R<u32, Reg<u32, _KEYR3>>[src]
impl R<u32, Reg<u32, _IVR0>>[src]
impl R<u32, Reg<u32, _IVR1>>[src]
impl R<u32, Reg<u32, _IVR2>>[src]
impl R<u32, Reg<u32, _IVR3>>[src]
impl R<u32, Reg<u32, _CSR>>[src]
pub fn tsusp(&self) -> TSUSP_R[src]
Bit 31 - Suspend Timer Mode
pub fn caif(&self) -> CAIF_R[src]
Bit 30 - Channel acquisition interrupt flag
pub fn caie(&self) -> CAIE_R[src]
Bit 29 - Channel Acquisition Interrupt Enable / Clear
pub fn rch13(&self) -> RCH13_R[src]
Bit 28 - Select GPIO port PC3 as re-routed ADC input channel CH13.
pub fn fch8(&self) -> FCH8_R[src]
Bit 27 - Select GPIO port PB0 as fast ADC input channel CH8.
pub fn fch3(&self) -> FCH3_R[src]
Bit 26 - Select GPIO port PA3 as fast ADC input channel CH3.
pub fn outsel(&self) -> OUTSEL_R[src]
Bits 21:23 - Comparator 2 output selection
pub fn insel(&self) -> INSEL_R[src]
Bits 18:20 - Inverted input selection
pub fn wndwe(&self) -> WNDWE_R[src]
Bit 17 - Window mode enable
pub fn vrefouten(&self) -> VREFOUTEN_R[src]
Bit 16 - VREFINT output enable
pub fn cmp2out(&self) -> CMP2OUT_R[src]
Bit 13 - Comparator 2 output
pub fn speed(&self) -> SPEED_R[src]
Bit 12 - Comparator 2 speed mode
pub fn cmp1out(&self) -> CMP1OUT_R[src]
Bit 7 - Comparator 1 output
pub fn sw1(&self) -> SW1_R[src]
Bit 5 - SW1 analog switch enable
pub fn cmp1en(&self) -> CMP1EN_R[src]
Bit 4 - Comparator 1 enable
pub fn pd400k(&self) -> PD400K_R[src]
Bit 3 - 400 kO pull-down resistor
pub fn pd10k(&self) -> PD10K_R[src]
Bit 2 - 10 kO pull-down resistor
pub fn pu400k(&self) -> PU400K_R[src]
Bit 1 - 400 kO pull-up resistor
pub fn pu10k(&self) -> PU10K_R[src]
Bit 0 - 10 kO pull-up resistor
impl R<u32, Reg<u32, _DR>>[src]
impl R<u32, Reg<u32, _IDR>>[src]
impl R<bool, DMAUDRIE2_A>[src]
pub fn variant(&self) -> DMAUDRIE2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, DMAEN2_A>[src]
pub fn variant(&self) -> DMAEN2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, WAVE2_A>[src]
pub fn variant(&self) -> Variant<u8, WAVE2_A>[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_noise(&self) -> bool[src]
Checks if the value of the field is NOISE
pub fn is_triangle(&self) -> bool[src]
Checks if the value of the field is TRIANGLE
impl R<u8, TSEL2_A>[src]
pub fn variant(&self) -> TSEL2_A[src]
Get enumerated values variant
pub fn is_tim6_trgo(&self) -> bool[src]
Checks if the value of the field is TIM6_TRGO
pub fn is_tim8_trgo(&self) -> bool[src]
Checks if the value of the field is TIM8_TRGO
pub fn is_tim7_trgo(&self) -> bool[src]
Checks if the value of the field is TIM7_TRGO
pub fn is_tim5_trgo(&self) -> bool[src]
Checks if the value of the field is TIM5_TRGO
pub fn is_tim2_trgo(&self) -> bool[src]
Checks if the value of the field is TIM2_TRGO
pub fn is_tim4_trgo(&self) -> bool[src]
Checks if the value of the field is TIM4_TRGO
pub fn is_exti9(&self) -> bool[src]
Checks if the value of the field is EXTI9
pub fn is_software(&self) -> bool[src]
Checks if the value of the field is SOFTWARE
impl R<bool, TEN2_A>[src]
pub fn variant(&self) -> TEN2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, BOFF2_A>[src]
pub fn variant(&self) -> BOFF2_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, EN2_A>[src]
pub fn variant(&self) -> EN2_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, WAVE1_A>[src]
pub fn variant(&self) -> Variant<u8, WAVE1_A>[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_noise(&self) -> bool[src]
Checks if the value of the field is NOISE
pub fn is_triangle(&self) -> bool[src]
Checks if the value of the field is TRIANGLE
impl R<u8, TSEL1_A>[src]
pub fn variant(&self) -> Variant<u8, TSEL1_A>[src]
Get enumerated values variant
pub fn is_tim6_trgo(&self) -> bool[src]
Checks if the value of the field is TIM6_TRGO
pub fn is_tim3_trgo(&self) -> bool[src]
Checks if the value of the field is TIM3_TRGO
pub fn is_tim7_trgo(&self) -> bool[src]
Checks if the value of the field is TIM7_TRGO
pub fn is_tim15_trgo(&self) -> bool[src]
Checks if the value of the field is TIM15_TRGO
pub fn is_tim2_trgo(&self) -> bool[src]
Checks if the value of the field is TIM2_TRGO
pub fn is_exti9(&self) -> bool[src]
Checks if the value of the field is EXTI9
pub fn is_software(&self) -> bool[src]
Checks if the value of the field is SOFTWARE
impl R<u32, Reg<u32, _CR>>[src]
pub fn dmaudrie2(&self) -> DMAUDRIE2_R[src]
Bit 29 - DAC channel2 DMA underrun interrupt enable
pub fn dmaen2(&self) -> DMAEN2_R[src]
Bit 28 - DAC channel2 DMA enable
pub fn mamp2(&self) -> MAMP2_R[src]
Bits 24:27 - DAC channel2 mask/amplitude selector
pub fn wave2(&self) -> WAVE2_R[src]
Bits 22:23 - DAC channel2 noise/triangle wave generation enable
pub fn tsel2(&self) -> TSEL2_R[src]
Bits 19:21 - DAC channel2 trigger selection
pub fn ten2(&self) -> TEN2_R[src]
Bit 18 - DAC channel2 trigger enable
pub fn boff2(&self) -> BOFF2_R[src]
Bit 17 - DAC channel2 output buffer disable
pub fn en2(&self) -> EN2_R[src]
Bit 16 - DAC channel2 enable
pub fn dmaudrie1(&self) -> DMAUDRIE1_R[src]
Bit 13 - DAC channel1 DMA Underrun Interrupt enable
pub fn dmaen1(&self) -> DMAEN1_R[src]
Bit 12 - DAC channel1 DMA enable
pub fn mamp1(&self) -> MAMP1_R[src]
Bits 8:11 - DAC channel1 mask/amplitude selector
pub fn wave1(&self) -> WAVE1_R[src]
Bits 6:7 - DAC channel1 noise/triangle wave generation enable
pub fn tsel1(&self) -> TSEL1_R[src]
Bits 3:5 - DAC channel1 trigger selection
pub fn ten1(&self) -> TEN1_R[src]
Bit 2 - DAC channel1 trigger enable
pub fn boff1(&self) -> BOFF1_R[src]
Bit 1 - DAC channel1 output buffer disable
pub fn en1(&self) -> EN1_R[src]
Bit 0 - DAC channel1 enable
impl R<u32, Reg<u32, _DHR12R1>>[src]
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
impl R<u32, Reg<u32, _DHR12L1>>[src]
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
impl R<u32, Reg<u32, _DHR8R1>>[src]
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl R<u32, Reg<u32, _DHR12R2>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 0:11 - DAC channel2 12-bit right-aligned data
impl R<u32, Reg<u32, _DHR12L2>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 4:15 - DAC channel2 12-bit left-aligned data
impl R<u32, Reg<u32, _DHR8R2>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 0:7 - DAC channel2 8-bit right-aligned data
impl R<u32, Reg<u32, _DHR12RD>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 16:27 - DAC channel2 12-bit right-aligned data
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:11 - DAC channel1 12-bit right-aligned data
impl R<u32, Reg<u32, _DHR12LD>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 20:31 - DAC channel2 12-bit left-aligned data
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 4:15 - DAC channel1 12-bit left-aligned data
impl R<u32, Reg<u32, _DHR8RD>>[src]
pub fn dacc2dhr(&self) -> DACC2DHR_R[src]
Bits 8:15 - DAC channel2 8-bit right-aligned data
pub fn dacc1dhr(&self) -> DACC1DHR_R[src]
Bits 0:7 - DAC channel1 8-bit right-aligned data
impl R<u32, Reg<u32, _DOR1>>[src]
pub fn dacc1dor(&self) -> DACC1DOR_R[src]
Bits 0:11 - DAC channel1 data output
impl R<u32, Reg<u32, _DOR2>>[src]
pub fn dacc2dor(&self) -> DACC2DOR_R[src]
Bits 0:11 - DAC channel2 data output
impl R<bool, DMAUDR2_A>[src]
pub fn variant(&self) -> DMAUDR2_A[src]
Get enumerated values variant
pub fn is_no_underrun(&self) -> bool[src]
Checks if the value of the field is NOUNDERRUN
pub fn is_underrun(&self) -> bool[src]
Checks if the value of the field is UNDERRUN
impl R<u32, Reg<u32, _SR>>[src]
pub fn dmaudr2(&self) -> DMAUDR2_R[src]
Bit 29 - DAC channel2 DMA underrun flag
pub fn dmaudr1(&self) -> DMAUDR1_R[src]
Bit 13 - DAC channel1 DMA underrun flag
impl R<u32, Reg<u32, _ISR>>[src]
pub fn teif7(&self) -> TEIF7_R[src]
Bit 27 - Channel x transfer error flag (x = 1 ..7)
pub fn htif7(&self) -> HTIF7_R[src]
Bit 26 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif7(&self) -> TCIF7_R[src]
Bit 25 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif7(&self) -> GIF7_R[src]
Bit 24 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif6(&self) -> TEIF6_R[src]
Bit 23 - Channel x transfer error flag (x = 1 ..7)
pub fn htif6(&self) -> HTIF6_R[src]
Bit 22 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif6(&self) -> TCIF6_R[src]
Bit 21 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif6(&self) -> GIF6_R[src]
Bit 20 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif5(&self) -> TEIF5_R[src]
Bit 19 - Channel x transfer error flag (x = 1 ..7)
pub fn htif5(&self) -> HTIF5_R[src]
Bit 18 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif5(&self) -> TCIF5_R[src]
Bit 17 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif5(&self) -> GIF5_R[src]
Bit 16 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif4(&self) -> TEIF4_R[src]
Bit 15 - Channel x transfer error flag (x = 1 ..7)
pub fn htif4(&self) -> HTIF4_R[src]
Bit 14 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif4(&self) -> TCIF4_R[src]
Bit 13 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif4(&self) -> GIF4_R[src]
Bit 12 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif3(&self) -> TEIF3_R[src]
Bit 11 - Channel x transfer error flag (x = 1 ..7)
pub fn htif3(&self) -> HTIF3_R[src]
Bit 10 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif3(&self) -> TCIF3_R[src]
Bit 9 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif3(&self) -> GIF3_R[src]
Bit 8 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif2(&self) -> TEIF2_R[src]
Bit 7 - Channel x transfer error flag (x = 1 ..7)
pub fn htif2(&self) -> HTIF2_R[src]
Bit 6 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif2(&self) -> TCIF2_R[src]
Bit 5 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif2(&self) -> GIF2_R[src]
Bit 4 - Channel x global interrupt flag (x = 1 ..7)
pub fn teif1(&self) -> TEIF1_R[src]
Bit 3 - Channel x transfer error flag (x = 1 ..7)
pub fn htif1(&self) -> HTIF1_R[src]
Bit 2 - Channel x half transfer flag (x = 1 ..7)
pub fn tcif1(&self) -> TCIF1_R[src]
Bit 1 - Channel x transfer complete flag (x = 1 ..7)
pub fn gif1(&self) -> GIF1_R[src]
Bit 0 - Channel x global interrupt flag (x = 1 ..7)
impl R<u32, Reg<u32, _CCR1>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR1>>[src]
impl R<u32, Reg<u32, _CPAR1>>[src]
impl R<u32, Reg<u32, _CMAR1>>[src]
impl R<u32, Reg<u32, _CCR2>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR2>>[src]
impl R<u32, Reg<u32, _CPAR2>>[src]
impl R<u32, Reg<u32, _CMAR2>>[src]
impl R<u32, Reg<u32, _CCR3>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR3>>[src]
impl R<u32, Reg<u32, _CPAR3>>[src]
impl R<u32, Reg<u32, _CMAR3>>[src]
impl R<u32, Reg<u32, _CCR4>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR4>>[src]
impl R<u32, Reg<u32, _CPAR4>>[src]
impl R<u32, Reg<u32, _CMAR4>>[src]
impl R<u32, Reg<u32, _CCR5>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR5>>[src]
impl R<u32, Reg<u32, _CPAR5>>[src]
impl R<u32, Reg<u32, _CMAR5>>[src]
impl R<u32, Reg<u32, _CCR6>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR6>>[src]
impl R<u32, Reg<u32, _CPAR6>>[src]
impl R<u32, Reg<u32, _CMAR6>>[src]
impl R<u32, Reg<u32, _CCR7>>[src]
pub fn mem2mem(&self) -> MEM2MEM_R[src]
Bit 14 - Memory to memory mode
pub fn pl(&self) -> PL_R[src]
Bits 12:13 - Channel priority level
pub fn msize(&self) -> MSIZE_R[src]
Bits 10:11 - Memory size
pub fn psize(&self) -> PSIZE_R[src]
Bits 8:9 - Peripheral size
pub fn minc(&self) -> MINC_R[src]
Bit 7 - Memory increment mode
pub fn pinc(&self) -> PINC_R[src]
Bit 6 - Peripheral increment mode
pub fn circ(&self) -> CIRC_R[src]
Bit 5 - Circular mode
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Data transfer direction
pub fn teie(&self) -> TEIE_R[src]
Bit 3 - Transfer error interrupt enable
pub fn htie(&self) -> HTIE_R[src]
Bit 2 - Half transfer interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 1 - Transfer complete interrupt enable
pub fn en(&self) -> EN_R[src]
Bit 0 - Channel enable
impl R<u32, Reg<u32, _CNDTR7>>[src]
impl R<u32, Reg<u32, _CPAR7>>[src]
impl R<u32, Reg<u32, _CMAR7>>[src]
impl R<bool, MR0_A>[src]
pub fn variant(&self) -> MR0_A[src]
Get enumerated values variant
pub fn is_masked(&self) -> bool[src]
Checks if the value of the field is MASKED
pub fn is_unmasked(&self) -> bool[src]
Checks if the value of the field is UNMASKED
impl R<u32, Reg<u32, _IMR>>[src]
pub fn mr0(&self) -> MR0_R[src]
Bit 0 - Interrupt mask on line x
pub fn mr1(&self) -> MR1_R[src]
Bit 1 - Interrupt mask on line x
pub fn mr2(&self) -> MR2_R[src]
Bit 2 - Interrupt mask on line x
pub fn mr3(&self) -> MR3_R[src]
Bit 3 - Interrupt mask on line x
pub fn mr4(&self) -> MR4_R[src]
Bit 4 - Interrupt mask on line x
pub fn mr5(&self) -> MR5_R[src]
Bit 5 - Interrupt mask on line x
pub fn mr6(&self) -> MR6_R[src]
Bit 6 - Interrupt mask on line x
pub fn mr7(&self) -> MR7_R[src]
Bit 7 - Interrupt mask on line x
pub fn mr8(&self) -> MR8_R[src]
Bit 8 - Interrupt mask on line x
pub fn mr9(&self) -> MR9_R[src]
Bit 9 - Interrupt mask on line x
pub fn mr10(&self) -> MR10_R[src]
Bit 10 - Interrupt mask on line x
pub fn mr11(&self) -> MR11_R[src]
Bit 11 - Interrupt mask on line x
pub fn mr12(&self) -> MR12_R[src]
Bit 12 - Interrupt mask on line x
pub fn mr13(&self) -> MR13_R[src]
Bit 13 - Interrupt mask on line x
pub fn mr14(&self) -> MR14_R[src]
Bit 14 - Interrupt mask on line x
pub fn mr15(&self) -> MR15_R[src]
Bit 15 - Interrupt mask on line x
pub fn mr16(&self) -> MR16_R[src]
Bit 16 - Interrupt mask on line x
pub fn mr17(&self) -> MR17_R[src]
Bit 17 - Interrupt mask on line x
pub fn mr18(&self) -> MR18_R[src]
Bit 18 - Interrupt mask on line x
pub fn mr19(&self) -> MR19_R[src]
Bit 19 - Interrupt mask on line x
pub fn mr20(&self) -> MR20_R[src]
Bit 20 - Interrupt mask on line x
pub fn mr21(&self) -> MR21_R[src]
Bit 21 - Interrupt mask on line x
pub fn mr22(&self) -> MR22_R[src]
Bit 22 - Interrupt mask on line x
impl R<bool, MR0_A>[src]
pub fn variant(&self) -> MR0_A[src]
Get enumerated values variant
pub fn is_masked(&self) -> bool[src]
Checks if the value of the field is MASKED
pub fn is_unmasked(&self) -> bool[src]
Checks if the value of the field is UNMASKED
impl R<u32, Reg<u32, _EMR>>[src]
pub fn mr0(&self) -> MR0_R[src]
Bit 0 - Event mask on line x
pub fn mr1(&self) -> MR1_R[src]
Bit 1 - Event mask on line x
pub fn mr2(&self) -> MR2_R[src]
Bit 2 - Event mask on line x
pub fn mr3(&self) -> MR3_R[src]
Bit 3 - Event mask on line x
pub fn mr4(&self) -> MR4_R[src]
Bit 4 - Event mask on line x
pub fn mr5(&self) -> MR5_R[src]
Bit 5 - Event mask on line x
pub fn mr6(&self) -> MR6_R[src]
Bit 6 - Event mask on line x
pub fn mr7(&self) -> MR7_R[src]
Bit 7 - Event mask on line x
pub fn mr8(&self) -> MR8_R[src]
Bit 8 - Event mask on line x
pub fn mr9(&self) -> MR9_R[src]
Bit 9 - Event mask on line x
pub fn mr10(&self) -> MR10_R[src]
Bit 10 - Event mask on line x
pub fn mr11(&self) -> MR11_R[src]
Bit 11 - Event mask on line x
pub fn mr12(&self) -> MR12_R[src]
Bit 12 - Event mask on line x
pub fn mr13(&self) -> MR13_R[src]
Bit 13 - Event mask on line x
pub fn mr14(&self) -> MR14_R[src]
Bit 14 - Event mask on line x
pub fn mr15(&self) -> MR15_R[src]
Bit 15 - Event mask on line x
pub fn mr16(&self) -> MR16_R[src]
Bit 16 - Event mask on line x
pub fn mr17(&self) -> MR17_R[src]
Bit 17 - Event mask on line x
pub fn mr18(&self) -> MR18_R[src]
Bit 18 - Event mask on line x
pub fn mr19(&self) -> MR19_R[src]
Bit 19 - Event mask on line x
pub fn mr20(&self) -> MR20_R[src]
Bit 20 - Event mask on line x
pub fn mr21(&self) -> MR21_R[src]
Bit 21 - Event mask on line x
pub fn mr22(&self) -> MR22_R[src]
Bit 22 - Event mask on line x
impl R<bool, TR0_A>[src]
pub fn variant(&self) -> TR0_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _RTSR>>[src]
pub fn tr0(&self) -> TR0_R[src]
Bit 0 - Rising edge trigger event configuration bit of line x
pub fn tr1(&self) -> TR1_R[src]
Bit 1 - Rising edge trigger event configuration bit of line x
pub fn tr2(&self) -> TR2_R[src]
Bit 2 - Rising edge trigger event configuration bit of line x
pub fn tr3(&self) -> TR3_R[src]
Bit 3 - Rising edge trigger event configuration bit of line x
pub fn tr4(&self) -> TR4_R[src]
Bit 4 - Rising edge trigger event configuration bit of line x
pub fn tr5(&self) -> TR5_R[src]
Bit 5 - Rising edge trigger event configuration bit of line x
pub fn tr6(&self) -> TR6_R[src]
Bit 6 - Rising edge trigger event configuration bit of line x
pub fn tr7(&self) -> TR7_R[src]
Bit 7 - Rising edge trigger event configuration bit of line x
pub fn tr8(&self) -> TR8_R[src]
Bit 8 - Rising edge trigger event configuration bit of line x
pub fn tr9(&self) -> TR9_R[src]
Bit 9 - Rising edge trigger event configuration bit of line x
pub fn tr10(&self) -> TR10_R[src]
Bit 10 - Rising edge trigger event configuration bit of line x
pub fn tr11(&self) -> TR11_R[src]
Bit 11 - Rising edge trigger event configuration bit of line x
pub fn tr12(&self) -> TR12_R[src]
Bit 12 - Rising edge trigger event configuration bit of line x
pub fn tr13(&self) -> TR13_R[src]
Bit 13 - Rising edge trigger event configuration bit of line x
pub fn tr14(&self) -> TR14_R[src]
Bit 14 - Rising edge trigger event configuration bit of line x
pub fn tr15(&self) -> TR15_R[src]
Bit 15 - Rising edge trigger event configuration bit of line x
pub fn tr16(&self) -> TR16_R[src]
Bit 16 - Rising edge trigger event configuration bit of line x
pub fn tr17(&self) -> TR17_R[src]
Bit 17 - Rising edge trigger event configuration bit of line x
pub fn tr18(&self) -> TR18_R[src]
Bit 18 - Rising edge trigger event configuration bit of line x
pub fn tr19(&self) -> TR19_R[src]
Bit 19 - Rising edge trigger event configuration bit of line x
pub fn tr20(&self) -> TR20_R[src]
Bit 20 - Rising edge trigger event configuration bit of line x
pub fn tr21(&self) -> TR21_R[src]
Bit 21 - Rising edge trigger event configuration bit of line x
pub fn tr22(&self) -> TR22_R[src]
Bit 22 - Rising edge trigger event configuration bit of line x
impl R<bool, TR0_A>[src]
pub fn variant(&self) -> TR0_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _FTSR>>[src]
pub fn tr0(&self) -> TR0_R[src]
Bit 0 - Falling edge trigger event configuration bit of line x
pub fn tr1(&self) -> TR1_R[src]
Bit 1 - Falling edge trigger event configuration bit of line x
pub fn tr2(&self) -> TR2_R[src]
Bit 2 - Falling edge trigger event configuration bit of line x
pub fn tr3(&self) -> TR3_R[src]
Bit 3 - Falling edge trigger event configuration bit of line x
pub fn tr4(&self) -> TR4_R[src]
Bit 4 - Falling edge trigger event configuration bit of line x
pub fn tr5(&self) -> TR5_R[src]
Bit 5 - Falling edge trigger event configuration bit of line x
pub fn tr6(&self) -> TR6_R[src]
Bit 6 - Falling edge trigger event configuration bit of line x
pub fn tr7(&self) -> TR7_R[src]
Bit 7 - Falling edge trigger event configuration bit of line x
pub fn tr8(&self) -> TR8_R[src]
Bit 8 - Falling edge trigger event configuration bit of line x
pub fn tr9(&self) -> TR9_R[src]
Bit 9 - Falling edge trigger event configuration bit of line x
pub fn tr10(&self) -> TR10_R[src]
Bit 10 - Falling edge trigger event configuration bit of line x
pub fn tr11(&self) -> TR11_R[src]
Bit 11 - Falling edge trigger event configuration bit of line x
pub fn tr12(&self) -> TR12_R[src]
Bit 12 - Falling edge trigger event configuration bit of line x
pub fn tr13(&self) -> TR13_R[src]
Bit 13 - Falling edge trigger event configuration bit of line x
pub fn tr14(&self) -> TR14_R[src]
Bit 14 - Falling edge trigger event configuration bit of line x
pub fn tr15(&self) -> TR15_R[src]
Bit 15 - Falling edge trigger event configuration bit of line x
pub fn tr16(&self) -> TR16_R[src]
Bit 16 - Falling edge trigger event configuration bit of line x
pub fn tr17(&self) -> TR17_R[src]
Bit 17 - Falling edge trigger event configuration bit of line x
pub fn tr18(&self) -> TR18_R[src]
Bit 18 - Falling edge trigger event configuration bit of line x
pub fn tr19(&self) -> TR19_R[src]
Bit 19 - Falling edge trigger event configuration bit of line x
pub fn tr20(&self) -> TR20_R[src]
Bit 20 - Falling edge trigger event configuration bit of line x
pub fn tr21(&self) -> TR21_R[src]
Bit 21 - Falling edge trigger event configuration bit of line x
pub fn tr22(&self) -> TR22_R[src]
Bit 22 - Falling edge trigger event configuration bit of line x
impl R<bool, SWIER0_A>[src]
pub fn variant(&self) -> Variant<bool, SWIER0_A>[src]
Get enumerated values variant
pub fn is_pend(&self) -> bool[src]
Checks if the value of the field is PEND
impl R<u32, Reg<u32, _SWIER>>[src]
pub fn swier0(&self) -> SWIER0_R[src]
Bit 0 - Software interrupt on line x
pub fn swier1(&self) -> SWIER1_R[src]
Bit 1 - Software interrupt on line x
pub fn swier2(&self) -> SWIER2_R[src]
Bit 2 - Software interrupt on line x
pub fn swier3(&self) -> SWIER3_R[src]
Bit 3 - Software interrupt on line x
pub fn swier4(&self) -> SWIER4_R[src]
Bit 4 - Software interrupt on line x
pub fn swier5(&self) -> SWIER5_R[src]
Bit 5 - Software interrupt on line x
pub fn swier6(&self) -> SWIER6_R[src]
Bit 6 - Software interrupt on line x
pub fn swier7(&self) -> SWIER7_R[src]
Bit 7 - Software interrupt on line x
pub fn swier8(&self) -> SWIER8_R[src]
Bit 8 - Software interrupt on line x
pub fn swier9(&self) -> SWIER9_R[src]
Bit 9 - Software interrupt on line x
pub fn swier10(&self) -> SWIER10_R[src]
Bit 10 - Software interrupt on line x
pub fn swier11(&self) -> SWIER11_R[src]
Bit 11 - Software interrupt on line x
pub fn swier12(&self) -> SWIER12_R[src]
Bit 12 - Software interrupt on line x
pub fn swier13(&self) -> SWIER13_R[src]
Bit 13 - Software interrupt on line x
pub fn swier14(&self) -> SWIER14_R[src]
Bit 14 - Software interrupt on line x
pub fn swier15(&self) -> SWIER15_R[src]
Bit 15 - Software interrupt on line x
pub fn swier16(&self) -> SWIER16_R[src]
Bit 16 - Software interrupt on line x
pub fn swier17(&self) -> SWIER17_R[src]
Bit 17 - Software interrupt on line x
pub fn swier18(&self) -> SWIER18_R[src]
Bit 18 - Software interrupt on line x
pub fn swier19(&self) -> SWIER19_R[src]
Bit 19 - Software interrupt on line x
pub fn swier20(&self) -> SWIER20_R[src]
Bit 20 - Software interrupt on line x
pub fn swier21(&self) -> SWIER21_R[src]
Bit 21 - Software interrupt on line x
pub fn swier22(&self) -> SWIER22_R[src]
Bit 22 - Software interrupt on line x
impl R<bool, PR0_A>[src]
pub fn variant(&self) -> PR0_A[src]
Get enumerated values variant
pub fn is_not_pending(&self) -> bool[src]
Checks if the value of the field is NOTPENDING
pub fn is_pending(&self) -> bool[src]
Checks if the value of the field is PENDING
impl R<u32, Reg<u32, _PR>>[src]
pub fn pr0(&self) -> PR0_R[src]
Bit 0 - Pending bit
pub fn pr1(&self) -> PR1_R[src]
Bit 1 - Pending bit
pub fn pr2(&self) -> PR2_R[src]
Bit 2 - Pending bit
pub fn pr3(&self) -> PR3_R[src]
Bit 3 - Pending bit
pub fn pr4(&self) -> PR4_R[src]
Bit 4 - Pending bit
pub fn pr5(&self) -> PR5_R[src]
Bit 5 - Pending bit
pub fn pr6(&self) -> PR6_R[src]
Bit 6 - Pending bit
pub fn pr7(&self) -> PR7_R[src]
Bit 7 - Pending bit
pub fn pr8(&self) -> PR8_R[src]
Bit 8 - Pending bit
pub fn pr9(&self) -> PR9_R[src]
Bit 9 - Pending bit
pub fn pr10(&self) -> PR10_R[src]
Bit 10 - Pending bit
pub fn pr11(&self) -> PR11_R[src]
Bit 11 - Pending bit
pub fn pr12(&self) -> PR12_R[src]
Bit 12 - Pending bit
pub fn pr13(&self) -> PR13_R[src]
Bit 13 - Pending bit
pub fn pr14(&self) -> PR14_R[src]
Bit 14 - Pending bit
pub fn pr15(&self) -> PR15_R[src]
Bit 15 - Pending bit
pub fn pr16(&self) -> PR16_R[src]
Bit 16 - Pending bit
pub fn pr17(&self) -> PR17_R[src]
Bit 17 - Pending bit
pub fn pr18(&self) -> PR18_R[src]
Bit 18 - Pending bit
pub fn pr19(&self) -> PR19_R[src]
Bit 19 - Pending bit
pub fn pr20(&self) -> PR20_R[src]
Bit 20 - Pending bit
pub fn pr21(&self) -> PR21_R[src]
Bit 21 - Pending bit
pub fn pr22(&self) -> PR22_R[src]
Bit 22 - Pending bit
impl R<u32, Reg<u32, _ACR>>[src]
pub fn latency(&self) -> LATENCY_R[src]
Bit 0 - Latency
pub fn prften(&self) -> PRFTEN_R[src]
Bit 1 - Prefetch enable
pub fn acc64(&self) -> ACC64_R[src]
Bit 2 - 64-bit access
pub fn sleep_pd(&self) -> SLEEP_PD_R[src]
Bit 3 - Flash mode during Sleep
pub fn run_pd(&self) -> RUN_PD_R[src]
Bit 4 - Flash mode during Run
impl R<u32, Reg<u32, _PECR>>[src]
pub fn pelock(&self) -> PELOCK_R[src]
Bit 0 - FLASH_PECR and data EEPROM lock
pub fn prglock(&self) -> PRGLOCK_R[src]
Bit 1 - Program memory lock
pub fn optlock(&self) -> OPTLOCK_R[src]
Bit 2 - Option bytes block lock
pub fn prog(&self) -> PROG_R[src]
Bit 3 - Program memory selection
pub fn data(&self) -> DATA_R[src]
Bit 4 - Data EEPROM selection
pub fn ftdw(&self) -> FTDW_R[src]
Bit 8 - Fixed time data write for Byte, Half Word and Word programming
pub fn erase(&self) -> ERASE_R[src]
Bit 9 - Page or Double Word erase mode
pub fn fprg(&self) -> FPRG_R[src]
Bit 10 - Half Page/Double Word programming mode
pub fn parallelbank(&self) -> PARALLELBANK_R[src]
Bit 15 - Parallel bank mode
pub fn eopie(&self) -> EOPIE_R[src]
Bit 16 - End of programming interrupt enable
pub fn errie(&self) -> ERRIE_R[src]
Bit 17 - Error interrupt enable
pub fn obl_launch(&self) -> OBL_LAUNCH_R[src]
Bit 18 - Launch the option byte loading
impl R<u32, Reg<u32, _SR>>[src]
pub fn bsy(&self) -> BSY_R[src]
Bit 0 - Write/erase operations in progress
pub fn eop(&self) -> EOP_R[src]
Bit 1 - End of operation
pub fn endhv(&self) -> ENDHV_R[src]
Bit 2 - End of high voltage
pub fn ready(&self) -> READY_R[src]
Bit 3 - Flash memory module ready after low power mode
pub fn wrperr(&self) -> WRPERR_R[src]
Bit 8 - Write protected error
pub fn pgaerr(&self) -> PGAERR_R[src]
Bit 9 - Programming alignment error
pub fn sizerr(&self) -> SIZERR_R[src]
Bit 10 - Size error
pub fn optverr(&self) -> OPTVERR_R[src]
Bit 11 - Option validity error
pub fn optverrusr(&self) -> OPTVERRUSR_R[src]
Bit 12 - Option UserValidity Error
impl R<u32, Reg<u32, _OBR>>[src]
pub fn rdprt(&self) -> RDPRT_R[src]
Bits 0:7 - Read protection
pub fn bor_lev(&self) -> BOR_LEV_R[src]
Bits 16:19 - BOR_LEV
pub fn iwdg_sw(&self) -> IWDG_SW_R[src]
Bit 20 - IWDG_SW
pub fn n_rts_stop(&self) -> NRTS_STOP_R[src]
Bit 21 - nRTS_STOP
pub fn n_rst_stdby(&self) -> NRST_STDBY_R[src]
Bit 22 - nRST_STDBY
pub fn bfb2(&self) -> BFB2_R[src]
Bit 23 - Boot From Bank 2
impl R<u32, Reg<u32, _WRPR1>>[src]
impl R<u32, Reg<u32, _WRPR2>>[src]
impl R<u32, Reg<u32, _WRPR3>>[src]
impl R<bool, CBURSTRW_A>[src]
pub fn variant(&self) -> CBURSTRW_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, ASYNCWAIT_A>[src]
pub fn variant(&self) -> ASYNCWAIT_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, EXTMOD_A>[src]
pub fn variant(&self) -> EXTMOD_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITEN_A>[src]
pub fn variant(&self) -> WAITEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WREN_A>[src]
pub fn variant(&self) -> WREN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITCFG_A>[src]
pub fn variant(&self) -> WAITCFG_A[src]
Get enumerated values variant
pub fn is_before_wait_state(&self) -> bool[src]
Checks if the value of the field is BEFOREWAITSTATE
pub fn is_during_wait_state(&self) -> bool[src]
Checks if the value of the field is DURINGWAITSTATE
impl R<bool, WAITPOL_A>[src]
pub fn variant(&self) -> WAITPOL_A[src]
Get enumerated values variant
pub fn is_active_low(&self) -> bool[src]
Checks if the value of the field is ACTIVELOW
pub fn is_active_high(&self) -> bool[src]
Checks if the value of the field is ACTIVEHIGH
impl R<bool, BURSTEN_A>[src]
pub fn variant(&self) -> BURSTEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, FACCEN_A>[src]
pub fn variant(&self) -> FACCEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, MWID_A>[src]
pub fn variant(&self) -> Variant<u8, MWID_A>[src]
Get enumerated values variant
pub fn is_bits8(&self) -> bool[src]
Checks if the value of the field is BITS8
pub fn is_bits16(&self) -> bool[src]
Checks if the value of the field is BITS16
pub fn is_bits32(&self) -> bool[src]
Checks if the value of the field is BITS32
impl R<u8, MTYP_A>[src]
pub fn variant(&self) -> Variant<u8, MTYP_A>[src]
Get enumerated values variant
pub fn is_sram(&self) -> bool[src]
Checks if the value of the field is SRAM
pub fn is_psram(&self) -> bool[src]
Checks if the value of the field is PSRAM
pub fn is_flash(&self) -> bool[src]
Checks if the value of the field is FLASH
impl R<bool, MUXEN_A>[src]
pub fn variant(&self) -> MUXEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, MBKEN_A>[src]
pub fn variant(&self) -> MBKEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CPSIZE_A>[src]
pub fn variant(&self) -> Variant<u8, CPSIZE_A>[src]
Get enumerated values variant
pub fn is_no_burst_split(&self) -> bool[src]
Checks if the value of the field is NOBURSTSPLIT
pub fn is_bytes128(&self) -> bool[src]
Checks if the value of the field is BYTES128
pub fn is_bytes256(&self) -> bool[src]
Checks if the value of the field is BYTES256
pub fn is_bytes512(&self) -> bool[src]
Checks if the value of the field is BYTES512
pub fn is_bytes1024(&self) -> bool[src]
Checks if the value of the field is BYTES1024
impl R<u32, Reg<u32, _BCR1>>[src]
pub fn cburstrw(&self) -> CBURSTRW_R[src]
Bit 19 - CBURSTRW
pub fn asyncwait(&self) -> ASYNCWAIT_R[src]
Bit 15 - ASYNCWAIT
pub fn extmod(&self) -> EXTMOD_R[src]
Bit 14 - EXTMOD
pub fn waiten(&self) -> WAITEN_R[src]
Bit 13 - WAITEN
pub fn wren(&self) -> WREN_R[src]
Bit 12 - WREN
pub fn waitcfg(&self) -> WAITCFG_R[src]
Bit 11 - WAITCFG
pub fn wrapmod(&self) -> WRAPMOD_R[src]
Bit 10 - WRAPMOD
pub fn waitpol(&self) -> WAITPOL_R[src]
Bit 9 - WAITPOL
pub fn bursten(&self) -> BURSTEN_R[src]
Bit 8 - BURSTEN
pub fn faccen(&self) -> FACCEN_R[src]
Bit 6 - FACCEN
pub fn mwid(&self) -> MWID_R[src]
Bits 4:5 - MWID
pub fn mtyp(&self) -> MTYP_R[src]
Bits 2:3 - MTYP
pub fn muxen(&self) -> MUXEN_R[src]
Bit 1 - MUXEN
pub fn mbken(&self) -> MBKEN_R[src]
Bit 0 - MBKEN
pub fn cpsize(&self) -> CPSIZE_R[src]
Bits 16:18 - CRAM page size
impl R<u8, ACCMOD_A>[src]
pub fn variant(&self) -> ACCMOD_A[src]
Get enumerated values variant
pub fn is_a(&self) -> bool[src]
Checks if the value of the field is A
pub fn is_b(&self) -> bool[src]
Checks if the value of the field is B
pub fn is_c(&self) -> bool[src]
Checks if the value of the field is C
pub fn is_d(&self) -> bool[src]
Checks if the value of the field is D
impl R<u32, Reg<u32, _BTR>>[src]
pub fn accmod(&self) -> ACCMOD_R[src]
Bits 28:29 - ACCMOD
pub fn datlat(&self) -> DATLAT_R[src]
Bits 24:27 - DATLAT
pub fn clkdiv(&self) -> CLKDIV_R[src]
Bits 20:23 - CLKDIV
pub fn busturn(&self) -> BUSTURN_R[src]
Bits 16:19 - BUSTURN
pub fn datast(&self) -> DATAST_R[src]
Bits 8:15 - DATAST
pub fn addhld(&self) -> ADDHLD_R[src]
Bits 4:7 - ADDHLD
pub fn addset(&self) -> ADDSET_R[src]
Bits 0:3 - ADDSET
impl R<bool, CBURSTRW_A>[src]
pub fn variant(&self) -> CBURSTRW_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, ASYNCWAIT_A>[src]
pub fn variant(&self) -> ASYNCWAIT_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, EXTMOD_A>[src]
pub fn variant(&self) -> EXTMOD_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITEN_A>[src]
pub fn variant(&self) -> WAITEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WREN_A>[src]
pub fn variant(&self) -> WREN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WAITCFG_A>[src]
pub fn variant(&self) -> WAITCFG_A[src]
Get enumerated values variant
pub fn is_before_wait_state(&self) -> bool[src]
Checks if the value of the field is BEFOREWAITSTATE
pub fn is_during_wait_state(&self) -> bool[src]
Checks if the value of the field is DURINGWAITSTATE
impl R<bool, WAITPOL_A>[src]
pub fn variant(&self) -> WAITPOL_A[src]
Get enumerated values variant
pub fn is_active_low(&self) -> bool[src]
Checks if the value of the field is ACTIVELOW
pub fn is_active_high(&self) -> bool[src]
Checks if the value of the field is ACTIVEHIGH
impl R<bool, BURSTEN_A>[src]
pub fn variant(&self) -> BURSTEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, FACCEN_A>[src]
pub fn variant(&self) -> FACCEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, MWID_A>[src]
pub fn variant(&self) -> Variant<u8, MWID_A>[src]
Get enumerated values variant
pub fn is_bits8(&self) -> bool[src]
Checks if the value of the field is BITS8
pub fn is_bits16(&self) -> bool[src]
Checks if the value of the field is BITS16
pub fn is_bits32(&self) -> bool[src]
Checks if the value of the field is BITS32
impl R<u8, MTYP_A>[src]
pub fn variant(&self) -> Variant<u8, MTYP_A>[src]
Get enumerated values variant
pub fn is_sram(&self) -> bool[src]
Checks if the value of the field is SRAM
pub fn is_psram(&self) -> bool[src]
Checks if the value of the field is PSRAM
pub fn is_flash(&self) -> bool[src]
Checks if the value of the field is FLASH
impl R<bool, MUXEN_A>[src]
pub fn variant(&self) -> MUXEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, MBKEN_A>[src]
pub fn variant(&self) -> MBKEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CPSIZE_A>[src]
pub fn variant(&self) -> Variant<u8, CPSIZE_A>[src]
Get enumerated values variant
pub fn is_no_burst_split(&self) -> bool[src]
Checks if the value of the field is NOBURSTSPLIT
pub fn is_bytes128(&self) -> bool[src]
Checks if the value of the field is BYTES128
pub fn is_bytes256(&self) -> bool[src]
Checks if the value of the field is BYTES256
pub fn is_bytes512(&self) -> bool[src]
Checks if the value of the field is BYTES512
pub fn is_bytes1024(&self) -> bool[src]
Checks if the value of the field is BYTES1024
impl R<u32, Reg<u32, _BCR>>[src]
pub fn cburstrw(&self) -> CBURSTRW_R[src]
Bit 19 - CBURSTRW
pub fn asyncwait(&self) -> ASYNCWAIT_R[src]
Bit 15 - ASYNCWAIT
pub fn extmod(&self) -> EXTMOD_R[src]
Bit 14 - EXTMOD
pub fn waiten(&self) -> WAITEN_R[src]
Bit 13 - WAITEN
pub fn wren(&self) -> WREN_R[src]
Bit 12 - WREN
pub fn waitcfg(&self) -> WAITCFG_R[src]
Bit 11 - WAITCFG
pub fn wrapmod(&self) -> WRAPMOD_R[src]
Bit 10 - WRAPMOD
pub fn waitpol(&self) -> WAITPOL_R[src]
Bit 9 - WAITPOL
pub fn bursten(&self) -> BURSTEN_R[src]
Bit 8 - BURSTEN
pub fn faccen(&self) -> FACCEN_R[src]
Bit 6 - FACCEN
pub fn mwid(&self) -> MWID_R[src]
Bits 4:5 - MWID
pub fn mtyp(&self) -> MTYP_R[src]
Bits 2:3 - MTYP
pub fn muxen(&self) -> MUXEN_R[src]
Bit 1 - MUXEN
pub fn mbken(&self) -> MBKEN_R[src]
Bit 0 - MBKEN
pub fn cpsize(&self) -> CPSIZE_R[src]
Bits 16:18 - CRAM page size
impl R<u8, ACCMOD_A>[src]
pub fn variant(&self) -> ACCMOD_A[src]
Get enumerated values variant
pub fn is_a(&self) -> bool[src]
Checks if the value of the field is A
pub fn is_b(&self) -> bool[src]
Checks if the value of the field is B
pub fn is_c(&self) -> bool[src]
Checks if the value of the field is C
pub fn is_d(&self) -> bool[src]
Checks if the value of the field is D
impl R<u32, Reg<u32, _BWTR>>[src]
pub fn accmod(&self) -> ACCMOD_R[src]
Bits 28:29 - ACCMOD
pub fn datlat(&self) -> DATLAT_R[src]
Bits 24:27 - DATLAT
pub fn clkdiv(&self) -> CLKDIV_R[src]
Bits 20:23 - CLKDIV
pub fn datast(&self) -> DATAST_R[src]
Bits 8:15 - DATAST
pub fn addhld(&self) -> ADDHLD_R[src]
Bits 4:7 - ADDHLD
pub fn addset(&self) -> ADDSET_R[src]
Bits 0:3 - ADDSET
pub fn busturn(&self) -> BUSTURN_R[src]
Bits 16:19 - Bus turnaround phase duration
impl R<u8, MODER15_A>[src]
pub fn variant(&self) -> MODER15_A[src]
Get enumerated values variant
pub fn is_input(&self) -> bool[src]
Checks if the value of the field is INPUT
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
pub fn is_alternate(&self) -> bool[src]
Checks if the value of the field is ALTERNATE
pub fn is_analog(&self) -> bool[src]
Checks if the value of the field is ANALOG
impl R<u32, Reg<u32, _MODER>>[src]
pub fn moder15(&self) -> MODER15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&self) -> MODER14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&self) -> MODER13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&self) -> MODER12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&self) -> MODER11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&self) -> MODER10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&self) -> MODER9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&self) -> MODER8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&self) -> MODER7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&self) -> MODER6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&self) -> MODER5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&self) -> MODER4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&self) -> MODER3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&self) -> MODER2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&self) -> MODER1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&self) -> MODER0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, OT15_A>[src]
pub fn variant(&self) -> OT15_A[src]
Get enumerated values variant
pub fn is_push_pull(&self) -> bool[src]
Checks if the value of the field is PUSHPULL
pub fn is_open_drain(&self) -> bool[src]
Checks if the value of the field is OPENDRAIN
impl R<u32, Reg<u32, _OTYPER>>[src]
pub fn ot15(&self) -> OT15_R[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&self) -> OT14_R[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&self) -> OT13_R[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&self) -> OT12_R[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&self) -> OT11_R[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&self) -> OT10_R[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&self) -> OT9_R[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&self) -> OT8_R[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&self) -> OT7_R[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&self) -> OT6_R[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&self) -> OT5_R[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&self) -> OT4_R[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&self) -> OT3_R[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&self) -> OT2_R[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&self) -> OT1_R[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&self) -> OT0_R[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl R<u8, OSPEEDR15_A>[src]
pub fn variant(&self) -> OSPEEDR15_A[src]
Get enumerated values variant
pub fn is_low_speed(&self) -> bool[src]
Checks if the value of the field is LOWSPEED
pub fn is_medium_speed(&self) -> bool[src]
Checks if the value of the field is MEDIUMSPEED
pub fn is_high_speed(&self) -> bool[src]
Checks if the value of the field is HIGHSPEED
pub fn is_very_high_speed(&self) -> bool[src]
Checks if the value of the field is VERYHIGHSPEED
impl R<u32, Reg<u32, _OSPEEDR>>[src]
pub fn ospeedr15(&self) -> OSPEEDR15_R[src]
Bits 30:31 - OSPEEDR15
pub fn ospeedr14(&self) -> OSPEEDR14_R[src]
Bits 28:29 - OSPEEDR14
pub fn ospeedr13(&self) -> OSPEEDR13_R[src]
Bits 26:27 - OSPEEDR13
pub fn ospeedr12(&self) -> OSPEEDR12_R[src]
Bits 24:25 - OSPEEDR12
pub fn ospeedr11(&self) -> OSPEEDR11_R[src]
Bits 22:23 - OSPEEDR11
pub fn ospeedr10(&self) -> OSPEEDR10_R[src]
Bits 20:21 - OSPEEDR10
pub fn ospeedr9(&self) -> OSPEEDR9_R[src]
Bits 18:19 - OSPEEDR9
pub fn ospeedr8(&self) -> OSPEEDR8_R[src]
Bits 16:17 - OSPEEDR8
pub fn ospeedr7(&self) -> OSPEEDR7_R[src]
Bits 14:15 - OSPEEDR7
pub fn ospeedr6(&self) -> OSPEEDR6_R[src]
Bits 12:13 - OSPEEDR6
pub fn ospeedr5(&self) -> OSPEEDR5_R[src]
Bits 10:11 - OSPEEDR5
pub fn ospeedr4(&self) -> OSPEEDR4_R[src]
Bits 8:9 - OSPEEDR4
pub fn ospeedr3(&self) -> OSPEEDR3_R[src]
Bits 6:7 - OSPEEDR3
pub fn ospeedr2(&self) -> OSPEEDR2_R[src]
Bits 4:5 - OSPEEDR2
pub fn ospeedr1(&self) -> OSPEEDR1_R[src]
Bits 2:3 - OSPEEDR1
pub fn ospeedr0(&self) -> OSPEEDR0_R[src]
Bits 0:1 - OSPEEDR0
impl R<u8, PUPDR15_A>[src]
pub fn variant(&self) -> Variant<u8, PUPDR15_A>[src]
Get enumerated values variant
pub fn is_floating(&self) -> bool[src]
Checks if the value of the field is FLOATING
pub fn is_pull_up(&self) -> bool[src]
Checks if the value of the field is PULLUP
pub fn is_pull_down(&self) -> bool[src]
Checks if the value of the field is PULLDOWN
impl R<u32, Reg<u32, _PUPDR>>[src]
pub fn pupdr15(&self) -> PUPDR15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&self) -> PUPDR14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&self) -> PUPDR13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&self) -> PUPDR12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&self) -> PUPDR11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&self) -> PUPDR10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&self) -> PUPDR9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&self) -> PUPDR8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&self) -> PUPDR7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&self) -> PUPDR6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&self) -> PUPDR5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&self) -> PUPDR4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&self) -> PUPDR3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&self) -> PUPDR2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&self) -> PUPDR1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&self) -> PUPDR0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, IDR15_A>[src]
pub fn variant(&self) -> IDR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _IDR>>[src]
pub fn idr15(&self) -> IDR15_R[src]
Bit 15 - Port input data (y = 0..15)
pub fn idr14(&self) -> IDR14_R[src]
Bit 14 - Port input data (y = 0..15)
pub fn idr13(&self) -> IDR13_R[src]
Bit 13 - Port input data (y = 0..15)
pub fn idr12(&self) -> IDR12_R[src]
Bit 12 - Port input data (y = 0..15)
pub fn idr11(&self) -> IDR11_R[src]
Bit 11 - Port input data (y = 0..15)
pub fn idr10(&self) -> IDR10_R[src]
Bit 10 - Port input data (y = 0..15)
pub fn idr9(&self) -> IDR9_R[src]
Bit 9 - Port input data (y = 0..15)
pub fn idr8(&self) -> IDR8_R[src]
Bit 8 - Port input data (y = 0..15)
pub fn idr7(&self) -> IDR7_R[src]
Bit 7 - Port input data (y = 0..15)
pub fn idr6(&self) -> IDR6_R[src]
Bit 6 - Port input data (y = 0..15)
pub fn idr5(&self) -> IDR5_R[src]
Bit 5 - Port input data (y = 0..15)
pub fn idr4(&self) -> IDR4_R[src]
Bit 4 - Port input data (y = 0..15)
pub fn idr3(&self) -> IDR3_R[src]
Bit 3 - Port input data (y = 0..15)
pub fn idr2(&self) -> IDR2_R[src]
Bit 2 - Port input data (y = 0..15)
pub fn idr1(&self) -> IDR1_R[src]
Bit 1 - Port input data (y = 0..15)
pub fn idr0(&self) -> IDR0_R[src]
Bit 0 - Port input data (y = 0..15)
impl R<bool, ODR15_A>[src]
pub fn variant(&self) -> ODR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _ODR>>[src]
pub fn odr15(&self) -> ODR15_R[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&self) -> ODR14_R[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&self) -> ODR13_R[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&self) -> ODR12_R[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&self) -> ODR11_R[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&self) -> ODR10_R[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&self) -> ODR9_R[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&self) -> ODR8_R[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&self) -> ODR7_R[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&self) -> ODR6_R[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&self) -> ODR5_R[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&self) -> ODR4_R[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&self) -> ODR3_R[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&self) -> ODR2_R[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&self) -> ODR1_R[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&self) -> ODR0_R[src]
Bit 0 - Port output data (y = 0..15)
impl R<bool, LCKK_A>[src]
pub fn variant(&self) -> LCKK_A[src]
Get enumerated values variant
pub fn is_not_active(&self) -> bool[src]
Checks if the value of the field is NOTACTIVE
pub fn is_active(&self) -> bool[src]
Checks if the value of the field is ACTIVE
impl R<bool, LCK15_A>[src]
pub fn variant(&self) -> LCK15_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, LCK9_A>[src]
pub fn variant(&self) -> LCK9_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<u32, Reg<u32, _LCKR>>[src]
pub fn lckk(&self) -> LCKK_R[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&self) -> LCK15_R[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&self) -> LCK14_R[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&self) -> LCK13_R[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&self) -> LCK12_R[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&self) -> LCK11_R[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&self) -> LCK10_R[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&self) -> LCK9_R[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&self) -> LCK8_R[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&self) -> LCK7_R[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&self) -> LCK6_R[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&self) -> LCK5_R[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&self) -> LCK4_R[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&self) -> LCK3_R[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&self) -> LCK2_R[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&self) -> LCK1_R[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&self) -> LCK0_R[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl R<u8, AFRL7_A>[src]
pub fn variant(&self) -> AFRL7_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRL>>[src]
pub fn afrl7(&self) -> AFRL7_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&self) -> AFRL6_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&self) -> AFRL5_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&self) -> AFRL4_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&self) -> AFRL3_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&self) -> AFRL2_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&self) -> AFRL1_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&self) -> AFRL0_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl R<u8, AFRH15_A>[src]
pub fn variant(&self) -> AFRH15_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRH>>[src]
pub fn afrh15(&self) -> AFRH15_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&self) -> AFRH14_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&self) -> AFRH13_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&self) -> AFRH12_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&self) -> AFRH11_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&self) -> AFRH10_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&self) -> AFRH9_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&self) -> AFRH8_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl R<u8, MODER15_A>[src]
pub fn variant(&self) -> MODER15_A[src]
Get enumerated values variant
pub fn is_input(&self) -> bool[src]
Checks if the value of the field is INPUT
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
pub fn is_alternate(&self) -> bool[src]
Checks if the value of the field is ALTERNATE
pub fn is_analog(&self) -> bool[src]
Checks if the value of the field is ANALOG
impl R<u32, Reg<u32, _MODER>>[src]
pub fn moder15(&self) -> MODER15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&self) -> MODER14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&self) -> MODER13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&self) -> MODER12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&self) -> MODER11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&self) -> MODER10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&self) -> MODER9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&self) -> MODER8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&self) -> MODER7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&self) -> MODER6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&self) -> MODER5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&self) -> MODER4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&self) -> MODER3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&self) -> MODER2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&self) -> MODER1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&self) -> MODER0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, OT15_A>[src]
pub fn variant(&self) -> OT15_A[src]
Get enumerated values variant
pub fn is_push_pull(&self) -> bool[src]
Checks if the value of the field is PUSHPULL
pub fn is_open_drain(&self) -> bool[src]
Checks if the value of the field is OPENDRAIN
impl R<u32, Reg<u32, _OTYPER>>[src]
pub fn ot15(&self) -> OT15_R[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&self) -> OT14_R[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&self) -> OT13_R[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&self) -> OT12_R[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&self) -> OT11_R[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&self) -> OT10_R[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&self) -> OT9_R[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&self) -> OT8_R[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&self) -> OT7_R[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&self) -> OT6_R[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&self) -> OT5_R[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&self) -> OT4_R[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&self) -> OT3_R[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&self) -> OT2_R[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&self) -> OT1_R[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&self) -> OT0_R[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl R<u8, OSPEEDR15_A>[src]
pub fn variant(&self) -> OSPEEDR15_A[src]
Get enumerated values variant
pub fn is_low_speed(&self) -> bool[src]
Checks if the value of the field is LOWSPEED
pub fn is_medium_speed(&self) -> bool[src]
Checks if the value of the field is MEDIUMSPEED
pub fn is_high_speed(&self) -> bool[src]
Checks if the value of the field is HIGHSPEED
pub fn is_very_high_speed(&self) -> bool[src]
Checks if the value of the field is VERYHIGHSPEED
impl R<u32, Reg<u32, _OSPEEDR>>[src]
pub fn ospeedr15(&self) -> OSPEEDR15_R[src]
Bits 30:31 - OSPEEDR15
pub fn ospeedr14(&self) -> OSPEEDR14_R[src]
Bits 28:29 - OSPEEDR14
pub fn ospeedr13(&self) -> OSPEEDR13_R[src]
Bits 26:27 - OSPEEDR13
pub fn ospeedr12(&self) -> OSPEEDR12_R[src]
Bits 24:25 - OSPEEDR12
pub fn ospeedr11(&self) -> OSPEEDR11_R[src]
Bits 22:23 - OSPEEDR11
pub fn ospeedr10(&self) -> OSPEEDR10_R[src]
Bits 20:21 - OSPEEDR10
pub fn ospeedr9(&self) -> OSPEEDR9_R[src]
Bits 18:19 - OSPEEDR9
pub fn ospeedr8(&self) -> OSPEEDR8_R[src]
Bits 16:17 - OSPEEDR8
pub fn ospeedr7(&self) -> OSPEEDR7_R[src]
Bits 14:15 - OSPEEDR7
pub fn ospeedr6(&self) -> OSPEEDR6_R[src]
Bits 12:13 - OSPEEDR6
pub fn ospeedr5(&self) -> OSPEEDR5_R[src]
Bits 10:11 - OSPEEDR5
pub fn ospeedr4(&self) -> OSPEEDR4_R[src]
Bits 8:9 - OSPEEDR4
pub fn ospeedr3(&self) -> OSPEEDR3_R[src]
Bits 6:7 - OSPEEDR3
pub fn ospeedr2(&self) -> OSPEEDR2_R[src]
Bits 4:5 - OSPEEDR2
pub fn ospeedr1(&self) -> OSPEEDR1_R[src]
Bits 2:3 - OSPEEDR1
pub fn ospeedr0(&self) -> OSPEEDR0_R[src]
Bits 0:1 - OSPEEDR0
impl R<u8, PUPDR15_A>[src]
pub fn variant(&self) -> Variant<u8, PUPDR15_A>[src]
Get enumerated values variant
pub fn is_floating(&self) -> bool[src]
Checks if the value of the field is FLOATING
pub fn is_pull_up(&self) -> bool[src]
Checks if the value of the field is PULLUP
pub fn is_pull_down(&self) -> bool[src]
Checks if the value of the field is PULLDOWN
impl R<u32, Reg<u32, _PUPDR>>[src]
pub fn pupdr15(&self) -> PUPDR15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&self) -> PUPDR14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&self) -> PUPDR13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&self) -> PUPDR12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&self) -> PUPDR11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&self) -> PUPDR10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&self) -> PUPDR9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&self) -> PUPDR8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&self) -> PUPDR7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&self) -> PUPDR6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&self) -> PUPDR5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&self) -> PUPDR4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&self) -> PUPDR3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&self) -> PUPDR2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&self) -> PUPDR1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&self) -> PUPDR0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, IDR15_A>[src]
pub fn variant(&self) -> IDR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _IDR>>[src]
pub fn idr15(&self) -> IDR15_R[src]
Bit 15 - Port input data (y = 0..15)
pub fn idr14(&self) -> IDR14_R[src]
Bit 14 - Port input data (y = 0..15)
pub fn idr13(&self) -> IDR13_R[src]
Bit 13 - Port input data (y = 0..15)
pub fn idr12(&self) -> IDR12_R[src]
Bit 12 - Port input data (y = 0..15)
pub fn idr11(&self) -> IDR11_R[src]
Bit 11 - Port input data (y = 0..15)
pub fn idr10(&self) -> IDR10_R[src]
Bit 10 - Port input data (y = 0..15)
pub fn idr9(&self) -> IDR9_R[src]
Bit 9 - Port input data (y = 0..15)
pub fn idr8(&self) -> IDR8_R[src]
Bit 8 - Port input data (y = 0..15)
pub fn idr7(&self) -> IDR7_R[src]
Bit 7 - Port input data (y = 0..15)
pub fn idr6(&self) -> IDR6_R[src]
Bit 6 - Port input data (y = 0..15)
pub fn idr5(&self) -> IDR5_R[src]
Bit 5 - Port input data (y = 0..15)
pub fn idr4(&self) -> IDR4_R[src]
Bit 4 - Port input data (y = 0..15)
pub fn idr3(&self) -> IDR3_R[src]
Bit 3 - Port input data (y = 0..15)
pub fn idr2(&self) -> IDR2_R[src]
Bit 2 - Port input data (y = 0..15)
pub fn idr1(&self) -> IDR1_R[src]
Bit 1 - Port input data (y = 0..15)
pub fn idr0(&self) -> IDR0_R[src]
Bit 0 - Port input data (y = 0..15)
impl R<bool, ODR15_A>[src]
pub fn variant(&self) -> ODR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _ODR>>[src]
pub fn odr15(&self) -> ODR15_R[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&self) -> ODR14_R[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&self) -> ODR13_R[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&self) -> ODR12_R[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&self) -> ODR11_R[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&self) -> ODR10_R[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&self) -> ODR9_R[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&self) -> ODR8_R[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&self) -> ODR7_R[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&self) -> ODR6_R[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&self) -> ODR5_R[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&self) -> ODR4_R[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&self) -> ODR3_R[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&self) -> ODR2_R[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&self) -> ODR1_R[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&self) -> ODR0_R[src]
Bit 0 - Port output data (y = 0..15)
impl R<bool, LCKK_A>[src]
pub fn variant(&self) -> LCKK_A[src]
Get enumerated values variant
pub fn is_not_active(&self) -> bool[src]
Checks if the value of the field is NOTACTIVE
pub fn is_active(&self) -> bool[src]
Checks if the value of the field is ACTIVE
impl R<bool, LCK15_A>[src]
pub fn variant(&self) -> LCK15_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, LCK9_A>[src]
pub fn variant(&self) -> LCK9_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<u32, Reg<u32, _LCKR>>[src]
pub fn lckk(&self) -> LCKK_R[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&self) -> LCK15_R[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&self) -> LCK14_R[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&self) -> LCK13_R[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&self) -> LCK12_R[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&self) -> LCK11_R[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&self) -> LCK10_R[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&self) -> LCK9_R[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&self) -> LCK8_R[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&self) -> LCK7_R[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&self) -> LCK6_R[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&self) -> LCK5_R[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&self) -> LCK4_R[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&self) -> LCK3_R[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&self) -> LCK2_R[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&self) -> LCK1_R[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&self) -> LCK0_R[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl R<u8, AFRL7_A>[src]
pub fn variant(&self) -> AFRL7_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRL>>[src]
pub fn afrl7(&self) -> AFRL7_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&self) -> AFRL6_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&self) -> AFRL5_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&self) -> AFRL4_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&self) -> AFRL3_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&self) -> AFRL2_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&self) -> AFRL1_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&self) -> AFRL0_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl R<u8, AFRH15_A>[src]
pub fn variant(&self) -> AFRH15_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRH>>[src]
pub fn afrh15(&self) -> AFRH15_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&self) -> AFRH14_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&self) -> AFRH13_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&self) -> AFRH12_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&self) -> AFRH11_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&self) -> AFRH10_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&self) -> AFRH9_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&self) -> AFRH8_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl R<u8, MODER15_A>[src]
pub fn variant(&self) -> MODER15_A[src]
Get enumerated values variant
pub fn is_input(&self) -> bool[src]
Checks if the value of the field is INPUT
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
pub fn is_alternate(&self) -> bool[src]
Checks if the value of the field is ALTERNATE
pub fn is_analog(&self) -> bool[src]
Checks if the value of the field is ANALOG
impl R<u32, Reg<u32, _MODER>>[src]
pub fn moder15(&self) -> MODER15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn moder14(&self) -> MODER14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn moder13(&self) -> MODER13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn moder12(&self) -> MODER12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn moder11(&self) -> MODER11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn moder10(&self) -> MODER10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn moder9(&self) -> MODER9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn moder8(&self) -> MODER8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn moder7(&self) -> MODER7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn moder6(&self) -> MODER6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn moder5(&self) -> MODER5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn moder4(&self) -> MODER4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn moder3(&self) -> MODER3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn moder2(&self) -> MODER2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn moder1(&self) -> MODER1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn moder0(&self) -> MODER0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, OT15_A>[src]
pub fn variant(&self) -> OT15_A[src]
Get enumerated values variant
pub fn is_push_pull(&self) -> bool[src]
Checks if the value of the field is PUSHPULL
pub fn is_open_drain(&self) -> bool[src]
Checks if the value of the field is OPENDRAIN
impl R<u32, Reg<u32, _OTYPER>>[src]
pub fn ot15(&self) -> OT15_R[src]
Bit 15 - Port x configuration bits (y = 0..15)
pub fn ot14(&self) -> OT14_R[src]
Bit 14 - Port x configuration bits (y = 0..15)
pub fn ot13(&self) -> OT13_R[src]
Bit 13 - Port x configuration bits (y = 0..15)
pub fn ot12(&self) -> OT12_R[src]
Bit 12 - Port x configuration bits (y = 0..15)
pub fn ot11(&self) -> OT11_R[src]
Bit 11 - Port x configuration bits (y = 0..15)
pub fn ot10(&self) -> OT10_R[src]
Bit 10 - Port x configuration bits (y = 0..15)
pub fn ot9(&self) -> OT9_R[src]
Bit 9 - Port x configuration bits (y = 0..15)
pub fn ot8(&self) -> OT8_R[src]
Bit 8 - Port x configuration bits (y = 0..15)
pub fn ot7(&self) -> OT7_R[src]
Bit 7 - Port x configuration bits (y = 0..15)
pub fn ot6(&self) -> OT6_R[src]
Bit 6 - Port x configuration bits (y = 0..15)
pub fn ot5(&self) -> OT5_R[src]
Bit 5 - Port x configuration bits (y = 0..15)
pub fn ot4(&self) -> OT4_R[src]
Bit 4 - Port x configuration bits (y = 0..15)
pub fn ot3(&self) -> OT3_R[src]
Bit 3 - Port x configuration bits (y = 0..15)
pub fn ot2(&self) -> OT2_R[src]
Bit 2 - Port x configuration bits (y = 0..15)
pub fn ot1(&self) -> OT1_R[src]
Bit 1 - Port x configuration bits (y = 0..15)
pub fn ot0(&self) -> OT0_R[src]
Bit 0 - Port x configuration bits (y = 0..15)
impl R<u8, OSPEEDR15_A>[src]
pub fn variant(&self) -> OSPEEDR15_A[src]
Get enumerated values variant
pub fn is_low_speed(&self) -> bool[src]
Checks if the value of the field is LOWSPEED
pub fn is_medium_speed(&self) -> bool[src]
Checks if the value of the field is MEDIUMSPEED
pub fn is_high_speed(&self) -> bool[src]
Checks if the value of the field is HIGHSPEED
pub fn is_very_high_speed(&self) -> bool[src]
Checks if the value of the field is VERYHIGHSPEED
impl R<u32, Reg<u32, _OSPEEDR>>[src]
pub fn ospeedr15(&self) -> OSPEEDR15_R[src]
Bits 30:31 - OSPEEDR15
pub fn ospeedr14(&self) -> OSPEEDR14_R[src]
Bits 28:29 - OSPEEDR14
pub fn ospeedr13(&self) -> OSPEEDR13_R[src]
Bits 26:27 - OSPEEDR13
pub fn ospeedr12(&self) -> OSPEEDR12_R[src]
Bits 24:25 - OSPEEDR12
pub fn ospeedr11(&self) -> OSPEEDR11_R[src]
Bits 22:23 - OSPEEDR11
pub fn ospeedr10(&self) -> OSPEEDR10_R[src]
Bits 20:21 - OSPEEDR10
pub fn ospeedr9(&self) -> OSPEEDR9_R[src]
Bits 18:19 - OSPEEDR9
pub fn ospeedr8(&self) -> OSPEEDR8_R[src]
Bits 16:17 - OSPEEDR8
pub fn ospeedr7(&self) -> OSPEEDR7_R[src]
Bits 14:15 - OSPEEDR7
pub fn ospeedr6(&self) -> OSPEEDR6_R[src]
Bits 12:13 - OSPEEDR6
pub fn ospeedr5(&self) -> OSPEEDR5_R[src]
Bits 10:11 - OSPEEDR5
pub fn ospeedr4(&self) -> OSPEEDR4_R[src]
Bits 8:9 - OSPEEDR4
pub fn ospeedr3(&self) -> OSPEEDR3_R[src]
Bits 6:7 - OSPEEDR3
pub fn ospeedr2(&self) -> OSPEEDR2_R[src]
Bits 4:5 - OSPEEDR2
pub fn ospeedr1(&self) -> OSPEEDR1_R[src]
Bits 2:3 - OSPEEDR1
pub fn ospeedr0(&self) -> OSPEEDR0_R[src]
Bits 0:1 - OSPEEDR0
impl R<u8, PUPDR15_A>[src]
pub fn variant(&self) -> Variant<u8, PUPDR15_A>[src]
Get enumerated values variant
pub fn is_floating(&self) -> bool[src]
Checks if the value of the field is FLOATING
pub fn is_pull_up(&self) -> bool[src]
Checks if the value of the field is PULLUP
pub fn is_pull_down(&self) -> bool[src]
Checks if the value of the field is PULLDOWN
impl R<u32, Reg<u32, _PUPDR>>[src]
pub fn pupdr15(&self) -> PUPDR15_R[src]
Bits 30:31 - Port x configuration bits (y = 0..15)
pub fn pupdr14(&self) -> PUPDR14_R[src]
Bits 28:29 - Port x configuration bits (y = 0..15)
pub fn pupdr13(&self) -> PUPDR13_R[src]
Bits 26:27 - Port x configuration bits (y = 0..15)
pub fn pupdr12(&self) -> PUPDR12_R[src]
Bits 24:25 - Port x configuration bits (y = 0..15)
pub fn pupdr11(&self) -> PUPDR11_R[src]
Bits 22:23 - Port x configuration bits (y = 0..15)
pub fn pupdr10(&self) -> PUPDR10_R[src]
Bits 20:21 - Port x configuration bits (y = 0..15)
pub fn pupdr9(&self) -> PUPDR9_R[src]
Bits 18:19 - Port x configuration bits (y = 0..15)
pub fn pupdr8(&self) -> PUPDR8_R[src]
Bits 16:17 - Port x configuration bits (y = 0..15)
pub fn pupdr7(&self) -> PUPDR7_R[src]
Bits 14:15 - Port x configuration bits (y = 0..15)
pub fn pupdr6(&self) -> PUPDR6_R[src]
Bits 12:13 - Port x configuration bits (y = 0..15)
pub fn pupdr5(&self) -> PUPDR5_R[src]
Bits 10:11 - Port x configuration bits (y = 0..15)
pub fn pupdr4(&self) -> PUPDR4_R[src]
Bits 8:9 - Port x configuration bits (y = 0..15)
pub fn pupdr3(&self) -> PUPDR3_R[src]
Bits 6:7 - Port x configuration bits (y = 0..15)
pub fn pupdr2(&self) -> PUPDR2_R[src]
Bits 4:5 - Port x configuration bits (y = 0..15)
pub fn pupdr1(&self) -> PUPDR1_R[src]
Bits 2:3 - Port x configuration bits (y = 0..15)
pub fn pupdr0(&self) -> PUPDR0_R[src]
Bits 0:1 - Port x configuration bits (y = 0..15)
impl R<bool, IDR15_A>[src]
pub fn variant(&self) -> IDR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _IDR>>[src]
pub fn idr15(&self) -> IDR15_R[src]
Bit 15 - Port input data (y = 0..15)
pub fn idr14(&self) -> IDR14_R[src]
Bit 14 - Port input data (y = 0..15)
pub fn idr13(&self) -> IDR13_R[src]
Bit 13 - Port input data (y = 0..15)
pub fn idr12(&self) -> IDR12_R[src]
Bit 12 - Port input data (y = 0..15)
pub fn idr11(&self) -> IDR11_R[src]
Bit 11 - Port input data (y = 0..15)
pub fn idr10(&self) -> IDR10_R[src]
Bit 10 - Port input data (y = 0..15)
pub fn idr9(&self) -> IDR9_R[src]
Bit 9 - Port input data (y = 0..15)
pub fn idr8(&self) -> IDR8_R[src]
Bit 8 - Port input data (y = 0..15)
pub fn idr7(&self) -> IDR7_R[src]
Bit 7 - Port input data (y = 0..15)
pub fn idr6(&self) -> IDR6_R[src]
Bit 6 - Port input data (y = 0..15)
pub fn idr5(&self) -> IDR5_R[src]
Bit 5 - Port input data (y = 0..15)
pub fn idr4(&self) -> IDR4_R[src]
Bit 4 - Port input data (y = 0..15)
pub fn idr3(&self) -> IDR3_R[src]
Bit 3 - Port input data (y = 0..15)
pub fn idr2(&self) -> IDR2_R[src]
Bit 2 - Port input data (y = 0..15)
pub fn idr1(&self) -> IDR1_R[src]
Bit 1 - Port input data (y = 0..15)
pub fn idr0(&self) -> IDR0_R[src]
Bit 0 - Port input data (y = 0..15)
impl R<bool, ODR15_A>[src]
pub fn variant(&self) -> ODR15_A[src]
Get enumerated values variant
pub fn is_high(&self) -> bool[src]
Checks if the value of the field is HIGH
pub fn is_low(&self) -> bool[src]
Checks if the value of the field is LOW
impl R<u32, Reg<u32, _ODR>>[src]
pub fn odr15(&self) -> ODR15_R[src]
Bit 15 - Port output data (y = 0..15)
pub fn odr14(&self) -> ODR14_R[src]
Bit 14 - Port output data (y = 0..15)
pub fn odr13(&self) -> ODR13_R[src]
Bit 13 - Port output data (y = 0..15)
pub fn odr12(&self) -> ODR12_R[src]
Bit 12 - Port output data (y = 0..15)
pub fn odr11(&self) -> ODR11_R[src]
Bit 11 - Port output data (y = 0..15)
pub fn odr10(&self) -> ODR10_R[src]
Bit 10 - Port output data (y = 0..15)
pub fn odr9(&self) -> ODR9_R[src]
Bit 9 - Port output data (y = 0..15)
pub fn odr8(&self) -> ODR8_R[src]
Bit 8 - Port output data (y = 0..15)
pub fn odr7(&self) -> ODR7_R[src]
Bit 7 - Port output data (y = 0..15)
pub fn odr6(&self) -> ODR6_R[src]
Bit 6 - Port output data (y = 0..15)
pub fn odr5(&self) -> ODR5_R[src]
Bit 5 - Port output data (y = 0..15)
pub fn odr4(&self) -> ODR4_R[src]
Bit 4 - Port output data (y = 0..15)
pub fn odr3(&self) -> ODR3_R[src]
Bit 3 - Port output data (y = 0..15)
pub fn odr2(&self) -> ODR2_R[src]
Bit 2 - Port output data (y = 0..15)
pub fn odr1(&self) -> ODR1_R[src]
Bit 1 - Port output data (y = 0..15)
pub fn odr0(&self) -> ODR0_R[src]
Bit 0 - Port output data (y = 0..15)
impl R<bool, LCKK_A>[src]
pub fn variant(&self) -> LCKK_A[src]
Get enumerated values variant
pub fn is_not_active(&self) -> bool[src]
Checks if the value of the field is NOTACTIVE
pub fn is_active(&self) -> bool[src]
Checks if the value of the field is ACTIVE
impl R<bool, LCK15_A>[src]
pub fn variant(&self) -> LCK15_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, LCK9_A>[src]
pub fn variant(&self) -> LCK9_A[src]
Get enumerated values variant
pub fn is_unlocked(&self) -> bool[src]
Checks if the value of the field is UNLOCKED
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<u32, Reg<u32, _LCKR>>[src]
pub fn lckk(&self) -> LCKK_R[src]
Bit 16 - Port x lock bit y (y= 0..15)
pub fn lck15(&self) -> LCK15_R[src]
Bit 15 - Port x lock bit y (y= 0..15)
pub fn lck14(&self) -> LCK14_R[src]
Bit 14 - Port x lock bit y (y= 0..15)
pub fn lck13(&self) -> LCK13_R[src]
Bit 13 - Port x lock bit y (y= 0..15)
pub fn lck12(&self) -> LCK12_R[src]
Bit 12 - Port x lock bit y (y= 0..15)
pub fn lck11(&self) -> LCK11_R[src]
Bit 11 - Port x lock bit y (y= 0..15)
pub fn lck10(&self) -> LCK10_R[src]
Bit 10 - Port x lock bit y (y= 0..15)
pub fn lck9(&self) -> LCK9_R[src]
Bit 9 - Port x lock bit y (y= 0..15)
pub fn lck8(&self) -> LCK8_R[src]
Bit 8 - Port x lock bit y (y= 0..15)
pub fn lck7(&self) -> LCK7_R[src]
Bit 7 - Port x lock bit y (y= 0..15)
pub fn lck6(&self) -> LCK6_R[src]
Bit 6 - Port x lock bit y (y= 0..15)
pub fn lck5(&self) -> LCK5_R[src]
Bit 5 - Port x lock bit y (y= 0..15)
pub fn lck4(&self) -> LCK4_R[src]
Bit 4 - Port x lock bit y (y= 0..15)
pub fn lck3(&self) -> LCK3_R[src]
Bit 3 - Port x lock bit y (y= 0..15)
pub fn lck2(&self) -> LCK2_R[src]
Bit 2 - Port x lock bit y (y= 0..15)
pub fn lck1(&self) -> LCK1_R[src]
Bit 1 - Port x lock bit y (y= 0..15)
pub fn lck0(&self) -> LCK0_R[src]
Bit 0 - Port x lock bit y (y= 0..15)
impl R<u8, AFRL7_A>[src]
pub fn variant(&self) -> AFRL7_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRL>>[src]
pub fn afrl7(&self) -> AFRL7_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl6(&self) -> AFRL6_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl5(&self) -> AFRL5_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl4(&self) -> AFRL4_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl3(&self) -> AFRL3_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl2(&self) -> AFRL2_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl1(&self) -> AFRL1_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 0..7)
pub fn afrl0(&self) -> AFRL0_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 0..7)
impl R<u8, AFRH15_A>[src]
pub fn variant(&self) -> AFRH15_A[src]
Get enumerated values variant
pub fn is_af0(&self) -> bool[src]
Checks if the value of the field is AF0
pub fn is_af1(&self) -> bool[src]
Checks if the value of the field is AF1
pub fn is_af2(&self) -> bool[src]
Checks if the value of the field is AF2
pub fn is_af3(&self) -> bool[src]
Checks if the value of the field is AF3
pub fn is_af4(&self) -> bool[src]
Checks if the value of the field is AF4
pub fn is_af5(&self) -> bool[src]
Checks if the value of the field is AF5
pub fn is_af6(&self) -> bool[src]
Checks if the value of the field is AF6
pub fn is_af7(&self) -> bool[src]
Checks if the value of the field is AF7
pub fn is_af8(&self) -> bool[src]
Checks if the value of the field is AF8
pub fn is_af9(&self) -> bool[src]
Checks if the value of the field is AF9
pub fn is_af10(&self) -> bool[src]
Checks if the value of the field is AF10
pub fn is_af11(&self) -> bool[src]
Checks if the value of the field is AF11
pub fn is_af12(&self) -> bool[src]
Checks if the value of the field is AF12
pub fn is_af13(&self) -> bool[src]
Checks if the value of the field is AF13
pub fn is_af14(&self) -> bool[src]
Checks if the value of the field is AF14
pub fn is_af15(&self) -> bool[src]
Checks if the value of the field is AF15
impl R<u32, Reg<u32, _AFRH>>[src]
pub fn afrh15(&self) -> AFRH15_R[src]
Bits 28:31 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh14(&self) -> AFRH14_R[src]
Bits 24:27 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh13(&self) -> AFRH13_R[src]
Bits 20:23 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh12(&self) -> AFRH12_R[src]
Bits 16:19 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh11(&self) -> AFRH11_R[src]
Bits 12:15 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh10(&self) -> AFRH10_R[src]
Bits 8:11 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh9(&self) -> AFRH9_R[src]
Bits 4:7 - Alternate function selection for port x bit y (y = 8..15)
pub fn afrh8(&self) -> AFRH8_R[src]
Bits 0:3 - Alternate function selection for port x bit y (y = 8..15)
impl R<bool, SWRST_A>[src]
pub fn variant(&self) -> SWRST_A[src]
Get enumerated values variant
pub fn is_not_reset(&self) -> bool[src]
Checks if the value of the field is NOTRESET
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<bool, ALERT_A>[src]
pub fn variant(&self) -> ALERT_A[src]
Get enumerated values variant
pub fn is_release(&self) -> bool[src]
Checks if the value of the field is RELEASE
pub fn is_drive(&self) -> bool[src]
Checks if the value of the field is DRIVE
impl R<bool, PEC_A>[src]
pub fn variant(&self) -> PEC_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, POS_A>[src]
pub fn variant(&self) -> POS_A[src]
Get enumerated values variant
pub fn is_current(&self) -> bool[src]
Checks if the value of the field is CURRENT
pub fn is_next(&self) -> bool[src]
Checks if the value of the field is NEXT
impl R<bool, ACK_A>[src]
pub fn variant(&self) -> ACK_A[src]
Get enumerated values variant
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_ack(&self) -> bool[src]
Checks if the value of the field is ACK
impl R<bool, STOP_A>[src]
pub fn variant(&self) -> STOP_A[src]
Get enumerated values variant
pub fn is_no_stop(&self) -> bool[src]
Checks if the value of the field is NOSTOP
pub fn is_stop(&self) -> bool[src]
Checks if the value of the field is STOP
impl R<bool, START_A>[src]
pub fn variant(&self) -> START_A[src]
Get enumerated values variant
pub fn is_no_start(&self) -> bool[src]
Checks if the value of the field is NOSTART
pub fn is_start(&self) -> bool[src]
Checks if the value of the field is START
impl R<bool, NOSTRETCH_A>[src]
pub fn variant(&self) -> NOSTRETCH_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, ENGC_A>[src]
pub fn variant(&self) -> ENGC_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ENPEC_A>[src]
pub fn variant(&self) -> ENPEC_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ENARP_A>[src]
pub fn variant(&self) -> ENARP_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, SMBTYPE_A>[src]
pub fn variant(&self) -> SMBTYPE_A[src]
Get enumerated values variant
pub fn is_device(&self) -> bool[src]
Checks if the value of the field is DEVICE
pub fn is_host(&self) -> bool[src]
Checks if the value of the field is HOST
impl R<bool, SMBUS_A>[src]
pub fn variant(&self) -> SMBUS_A[src]
Get enumerated values variant
pub fn is_i2c(&self) -> bool[src]
Checks if the value of the field is I2C
pub fn is_smbus(&self) -> bool[src]
Checks if the value of the field is SMBUS
impl R<bool, PE_A>[src]
pub fn variant(&self) -> PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn swrst(&self) -> SWRST_R[src]
Bit 15 - Software reset
pub fn alert(&self) -> ALERT_R[src]
Bit 13 - SMBus alert
pub fn pec(&self) -> PEC_R[src]
Bit 12 - Packet error checking
pub fn pos(&self) -> POS_R[src]
Bit 11 - Acknowledge/PEC Position (for data reception)
pub fn ack(&self) -> ACK_R[src]
Bit 10 - Acknowledge enable
pub fn stop(&self) -> STOP_R[src]
Bit 9 - Stop generation
pub fn start(&self) -> START_R[src]
Bit 8 - Start generation
pub fn nostretch(&self) -> NOSTRETCH_R[src]
Bit 7 - Clock stretching disable (Slave mode)
pub fn engc(&self) -> ENGC_R[src]
Bit 6 - General call enable
pub fn enpec(&self) -> ENPEC_R[src]
Bit 5 - PEC enable
pub fn enarp(&self) -> ENARP_R[src]
Bit 4 - ARP enable
pub fn smbtype(&self) -> SMBTYPE_R[src]
Bit 3 - SMBus type
pub fn smbus(&self) -> SMBUS_R[src]
Bit 1 - SMBus mode
pub fn pe(&self) -> PE_R[src]
Bit 0 - Peripheral enable
impl R<bool, LAST_A>[src]
pub fn variant(&self) -> LAST_A[src]
Get enumerated values variant
pub fn is_not_last(&self) -> bool[src]
Checks if the value of the field is NOTLAST
pub fn is_last(&self) -> bool[src]
Checks if the value of the field is LAST
impl R<bool, DMAEN_A>[src]
pub fn variant(&self) -> DMAEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ITBUFEN_A>[src]
pub fn variant(&self) -> ITBUFEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ITEVTEN_A>[src]
pub fn variant(&self) -> ITEVTEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ITERREN_A>[src]
pub fn variant(&self) -> ITERREN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR2>>[src]
pub fn last(&self) -> LAST_R[src]
Bit 12 - DMA last transfer
pub fn dmaen(&self) -> DMAEN_R[src]
Bit 11 - DMA requests enable
pub fn itbufen(&self) -> ITBUFEN_R[src]
Bit 10 - Buffer interrupt enable
pub fn itevten(&self) -> ITEVTEN_R[src]
Bit 9 - Event interrupt enable
pub fn iterren(&self) -> ITERREN_R[src]
Bit 8 - Error interrupt enable
pub fn freq(&self) -> FREQ_R[src]
Bits 0:5 - Peripheral clock frequency
impl R<bool, ADDMODE_A>[src]
pub fn variant(&self) -> ADDMODE_A[src]
Get enumerated values variant
pub fn is_add7(&self) -> bool[src]
Checks if the value of the field is ADD7
pub fn is_add10(&self) -> bool[src]
Checks if the value of the field is ADD10
impl R<u32, Reg<u32, _OAR1>>[src]
pub fn addmode(&self) -> ADDMODE_R[src]
Bit 15 - ADDMODE
pub fn add(&self) -> ADD_R[src]
Bits 0:9 - Interface address
impl R<bool, ENDUAL_A>[src]
pub fn variant(&self) -> ENDUAL_A[src]
Get enumerated values variant
pub fn is_single(&self) -> bool[src]
Checks if the value of the field is SINGLE
pub fn is_dual(&self) -> bool[src]
Checks if the value of the field is DUAL
impl R<u32, Reg<u32, _OAR2>>[src]
pub fn add2(&self) -> ADD2_R[src]
Bits 1:7 - Interface address
pub fn endual(&self) -> ENDUAL_R[src]
Bit 0 - Dual addressing mode enable
impl R<u32, Reg<u32, _DR>>[src]
impl R<bool, SMBALERT_A>[src]
pub fn variant(&self) -> SMBALERT_A[src]
Get enumerated values variant
pub fn is_no_alert(&self) -> bool[src]
Checks if the value of the field is NOALERT
pub fn is_alert(&self) -> bool[src]
Checks if the value of the field is ALERT
impl R<bool, TIMEOUT_A>[src]
pub fn variant(&self) -> TIMEOUT_A[src]
Get enumerated values variant
pub fn is_no_timeout(&self) -> bool[src]
Checks if the value of the field is NOTIMEOUT
pub fn is_timeout(&self) -> bool[src]
Checks if the value of the field is TIMEOUT
impl R<bool, PECERR_A>[src]
pub fn variant(&self) -> PECERR_A[src]
Get enumerated values variant
pub fn is_no_error(&self) -> bool[src]
Checks if the value of the field is NOERROR
pub fn is_error(&self) -> bool[src]
Checks if the value of the field is ERROR
impl R<bool, OVR_A>[src]
pub fn variant(&self) -> OVR_A[src]
Get enumerated values variant
pub fn is_no_overrun(&self) -> bool[src]
Checks if the value of the field is NOOVERRUN
pub fn is_overrun(&self) -> bool[src]
Checks if the value of the field is OVERRUN
impl R<bool, AF_A>[src]
pub fn variant(&self) -> AF_A[src]
Get enumerated values variant
pub fn is_no_failure(&self) -> bool[src]
Checks if the value of the field is NOFAILURE
pub fn is_failure(&self) -> bool[src]
Checks if the value of the field is FAILURE
impl R<bool, ARLO_A>[src]
pub fn variant(&self) -> ARLO_A[src]
Get enumerated values variant
pub fn is_no_lost(&self) -> bool[src]
Checks if the value of the field is NOLOST
pub fn is_lost(&self) -> bool[src]
Checks if the value of the field is LOST
impl R<bool, BERR_A>[src]
pub fn variant(&self) -> BERR_A[src]
Get enumerated values variant
pub fn is_no_error(&self) -> bool[src]
Checks if the value of the field is NOERROR
pub fn is_error(&self) -> bool[src]
Checks if the value of the field is ERROR
impl R<bool, TXE_A>[src]
pub fn variant(&self) -> TXE_A[src]
Get enumerated values variant
pub fn is_not_empty(&self) -> bool[src]
Checks if the value of the field is NOTEMPTY
pub fn is_empty(&self) -> bool[src]
Checks if the value of the field is EMPTY
impl R<bool, RXNE_A>[src]
pub fn variant(&self) -> RXNE_A[src]
Get enumerated values variant
pub fn is_empty(&self) -> bool[src]
Checks if the value of the field is EMPTY
pub fn is_not_empty(&self) -> bool[src]
Checks if the value of the field is NOTEMPTY
impl R<bool, STOPF_A>[src]
pub fn variant(&self) -> STOPF_A[src]
Get enumerated values variant
pub fn is_no_stop(&self) -> bool[src]
Checks if the value of the field is NOSTOP
pub fn is_stop(&self) -> bool[src]
Checks if the value of the field is STOP
impl R<bool, BTF_A>[src]
pub fn variant(&self) -> BTF_A[src]
Get enumerated values variant
pub fn is_not_finished(&self) -> bool[src]
Checks if the value of the field is NOTFINISHED
pub fn is_finished(&self) -> bool[src]
Checks if the value of the field is FINISHED
impl R<bool, ADDR_A>[src]
pub fn variant(&self) -> ADDR_A[src]
Get enumerated values variant
pub fn is_not_match(&self) -> bool[src]
Checks if the value of the field is NOTMATCH
pub fn is_match_(&self) -> bool[src]
Checks if the value of the field is MATCH
impl R<bool, SB_A>[src]
pub fn variant(&self) -> SB_A[src]
Get enumerated values variant
pub fn is_no_start(&self) -> bool[src]
Checks if the value of the field is NOSTART
pub fn is_start(&self) -> bool[src]
Checks if the value of the field is START
impl R<u32, Reg<u32, _SR1>>[src]
pub fn smbalert(&self) -> SMBALERT_R[src]
Bit 15 - SMBus alert
pub fn timeout(&self) -> TIMEOUT_R[src]
Bit 14 - Timeout or Tlow error
pub fn pecerr(&self) -> PECERR_R[src]
Bit 12 - PEC Error in reception
pub fn ovr(&self) -> OVR_R[src]
Bit 11 - Overrun/Underrun
pub fn af(&self) -> AF_R[src]
Bit 10 - Acknowledge failure
pub fn arlo(&self) -> ARLO_R[src]
Bit 9 - Arbitration lost (master mode)
pub fn berr(&self) -> BERR_R[src]
Bit 8 - Bus error
pub fn tx_e(&self) -> TXE_R[src]
Bit 7 - Data register empty (transmitters)
pub fn rx_ne(&self) -> RXNE_R[src]
Bit 6 - Data register not empty (receivers)
pub fn stopf(&self) -> STOPF_R[src]
Bit 4 - Stop detection (slave mode)
pub fn add10(&self) -> ADD10_R[src]
Bit 3 - 10-bit header sent (Master mode)
pub fn btf(&self) -> BTF_R[src]
Bit 2 - Byte transfer finished
pub fn addr(&self) -> ADDR_R[src]
Bit 1 - Address sent (master mode)/matched (slave mode)
pub fn sb(&self) -> SB_R[src]
Bit 0 - Start bit (Master mode)
impl R<u32, Reg<u32, _SR2>>[src]
pub fn pec(&self) -> PEC_R[src]
Bits 8:15 - acket error checking register
pub fn dualf(&self) -> DUALF_R[src]
Bit 7 - Dual flag (Slave mode)
pub fn smbhost(&self) -> SMBHOST_R[src]
Bit 6 - SMBus host header (Slave mode)
pub fn smbdefault(&self) -> SMBDEFAULT_R[src]
Bit 5 - SMBus device default address (Slave mode)
pub fn gencall(&self) -> GENCALL_R[src]
Bit 4 - General call address (Slave mode)
pub fn tra(&self) -> TRA_R[src]
Bit 2 - Transmitter/receiver
pub fn busy(&self) -> BUSY_R[src]
Bit 1 - Bus busy
pub fn msl(&self) -> MSL_R[src]
Bit 0 - Master/slave
impl R<bool, F_S_A>[src]
pub fn variant(&self) -> F_S_A[src]
Get enumerated values variant
pub fn is_standard(&self) -> bool[src]
Checks if the value of the field is STANDARD
pub fn is_fast(&self) -> bool[src]
Checks if the value of the field is FAST
impl R<bool, DUTY_A>[src]
pub fn variant(&self) -> DUTY_A[src]
Get enumerated values variant
pub fn is_duty2_1(&self) -> bool[src]
Checks if the value of the field is DUTY2_1
pub fn is_duty16_9(&self) -> bool[src]
Checks if the value of the field is DUTY16_9
impl R<u32, Reg<u32, _CCR>>[src]
pub fn f_s(&self) -> F_S_R[src]
Bit 15 - I2C master mode selection
pub fn duty(&self) -> DUTY_R[src]
Bit 14 - Fast mode duty cycle
pub fn ccr(&self) -> CCR_R[src]
Bits 0:11 - Clock control register in Fast/Standard mode (Master mode)
impl R<u32, Reg<u32, _TRISE>>[src]
impl R<u8, PR_A>[src]
pub fn variant(&self) -> PR_A[src]
Get enumerated values variant
pub fn is_divide_by4(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY4
pub fn is_divide_by8(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY8
pub fn is_divide_by16(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY16
pub fn is_divide_by32(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY32
pub fn is_divide_by64(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY64
pub fn is_divide_by128(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY128
pub fn is_divide_by256(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY256
pub fn is_divide_by256bis(&self) -> bool[src]
Checks if the value of the field is DIVIDEBY256BIS
impl R<u32, Reg<u32, _PR>>[src]
impl R<u32, Reg<u32, _RLR>>[src]
impl R<u32, Reg<u32, _SR>>[src]
pub fn rvu(&self) -> RVU_R[src]
Bit 1 - Watchdog counter reload value update
pub fn pvu(&self) -> PVU_R[src]
Bit 0 - Watchdog prescaler value update
impl R<u32, Reg<u32, _CR>>[src]
pub fn mux_seg(&self) -> MUX_SEG_R[src]
Bit 7 - Mux segment enable
pub fn bias(&self) -> BIAS_R[src]
Bits 5:6 - Bias selector
pub fn duty(&self) -> DUTY_R[src]
Bits 2:4 - Duty selection
pub fn vsel(&self) -> VSEL_R[src]
Bit 1 - Voltage source selection
pub fn lcden(&self) -> LCDEN_R[src]
Bit 0 - LCD controller enable
impl R<u32, Reg<u32, _FCR>>[src]
pub fn ps(&self) -> PS_R[src]
Bits 22:25 - PS 16-bit prescaler
pub fn div(&self) -> DIV_R[src]
Bits 18:21 - DIV clock divider
pub fn blink(&self) -> BLINK_R[src]
Bits 16:17 - Blink mode selection
pub fn blinkf(&self) -> BLINKF_R[src]
Bits 13:15 - Blink frequency selection
pub fn cc(&self) -> CC_R[src]
Bits 10:12 - Contrast control
pub fn dead(&self) -> DEAD_R[src]
Bits 7:9 - Dead time duration
pub fn pon(&self) -> PON_R[src]
Bits 4:6 - Pulse ON duration
pub fn uddie(&self) -> UDDIE_R[src]
Bit 3 - Update display done interrupt enable
pub fn sofie(&self) -> SOFIE_R[src]
Bit 1 - Start of frame interrupt enable
pub fn hd(&self) -> HD_R[src]
Bit 0 - High drive enable
impl R<u32, Reg<u32, _SR>>[src]
pub fn fcrsf(&self) -> FCRSF_R[src]
Bit 5 - LCD Frame Control Register Synchronization flag
pub fn rdy(&self) -> RDY_R[src]
Bit 4 - Ready flag
pub fn udd(&self) -> UDD_R[src]
Bit 3 - Update Display Done
pub fn udr(&self) -> UDR_R[src]
Bit 2 - Update display request
pub fn sof(&self) -> SOF_R[src]
Bit 1 - Start of frame flag
pub fn ens(&self) -> ENS_R[src]
Bit 0 - LCD enabled status
impl R<u32, Reg<u32, _RAM_COM0>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM1>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM2>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM3>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM4>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM5>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM6>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _RAM_COM7>>[src]
pub fn s31(&self) -> S31_R[src]
Bit 31 - S31
pub fn s30(&self) -> S30_R[src]
Bit 30 - S30
pub fn s29(&self) -> S29_R[src]
Bit 29 - S29
pub fn s28(&self) -> S28_R[src]
Bit 28 - S28
pub fn s27(&self) -> S27_R[src]
Bit 27 - S27
pub fn s26(&self) -> S26_R[src]
Bit 26 - S26
pub fn s25(&self) -> S25_R[src]
Bit 25 - S25
pub fn s24(&self) -> S24_R[src]
Bit 24 - S24
pub fn s23(&self) -> S23_R[src]
Bit 23 - S23
pub fn s22(&self) -> S22_R[src]
Bit 22 - S22
pub fn s21(&self) -> S21_R[src]
Bit 21 - S21
pub fn s20(&self) -> S20_R[src]
Bit 20 - S20
pub fn s19(&self) -> S19_R[src]
Bit 19 - S19
pub fn s18(&self) -> S18_R[src]
Bit 18 - S18
pub fn s17(&self) -> S17_R[src]
Bit 17 - S17
pub fn s16(&self) -> S16_R[src]
Bit 16 - S16
pub fn s15(&self) -> S15_R[src]
Bit 15 - S15
pub fn s14(&self) -> S14_R[src]
Bit 14 - S14
pub fn s13(&self) -> S13_R[src]
Bit 13 - S13
pub fn s12(&self) -> S12_R[src]
Bit 12 - S12
pub fn s11(&self) -> S11_R[src]
Bit 11 - S11
pub fn s10(&self) -> S10_R[src]
Bit 10 - S10
pub fn s09(&self) -> S09_R[src]
Bit 9 - S09
pub fn s08(&self) -> S08_R[src]
Bit 8 - S08
pub fn s07(&self) -> S07_R[src]
Bit 7 - S07
pub fn s06(&self) -> S06_R[src]
Bit 6 - S06
pub fn s05(&self) -> S05_R[src]
Bit 5 - S05
pub fn s04(&self) -> S04_R[src]
Bit 4 - S04
pub fn s03(&self) -> S03_R[src]
Bit 3 - S03
pub fn s02(&self) -> S02_R[src]
Bit 2 - S02
pub fn s01(&self) -> S01_R[src]
Bit 1 - S01
pub fn s00(&self) -> S00_R[src]
Bit 0 - S00
impl R<u32, Reg<u32, _CSR>>[src]
pub fn opa3calout(&self) -> OPA3CALOUT_R[src]
Bit 31 - OPAMP3 calibration output
pub fn opa2calout(&self) -> OPA2CALOUT_R[src]
Bit 30 - OPAMP2 calibration output
pub fn opa1calout(&self) -> OPA1CALOUT_R[src]
Bit 29 - OPAMP1 calibration output
pub fn aop_range(&self) -> AOP_RANGE_R[src]
Bit 28 - Power range selection
pub fn s7sel2(&self) -> S7SEL2_R[src]
Bit 27 - Switch 7 for OPAMP2 enable
pub fn anawsel3(&self) -> ANAWSEL3_R[src]
Bit 26 - Switch SanA enable for OPAMP3
pub fn anawsel2(&self) -> ANAWSEL2_R[src]
Bit 25 - Switch SanA enable for OPAMP2
pub fn anawsel1(&self) -> ANAWSEL1_R[src]
Bit 24 - Switch SanA enable for OPAMP1
pub fn opa3lpm(&self) -> OPA3LPM_R[src]
Bit 23 - OPAMP3 low power mode
pub fn opa3cal_h(&self) -> OPA3CAL_H_R[src]
Bit 22 - OPAMP3 offset calibration for N differential pair
pub fn opa3cal_l(&self) -> OPA3CAL_L_R[src]
Bit 21 - OPAMP3 offset Calibration for P differential pair
pub fn s6sel3(&self) -> S6SEL3_R[src]
Bit 20 - Switch 6 for OPAMP3 enable
pub fn s5sel3(&self) -> S5SEL3_R[src]
Bit 19 - Switch 5 for OPAMP3 enable
pub fn s4sel3(&self) -> S4SEL3_R[src]
Bit 18 - Switch 4 for OPAMP3 enable
pub fn s3sel3(&self) -> S3SEL3_R[src]
Bit 17 - Switch 3 for OPAMP3 Enable
pub fn opa3pd(&self) -> OPA3PD_R[src]
Bit 16 - OPAMP3 power down
pub fn opa2lpm(&self) -> OPA2LPM_R[src]
Bit 15 - OPAMP2 low power mode
pub fn opa2cal_h(&self) -> OPA2CAL_H_R[src]
Bit 14 - OPAMP2 offset calibration for N differential pair
pub fn opa2cal_l(&self) -> OPA2CAL_L_R[src]
Bit 13 - OPAMP2 offset Calibration for P differential pair
pub fn s6sel2(&self) -> S6SEL2_R[src]
Bit 12 - Switch 6 for OPAMP2 enable
pub fn s5sel2(&self) -> S5SEL2_R[src]
Bit 11 - Switch 5 for OPAMP2 enable
pub fn s4sel2(&self) -> S4SEL2_R[src]
Bit 10 - Switch 4 for OPAMP2 enable
pub fn s3sel2(&self) -> S3SEL2_R[src]
Bit 9 - Switch 3 for OPAMP2 enable
pub fn opa2pd(&self) -> OPA2PD_R[src]
Bit 8 - OPAMP2 power down
pub fn opa1lpm(&self) -> OPA1LPM_R[src]
Bit 7 - OPAMP1 low power mode
pub fn opa1cal_h(&self) -> OPA1CAL_H_R[src]
Bit 6 - OPAMP1 offset calibration for N differential pair
pub fn opa1cal_l(&self) -> OPA1CAL_L_R[src]
Bit 5 - OPAMP1 offset calibration for P differential pair
pub fn s6sel1(&self) -> S6SEL1_R[src]
Bit 4 - Switch 6 for OPAMP1 enable
pub fn s5sel1(&self) -> S5SEL1_R[src]
Bit 3 - Switch 5 for OPAMP1 enable
pub fn s4sel1(&self) -> S4SEL1_R[src]
Bit 2 - Switch 4 for OPAMP1 enable
pub fn s3sel1(&self) -> S3SEL1_R[src]
Bit 1 - Switch 3 for OPAMP1 enable
pub fn opa1pd(&self) -> OPA1PD_R[src]
Bit 0 - OPAMP1 power down
impl R<u32, Reg<u32, _OTR>>[src]
pub fn ot_user(&self) -> OT_USER_R[src]
Bit 31 - Select user or factory trimming value
pub fn ao3_opt_offset_trim(&self) -> AO3_OPT_OFFSET_TRIM_R[src]
Bits 20:29 - OPAMP3, 10-bit offset trim value for normal mode
pub fn ao2_opt_offset_trim(&self) -> AO2_OPT_OFFSET_TRIM_R[src]
Bits 10:19 - OPAMP2, 10-bit offset trim value for normal mode
pub fn ao1_opt_offset_trim(&self) -> AO1_OPT_OFFSET_TRIM_R[src]
Bits 0:9 - OPAMP1, 10-bit offset trim value for normal mode
impl R<u32, Reg<u32, _LPOTR>>[src]
pub fn ao3_opt_offset_trim_lp(&self) -> AO3_OPT_OFFSET_TRIM_LP_R[src]
Bits 20:29 - OPAMP3, 10-bit offset trim value for low power mode
pub fn ao2_opt_offset_trim_lp(&self) -> AO2_OPT_OFFSET_TRIM_LP_R[src]
Bits 10:19 - OPAMP2, 10-bit offset trim value for low power mode
pub fn ao1_opt_offset_trim_lp(&self) -> AO1_OPT_OFFSET_TRIM_LP_R[src]
Bits 0:9 - OPAMP1, 10-bit offset trim value for low power mode
impl R<bool, PDDS_A>[src]
pub fn variant(&self) -> PDDS_A[src]
Get enumerated values variant
pub fn is_stop_mode(&self) -> bool[src]
Checks if the value of the field is STOP_MODE
pub fn is_standby_mode(&self) -> bool[src]
Checks if the value of the field is STANDBY_MODE
impl R<u32, Reg<u32, _CR>>[src]
pub fn lprun(&self) -> LPRUN_R[src]
Bit 14 - Low power run mode
pub fn vos(&self) -> VOS_R[src]
Bits 11:12 - Voltage scaling range selection
pub fn fwu(&self) -> FWU_R[src]
Bit 10 - Fast wakeup
pub fn ulp(&self) -> ULP_R[src]
Bit 9 - Ultralow power mode
pub fn dbp(&self) -> DBP_R[src]
Bit 8 - Disable backup domain write protection
pub fn pls(&self) -> PLS_R[src]
Bits 5:7 - PVD level selection
pub fn pvde(&self) -> PVDE_R[src]
Bit 4 - Power voltage detector enable
pub fn csbf(&self) -> CSBF_R[src]
Bit 3 - Clear standby flag
pub fn cwuf(&self) -> CWUF_R[src]
Bit 2 - Clear wakeup flag
pub fn pdds(&self) -> PDDS_R[src]
Bit 1 - Power down deepsleep
pub fn lpsdsr(&self) -> LPSDSR_R[src]
Bit 0 - Low-power deep sleep
impl R<u32, Reg<u32, _CSR>>[src]
pub fn ewup3(&self) -> EWUP3_R[src]
Bit 10 - Enable WKUP pin 3
pub fn ewup2(&self) -> EWUP2_R[src]
Bit 9 - Enable WKUP pin 2
pub fn ewup1(&self) -> EWUP1_R[src]
Bit 8 - Enable WKUP pin 1
pub fn reglpf(&self) -> REGLPF_R[src]
Bit 5 - Regulator LP flag
pub fn vosf(&self) -> VOSF_R[src]
Bit 4 - Voltage Scaling select flag
pub fn vrefintrdyf(&self) -> VREFINTRDYF_R[src]
Bit 3 - Internal voltage reference (VREFINT) ready flag
pub fn pvdo(&self) -> PVDO_R[src]
Bit 2 - PVD output
pub fn sbf(&self) -> SBF_R[src]
Bit 1 - Standby flag
pub fn wuf(&self) -> WUF_R[src]
Bit 0 - Wakeup flag
impl R<u32, Reg<u32, _CR>>[src]
pub fn rtcpre1(&self) -> RTCPRE1_R[src]
Bit 30 - TC/LCD prescaler
pub fn rtcpre0(&self) -> RTCPRE0_R[src]
Bit 29 - RTCPRE0
pub fn csson(&self) -> CSSON_R[src]
Bit 28 - Clock security system enable
pub fn pllrdy(&self) -> PLLRDY_R[src]
Bit 25 - PLL clock ready flag
pub fn pllon(&self) -> PLLON_R[src]
Bit 24 - PLL enable
pub fn hsebyp(&self) -> HSEBYP_R[src]
Bit 18 - HSE clock bypass
pub fn hserdy(&self) -> HSERDY_R[src]
Bit 17 - HSE clock ready flag
pub fn hseon(&self) -> HSEON_R[src]
Bit 16 - HSE clock enable
pub fn msirdy(&self) -> MSIRDY_R[src]
Bit 9 - MSI clock ready flag
pub fn msion(&self) -> MSION_R[src]
Bit 8 - MSI clock enable
pub fn hsirdy(&self) -> HSIRDY_R[src]
Bit 1 - Internal high-speed clock ready flag
pub fn hsion(&self) -> HSION_R[src]
Bit 0 - Internal high-speed clock enable
impl R<u32, Reg<u32, _ICSCR>>[src]
pub fn msitrim(&self) -> MSITRIM_R[src]
Bits 24:31 - MSI clock trimming
pub fn msical(&self) -> MSICAL_R[src]
Bits 16:23 - MSI clock calibration
pub fn msirange(&self) -> MSIRANGE_R[src]
Bits 13:15 - MSI clock ranges
pub fn hsitrim(&self) -> HSITRIM_R[src]
Bits 8:12 - High speed internal clock trimming
pub fn hsical(&self) -> HSICAL_R[src]
Bits 0:7 - nternal high speed clock calibration
impl R<u32, Reg<u32, _CFGR>>[src]
pub fn mcopre(&self) -> MCOPRE_R[src]
Bits 28:30 - Microcontroller clock output prescaler
pub fn mcosel(&self) -> MCOSEL_R[src]
Bits 24:26 - Microcontroller clock output selection
pub fn plldiv(&self) -> PLLDIV_R[src]
Bits 22:23 - PLL output division
pub fn pllmul(&self) -> PLLMUL_R[src]
Bits 18:21 - PLL multiplication factor
pub fn pllsrc(&self) -> PLLSRC_R[src]
Bit 16 - PLL entry clock source
pub fn ppre2(&self) -> PPRE2_R[src]
Bits 11:13 - APB high-speed prescaler (APB2)
pub fn ppre1(&self) -> PPRE1_R[src]
Bits 8:10 - APB low-speed prescaler (APB1)
pub fn hpre(&self) -> HPRE_R[src]
Bits 4:7 - AHB prescaler
pub fn sws(&self) -> SWS_R[src]
Bits 2:3 - System clock switch status
pub fn sw(&self) -> SW_R[src]
Bits 0:1 - System clock switch
impl R<u32, Reg<u32, _CIR>>[src]
pub fn msirdyie(&self) -> MSIRDYIE_R[src]
Bit 13 - MSI ready interrupt enable
pub fn pllrdyie(&self) -> PLLRDYIE_R[src]
Bit 12 - PLL ready interrupt enable
pub fn hserdyie(&self) -> HSERDYIE_R[src]
Bit 11 - HSE ready interrupt enable
pub fn hsirdyie(&self) -> HSIRDYIE_R[src]
Bit 10 - HSI ready interrupt enable
pub fn lserdyie(&self) -> LSERDYIE_R[src]
Bit 9 - LSE ready interrupt enable
pub fn lsirdyie(&self) -> LSIRDYIE_R[src]
Bit 8 - LSI ready interrupt enable
pub fn cssf(&self) -> CSSF_R[src]
Bit 7 - Clock security system interrupt flag
pub fn msirdyf(&self) -> MSIRDYF_R[src]
Bit 5 - MSI ready interrupt flag
pub fn pllrdyf(&self) -> PLLRDYF_R[src]
Bit 4 - PLL ready interrupt flag
pub fn hserdyf(&self) -> HSERDYF_R[src]
Bit 3 - HSE ready interrupt flag
pub fn hsirdyf(&self) -> HSIRDYF_R[src]
Bit 2 - HSI ready interrupt flag
pub fn lserdyf(&self) -> LSERDYF_R[src]
Bit 1 - LSE ready interrupt flag
pub fn lsirdyf(&self) -> LSIRDYF_R[src]
Bit 0 - LSI ready interrupt flag
impl R<u32, Reg<u32, _AHBRSTR>>[src]
pub fn fsmcrst(&self) -> FSMCRST_R[src]
Bit 30 - FSMC reset
pub fn dma2rst(&self) -> DMA2RST_R[src]
Bit 25 - DMA2 reset
pub fn dma1rst(&self) -> DMA1RST_R[src]
Bit 24 - DMA1 reset
pub fn flitfrst(&self) -> FLITFRST_R[src]
Bit 15 - FLITF reset
pub fn crcrst(&self) -> CRCRST_R[src]
Bit 12 - CRC reset
pub fn gpiogrst(&self) -> GPIOGRST_R[src]
Bit 7 - IO port G reset
pub fn gpiofrst(&self) -> GPIOFRST_R[src]
Bit 6 - IO port F reset
pub fn gpiohrst(&self) -> GPIOHRST_R[src]
Bit 5 - IO port H reset
pub fn gpioerst(&self) -> GPIOERST_R[src]
Bit 4 - IO port E reset
pub fn gpiodrst(&self) -> GPIODRST_R[src]
Bit 3 - IO port D reset
pub fn gpiocrst(&self) -> GPIOCRST_R[src]
Bit 2 - IO port C reset
pub fn gpiobrst(&self) -> GPIOBRST_R[src]
Bit 1 - IO port B reset
pub fn gpioarst(&self) -> GPIOARST_R[src]
Bit 0 - IO port A reset
impl R<u32, Reg<u32, _APB2RSTR>>[src]
pub fn usart1rst(&self) -> USART1RST_R[src]
Bit 14 - USART1RST
pub fn spi1rst(&self) -> SPI1RST_R[src]
Bit 12 - SPI1RST
pub fn sdiorst(&self) -> SDIORST_R[src]
Bit 11 - SDIORST
pub fn adc1rst(&self) -> ADC1RST_R[src]
Bit 9 - ADC1RST
pub fn tm11rst(&self) -> TM11RST_R[src]
Bit 4 - TM11RST
pub fn tm10rst(&self) -> TM10RST_R[src]
Bit 3 - TM10RST
pub fn tim9rst(&self) -> TIM9RST_R[src]
Bit 2 - TIM9RST
pub fn syscfgrst(&self) -> SYSCFGRST_R[src]
Bit 0 - SYSCFGRST
impl R<u32, Reg<u32, _APB1RSTR>>[src]
pub fn comprst(&self) -> COMPRST_R[src]
Bit 31 - COMP interface reset
pub fn dacrst(&self) -> DACRST_R[src]
Bit 29 - DAC interface reset
pub fn pwrrst(&self) -> PWRRST_R[src]
Bit 28 - Power interface reset
pub fn usbrst(&self) -> USBRST_R[src]
Bit 23 - USB reset
pub fn i2c2rst(&self) -> I2C2RST_R[src]
Bit 22 - I2C 2 reset
pub fn i2c1rst(&self) -> I2C1RST_R[src]
Bit 21 - I2C 1 reset
pub fn uart5rst(&self) -> UART5RST_R[src]
Bit 20 - UART 5 reset
pub fn uart4rst(&self) -> UART4RST_R[src]
Bit 19 - UART 4 reset
pub fn usart3rst(&self) -> USART3RST_R[src]
Bit 18 - USART 3 reset
pub fn usart2rst(&self) -> USART2RST_R[src]
Bit 17 - USART 2 reset
pub fn spi3rst(&self) -> SPI3RST_R[src]
Bit 15 - SPI 3 reset
pub fn spi2rst(&self) -> SPI2RST_R[src]
Bit 14 - SPI 2 reset
pub fn wwdrst(&self) -> WWDRST_R[src]
Bit 11 - Window watchdog reset
pub fn lcdrst(&self) -> LCDRST_R[src]
Bit 9 - LCD reset
pub fn tim7rst(&self) -> TIM7RST_R[src]
Bit 5 - Timer 7 reset
pub fn tim6rst(&self) -> TIM6RST_R[src]
Bit 4 - Timer 6reset
pub fn tim5rst(&self) -> TIM5RST_R[src]
Bit 3 - Timer 5 reset
pub fn tim4rst(&self) -> TIM4RST_R[src]
Bit 2 - Timer 4 reset
pub fn tim3rst(&self) -> TIM3RST_R[src]
Bit 1 - Timer 3 reset
pub fn tim2rst(&self) -> TIM2RST_R[src]
Bit 0 - Timer 2 reset
impl R<u32, Reg<u32, _AHBENR>>[src]
pub fn fsmcen(&self) -> FSMCEN_R[src]
Bit 30 - FSMCEN
pub fn dma2en(&self) -> DMA2EN_R[src]
Bit 25 - DMA2 clock enable
pub fn dma1en(&self) -> DMA1EN_R[src]
Bit 24 - DMA1 clock enable
pub fn flitfen(&self) -> FLITFEN_R[src]
Bit 15 - FLITF clock enable
pub fn crcen(&self) -> CRCEN_R[src]
Bit 12 - CRC clock enable
pub fn gpiopgen(&self) -> GPIOPGEN_R[src]
Bit 7 - IO port G clock enable
pub fn gpiopfen(&self) -> GPIOPFEN_R[src]
Bit 6 - IO port F clock enable
pub fn gpiophen(&self) -> GPIOPHEN_R[src]
Bit 5 - IO port H clock enable
pub fn gpiopeen(&self) -> GPIOPEEN_R[src]
Bit 4 - IO port E clock enable
pub fn gpiopden(&self) -> GPIOPDEN_R[src]
Bit 3 - IO port D clock enable
pub fn gpiopcen(&self) -> GPIOPCEN_R[src]
Bit 2 - IO port C clock enable
pub fn gpiopben(&self) -> GPIOPBEN_R[src]
Bit 1 - IO port B clock enable
pub fn gpiopaen(&self) -> GPIOPAEN_R[src]
Bit 0 - IO port A clock enable
impl R<u32, Reg<u32, _APB2ENR>>[src]
pub fn usart1en(&self) -> USART1EN_R[src]
Bit 14 - USART1 clock enable
pub fn spi1en(&self) -> SPI1EN_R[src]
Bit 12 - SPI 1 clock enable
pub fn sdioen(&self) -> SDIOEN_R[src]
Bit 11 - SDIO clock enable
pub fn adc1en(&self) -> ADC1EN_R[src]
Bit 9 - ADC1 interface clock enable
pub fn tim11en(&self) -> TIM11EN_R[src]
Bit 4 - TIM11 timer clock enable
pub fn tim10en(&self) -> TIM10EN_R[src]
Bit 3 - TIM10 timer clock enable
pub fn tim9en(&self) -> TIM9EN_R[src]
Bit 2 - TIM9 timer clock enable
pub fn syscfgen(&self) -> SYSCFGEN_R[src]
Bit 0 - System configuration controller clock enable
impl R<u32, Reg<u32, _APB1ENR>>[src]
pub fn compen(&self) -> COMPEN_R[src]
Bit 31 - COMP interface clock enable
pub fn dacen(&self) -> DACEN_R[src]
Bit 29 - DAC interface clock enable
pub fn pwren(&self) -> PWREN_R[src]
Bit 28 - Power interface clock enable
pub fn usben(&self) -> USBEN_R[src]
Bit 23 - USB clock enable
pub fn i2c2en(&self) -> I2C2EN_R[src]
Bit 22 - I2C 2 clock enable
pub fn i2c1en(&self) -> I2C1EN_R[src]
Bit 21 - I2C 1 clock enable
pub fn usart5en(&self) -> USART5EN_R[src]
Bit 20 - UART 5 clock enable
pub fn usart4en(&self) -> USART4EN_R[src]
Bit 19 - UART 4 clock enable
pub fn usart3en(&self) -> USART3EN_R[src]
Bit 18 - USART 3 clock enable
pub fn usart2en(&self) -> USART2EN_R[src]
Bit 17 - USART 2 clock enable
pub fn spi3en(&self) -> SPI3EN_R[src]
Bit 15 - SPI 3 clock enable
pub fn spi2en(&self) -> SPI2EN_R[src]
Bit 14 - SPI 2 clock enable
pub fn wwdgen(&self) -> WWDGEN_R[src]
Bit 11 - Window watchdog clock enable
pub fn lcden(&self) -> LCDEN_R[src]
Bit 9 - LCD clock enable
pub fn tim7en(&self) -> TIM7EN_R[src]
Bit 5 - Timer 7 clock enable
pub fn tim6en(&self) -> TIM6EN_R[src]
Bit 4 - Timer 6 clock enable
pub fn tim5en(&self) -> TIM5EN_R[src]
Bit 3 - Timer 5 clock enable
pub fn tim4en(&self) -> TIM4EN_R[src]
Bit 2 - Timer 4 clock enable
pub fn tim3en(&self) -> TIM3EN_R[src]
Bit 1 - Timer 3 clock enable
pub fn tim2en(&self) -> TIM2EN_R[src]
Bit 0 - Timer 2 clock enable
impl R<u32, Reg<u32, _AHBLPENR>>[src]
pub fn dma2lpen(&self) -> DMA2LPEN_R[src]
Bit 25 - DMA2 clock enable during Sleep mode
pub fn dma1lpen(&self) -> DMA1LPEN_R[src]
Bit 24 - DMA1 clock enable during Sleep mode
pub fn sramlpen(&self) -> SRAMLPEN_R[src]
Bit 16 - SRAM clock enable during Sleep mode
pub fn flitflpen(&self) -> FLITFLPEN_R[src]
Bit 15 - FLITF clock enable during Sleep mode
pub fn crclpen(&self) -> CRCLPEN_R[src]
Bit 12 - CRC clock enable during Sleep mode
pub fn gpioglpen(&self) -> GPIOGLPEN_R[src]
Bit 7 - IO port G clock enable during Sleep mode
pub fn gpioflpen(&self) -> GPIOFLPEN_R[src]
Bit 6 - IO port F clock enable during Sleep mode
pub fn gpiohlpen(&self) -> GPIOHLPEN_R[src]
Bit 5 - IO port H clock enable during Sleep mode
pub fn gpioelpen(&self) -> GPIOELPEN_R[src]
Bit 4 - IO port E clock enable during Sleep mode
pub fn gpiodlpen(&self) -> GPIODLPEN_R[src]
Bit 3 - IO port D clock enable during Sleep mode
pub fn gpioclpen(&self) -> GPIOCLPEN_R[src]
Bit 2 - IO port C clock enable during Sleep mode
pub fn gpioblpen(&self) -> GPIOBLPEN_R[src]
Bit 1 - IO port B clock enable during Sleep mode
pub fn gpioalpen(&self) -> GPIOALPEN_R[src]
Bit 0 - IO port A clock enable during Sleep mode
impl R<u32, Reg<u32, _APB2LPENR>>[src]
pub fn usart1lpen(&self) -> USART1LPEN_R[src]
Bit 14 - USART1 clock enable during Sleep mode
pub fn spi1lpen(&self) -> SPI1LPEN_R[src]
Bit 12 - SPI 1 clock enable during Sleep mode
pub fn sdiolpen(&self) -> SDIOLPEN_R[src]
Bit 11 - SDIO clock enable during Sleep mode
pub fn adc1lpen(&self) -> ADC1LPEN_R[src]
Bit 9 - ADC1 interface clock enable during Sleep mode
pub fn tim11lpen(&self) -> TIM11LPEN_R[src]
Bit 4 - TIM11 timer clock enable during Sleep mode
pub fn tim10lpen(&self) -> TIM10LPEN_R[src]
Bit 3 - TIM10 timer clock enable during Sleep mode
pub fn tim9lpen(&self) -> TIM9LPEN_R[src]
Bit 2 - TIM9 timer clock enable during Sleep mode
pub fn syscfglpen(&self) -> SYSCFGLPEN_R[src]
Bit 0 - System configuration controller clock enable during Sleep mode
impl R<u32, Reg<u32, _APB1LPENR>>[src]
pub fn complpen(&self) -> COMPLPEN_R[src]
Bit 31 - COMP interface clock enable during Sleep mode
pub fn daclpen(&self) -> DACLPEN_R[src]
Bit 29 - DAC interface clock enable during Sleep mode
pub fn pwrlpen(&self) -> PWRLPEN_R[src]
Bit 28 - Power interface clock enable during Sleep mode
pub fn usblpen(&self) -> USBLPEN_R[src]
Bit 23 - USB clock enable during Sleep mode
pub fn i2c2lpen(&self) -> I2C2LPEN_R[src]
Bit 22 - I2C 2 clock enable during Sleep mode
pub fn i2c1lpen(&self) -> I2C1LPEN_R[src]
Bit 21 - I2C 1 clock enable during Sleep mode
pub fn usart3lpen(&self) -> USART3LPEN_R[src]
Bit 18 - USART 3 clock enable during Sleep mode
pub fn usart2lpen(&self) -> USART2LPEN_R[src]
Bit 17 - USART 2 clock enable during Sleep mode
pub fn spi2lpen(&self) -> SPI2LPEN_R[src]
Bit 14 - SPI 2 clock enable during Sleep mode
pub fn wwdglpen(&self) -> WWDGLPEN_R[src]
Bit 11 - Window watchdog clock enable during Sleep mode
pub fn lcdlpen(&self) -> LCDLPEN_R[src]
Bit 9 - LCD clock enable during Sleep mode
pub fn tim7lpen(&self) -> TIM7LPEN_R[src]
Bit 5 - Timer 7 clock enable during Sleep mode
pub fn tim6lpen(&self) -> TIM6LPEN_R[src]
Bit 4 - Timer 6 clock enable during Sleep mode
pub fn tim4lpen(&self) -> TIM4LPEN_R[src]
Bit 2 - Timer 4 clock enable during Sleep mode
pub fn tim3lpen(&self) -> TIM3LPEN_R[src]
Bit 1 - Timer 3 clock enable during Sleep mode
pub fn tim2lpen(&self) -> TIM2LPEN_R[src]
Bit 0 - Timer 2 clock enable during Sleep mode
impl R<u32, Reg<u32, _CSR>>[src]
pub fn lpwrstf(&self) -> LPWRSTF_R[src]
Bit 31 - Low-power reset flag
pub fn wwdgrstf(&self) -> WWDGRSTF_R[src]
Bit 30 - Window watchdog reset flag
pub fn iwdgrstf(&self) -> IWDGRSTF_R[src]
Bit 29 - Independent watchdog reset flag
pub fn sftrstf(&self) -> SFTRSTF_R[src]
Bit 28 - Software reset flag
pub fn porrstf(&self) -> PORRSTF_R[src]
Bit 27 - POR/PDR reset flag
pub fn pinrstf(&self) -> PINRSTF_R[src]
Bit 26 - PIN reset flag
pub fn rmvf(&self) -> RMVF_R[src]
Bit 24 - Remove reset flag
pub fn rtcrst(&self) -> RTCRST_R[src]
Bit 23 - RTC software reset
pub fn rtcen(&self) -> RTCEN_R[src]
Bit 22 - RTC clock enable
pub fn rtcsel(&self) -> RTCSEL_R[src]
Bits 16:17 - RTC and LCD clock source selection
pub fn lsebyp(&self) -> LSEBYP_R[src]
Bit 10 - External low-speed oscillator bypass
pub fn lserdy(&self) -> LSERDY_R[src]
Bit 9 - External low-speed oscillator ready
pub fn lseon(&self) -> LSEON_R[src]
Bit 8 - External low-speed oscillator enable
pub fn lsirdy(&self) -> LSIRDY_R[src]
Bit 1 - Internal low-speed oscillator ready
pub fn lsion(&self) -> LSION_R[src]
Bit 0 - Internal low-speed oscillator enable
impl R<u32, Reg<u32, _ICR>>[src]
pub fn ic4(&self) -> IC4_R[src]
Bit 21 - IC4
pub fn ic3(&self) -> IC3_R[src]
Bit 20 - IC3
pub fn ic2(&self) -> IC2_R[src]
Bit 19 - IC2
pub fn ic1(&self) -> IC1_R[src]
Bit 18 - IC1
pub fn tim(&self) -> TIM_R[src]
Bits 16:17 - Timer select bits
pub fn ic4ios(&self) -> IC4IOS_R[src]
Bits 12:15 - Input capture 4 select bits
pub fn ic3ios(&self) -> IC3IOS_R[src]
Bits 8:11 - Input capture 3 select bits
pub fn ic2ios(&self) -> IC2IOS_R[src]
Bits 4:7 - Input capture 2 select bits
pub fn ic1ios(&self) -> IC1IOS_R[src]
Bits 0:3 - Input capture 1 select bits
impl R<u32, Reg<u32, _ASCR1>>[src]
pub fn scm(&self) -> SCM_R[src]
Bit 31 - Switch control mode
pub fn ch30gr11_4(&self) -> CH30GR11_4_R[src]
Bit 30 - Analog switch control
pub fn ch29gr11_3(&self) -> CH29GR11_3_R[src]
Bit 29 - Analog switch control
pub fn ch28gr11_2(&self) -> CH28GR11_2_R[src]
Bit 28 - Analog switch control
pub fn ch27gr11_1(&self) -> CH27GR11_1_R[src]
Bit 27 - Analog switch control
pub fn vcomp(&self) -> VCOMP_R[src]
Bit 26 - ADC analog switch selection for internal node to comparator 1
pub fn ch25(&self) -> CH25_R[src]
Bit 25 - Analog I/O switch control of channel CH25
pub fn ch24(&self) -> CH24_R[src]
Bit 24 - Analog I/O switch control of channel CH24
pub fn ch23(&self) -> CH23_R[src]
Bit 23 - Analog I/O switch control of channel CH23
pub fn ch22(&self) -> CH22_R[src]
Bit 22 - Analog I/O switch control of channel CH22
pub fn ch21gr7_4(&self) -> CH21GR7_4_R[src]
Bit 21 - Analog switch control
pub fn ch20gr7_3(&self) -> CH20GR7_3_R[src]
Bit 20 - Analog switch control
pub fn ch19gr7_2(&self) -> CH19GR7_2_R[src]
Bit 19 - Analog switch control
pub fn ch18gr7_1(&self) -> CH18GR7_1_R[src]
Bit 18 - Analog switch control
pub fn ch31gr7_1(&self) -> CH31GR7_1_R[src]
Bit 16 - Analog switch control
pub fn ch15gr9_2(&self) -> CH15GR9_2_R[src]
Bit 15 - Analog switch control
pub fn ch14gr9_1(&self) -> CH14GR9_1_R[src]
Bit 14 - Analog switch control
pub fn ch13gr8_4(&self) -> CH13GR8_4_R[src]
Bit 13 - Analog switch control
pub fn ch12gr8_3(&self) -> CH12GR8_3_R[src]
Bit 12 - Analog switch control
pub fn ch11gr8_2(&self) -> CH11GR8_2_R[src]
Bit 11 - Analog switch control
pub fn ch10gr8_1(&self) -> CH10GR8_1_R[src]
Bit 10 - Analog switch control
pub fn ch9gr3_2(&self) -> CH9GR3_2_R[src]
Bit 9 - Analog switch control
pub fn ch8gr3_1(&self) -> CH8GR3_1_R[src]
Bit 8 - Analog switch control
pub fn ch7gr2_2(&self) -> CH7GR2_2_R[src]
Bit 7 - Analog switch control
pub fn ch6gr2_1(&self) -> CH6GR2_1_R[src]
Bit 6 - Analog switch control
pub fn comp1_sw1(&self) -> COMP1_SW1_R[src]
Bit 5 - Comparator 1 analog switch
pub fn ch31gr11_5(&self) -> CH31GR11_5_R[src]
Bit 4 - Analog switch control
pub fn ch3gr1_4(&self) -> CH3GR1_4_R[src]
Bit 3 - Analog switch control
pub fn ch2gr1_3(&self) -> CH2GR1_3_R[src]
Bit 2 - Analog switch control
pub fn ch1gr1_2(&self) -> CH1GR1_2_R[src]
Bit 1 - Analog switch control
pub fn ch0gr1_1(&self) -> CH0GR1_1_R[src]
Bit 0 - Analog switch control
impl R<u32, Reg<u32, _ASCR2>>[src]
pub fn gr5_4(&self) -> GR5_4_R[src]
Bit 29 - GR5_4 analog switch control
pub fn gr6_4(&self) -> GR6_4_R[src]
Bit 28 - GR6_4 analog switch control
pub fn gr6_3(&self) -> GR6_3_R[src]
Bit 27 - GR6_3 analog switch control
pub fn gr7_7(&self) -> GR7_7_R[src]
Bit 26 - GR7_7 analog switch control
pub fn gr7_6(&self) -> GR7_6_R[src]
Bit 25 - GR7_6 analog switch control
pub fn gr7_5(&self) -> GR7_5_R[src]
Bit 24 - GR7_5 analog switch control
pub fn gr2_5(&self) -> GR2_5_R[src]
Bit 23 - GR2_5 analog switch control
pub fn gr2_4(&self) -> GR2_4_R[src]
Bit 22 - GR2_4 analog switch control
pub fn gr2_3(&self) -> GR2_3_R[src]
Bit 21 - GR2_3 analog switch control
pub fn gr9_4(&self) -> GR9_4_R[src]
Bit 20 - GR9_4 analog switch control
pub fn gr9_3(&self) -> GR9_3_R[src]
Bit 19 - GR9_3 analog switch control
pub fn gr3_5(&self) -> GR3_5_R[src]
Bit 18 - GR3_5 analog switch control
pub fn gr3_4(&self) -> GR3_4_R[src]
Bit 17 - GR3_4 analog switch control
pub fn gr3_3(&self) -> GR3_3_R[src]
Bit 16 - GR3_3 analog switch control
pub fn gr4_3(&self) -> GR4_3_R[src]
Bit 11 - GR4_3 analog switch control
pub fn gr4_2(&self) -> GR4_2_R[src]
Bit 10 - GR4_2 analog switch control
pub fn gr4_1(&self) -> GR4_1_R[src]
Bit 9 - GR4_1 analog switch control
pub fn gr5_3(&self) -> GR5_3_R[src]
Bit 8 - GR5_3 analog switch control
pub fn gr5_2(&self) -> GR5_2_R[src]
Bit 7 - GR5_2 analog switch control
pub fn gr5_1(&self) -> GR5_1_R[src]
Bit 6 - GR5_1 analog switch control
pub fn gr6_2(&self) -> GR6_2_R[src]
Bit 5 - GR6_2 analog switch control
pub fn gr6_1(&self) -> GR6_1_R[src]
Bit 4 - GR6_1 analog switch control
pub fn gr10_4(&self) -> GR10_4_R[src]
Bit 3 - GR10_4 analog switch control
pub fn gr10_3(&self) -> GR10_3_R[src]
Bit 2 - GR10_3 analog switch control
pub fn gr10_2(&self) -> GR10_2_R[src]
Bit 1 - GR10_2 analog switch control
pub fn gr10_1(&self) -> GR10_1_R[src]
Bit 0 - GR10_1 analog switch control
impl R<u32, Reg<u32, _HYSCR1>>[src]
pub fn pb(&self) -> PB_R[src]
Bits 16:31 - Port B hysteresis control on/off
pub fn pa(&self) -> PA_R[src]
Bits 0:15 - Port A hysteresis control on/off
impl R<u32, Reg<u32, _HYSCR2>>[src]
pub fn pd(&self) -> PD_R[src]
Bits 16:31 - Port D hysteresis control on/off
pub fn pc(&self) -> PC_R[src]
Bits 0:15 - Port C hysteresis control on/off
impl R<u32, Reg<u32, _HYSCR3>>[src]
pub fn pf(&self) -> PF_R[src]
Bits 16:31 - Port F hysteresis control on/off
pub fn pe(&self) -> PE_R[src]
Bits 0:15 - Port E hysteresis control on/off
impl R<u32, Reg<u32, _HYSCR4>>[src]
impl R<u32, Reg<u32, _TR>>[src]
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format
impl R<u32, Reg<u32, _DR>>[src]
pub fn yt(&self) -> YT_R[src]
Bits 20:23 - Year tens in BCD format
pub fn yu(&self) -> YU_R[src]
Bits 16:19 - Year units in BCD format
pub fn wdu(&self) -> WDU_R[src]
Bits 13:15 - Week day units
pub fn mt(&self) -> MT_R[src]
Bit 12 - Month tens in BCD format
pub fn mu(&self) -> MU_R[src]
Bits 8:11 - Month units in BCD format
pub fn dt(&self) -> DT_R[src]
Bits 4:5 - Date tens in BCD format
pub fn du(&self) -> DU_R[src]
Bits 0:3 - Date units in BCD format
impl R<u32, Reg<u32, _CR>>[src]
pub fn coe(&self) -> COE_R[src]
Bit 23 - Calibration output enable
pub fn osel(&self) -> OSEL_R[src]
Bits 21:22 - Output selection
pub fn pol(&self) -> POL_R[src]
Bit 20 - Output polarity
pub fn cosel(&self) -> COSEL_R[src]
Bit 19 - Calibration output selection
pub fn bkp(&self) -> BKP_R[src]
Bit 18 - Backup
pub fn sub1h(&self) -> SUB1H_R[src]
Bit 17 - Subtract 1 hour
pub fn add1h(&self) -> ADD1H_R[src]
Bit 16 - Add 1 hour
pub fn tsie(&self) -> TSIE_R[src]
Bit 15 - Time-stamp interrupt enable
pub fn wutie(&self) -> WUTIE_R[src]
Bit 14 - Wakeup timer interrupt enable
pub fn alrbie(&self) -> ALRBIE_R[src]
Bit 13 - Alarm B interrupt enable
pub fn alraie(&self) -> ALRAIE_R[src]
Bit 12 - Alarm A interrupt enable
pub fn tse(&self) -> TSE_R[src]
Bit 11 - Time stamp enable
pub fn wute(&self) -> WUTE_R[src]
Bit 10 - Wakeup timer enable
pub fn alrbe(&self) -> ALRBE_R[src]
Bit 9 - Alarm B enable
pub fn alrae(&self) -> ALRAE_R[src]
Bit 8 - Alarm A enable
pub fn dce(&self) -> DCE_R[src]
Bit 7 - Coarse digital calibration enable
pub fn fmt(&self) -> FMT_R[src]
Bit 6 - Hour format
pub fn bypshad(&self) -> BYPSHAD_R[src]
Bit 5 - Bypass the shadow registers
pub fn refckon(&self) -> REFCKON_R[src]
Bit 4 - Reference clock detection enable
pub fn tsedge(&self) -> TSEDGE_R[src]
Bit 3 - Time-stamp event active edge
pub fn wcksel(&self) -> WCKSEL_R[src]
Bits 0:2 - WCKSEL
impl R<u32, Reg<u32, _ISR>>[src]
pub fn recalpf(&self) -> RECALPF_R[src]
Bit 16 - Recalibration pending Flag
pub fn tamp3f(&self) -> TAMP3F_R[src]
Bit 15 - TAMPER3 detection flag
pub fn tamp2f(&self) -> TAMP2F_R[src]
Bit 14 - TAMPER2 detection flag
pub fn tamp1f(&self) -> TAMP1F_R[src]
Bit 13 - Tamper detection flag
pub fn tsovf(&self) -> TSOVF_R[src]
Bit 12 - Timestamp overflow flag
pub fn tsf(&self) -> TSF_R[src]
Bit 11 - Timestamp flag
pub fn wutf(&self) -> WUTF_R[src]
Bit 10 - Wakeup timer flag
pub fn alrbf(&self) -> ALRBF_R[src]
Bit 9 - Alarm B flag
pub fn alraf(&self) -> ALRAF_R[src]
Bit 8 - Alarm A flag
pub fn init(&self) -> INIT_R[src]
Bit 7 - Initialization mode
pub fn initf(&self) -> INITF_R[src]
Bit 6 - Initialization flag
pub fn rsf(&self) -> RSF_R[src]
Bit 5 - Registers synchronization flag
pub fn inits(&self) -> INITS_R[src]
Bit 4 - Initialization status flag
pub fn shpf(&self) -> SHPF_R[src]
Bit 3 - Shift operation pending
pub fn wutwf(&self) -> WUTWF_R[src]
Bit 2 - Wakeup timer write flag
pub fn alrbwf(&self) -> ALRBWF_R[src]
Bit 1 - Alarm B write flag
pub fn alrawf(&self) -> ALRAWF_R[src]
Bit 0 - Alarm A write flag
impl R<u32, Reg<u32, _PRER>>[src]
pub fn prediv_a(&self) -> PREDIV_A_R[src]
Bits 16:22 - Asynchronous prescaler factor
pub fn prediv_s(&self) -> PREDIV_S_R[src]
Bits 0:14 - Synchronous prescaler factor
impl R<u32, Reg<u32, _WUTR>>[src]
impl R<u32, Reg<u32, _CALIBR>>[src]
pub fn dcs(&self) -> DCS_R[src]
Bit 7 - Digital calibration sign
pub fn dc(&self) -> DC_R[src]
Bits 0:4 - Digital calibration
impl R<u32, Reg<u32, _ALRMAR>>[src]
pub fn msk4(&self) -> MSK4_R[src]
Bit 31 - Alarm A date mask
pub fn wdsel(&self) -> WDSEL_R[src]
Bit 30 - Week day selection
pub fn dt(&self) -> DT_R[src]
Bits 28:29 - Date tens in BCD format.
pub fn du(&self) -> DU_R[src]
Bits 24:27 - Date units or day in BCD format.
pub fn msk3(&self) -> MSK3_R[src]
Bit 23 - Alarm A hours mask
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format.
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format.
pub fn msk2(&self) -> MSK2_R[src]
Bit 15 - Alarm A minutes mask
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format.
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format.
pub fn msk1(&self) -> MSK1_R[src]
Bit 7 - Alarm A seconds mask
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format.
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format.
impl R<u32, Reg<u32, _ALRMBR>>[src]
pub fn msk4(&self) -> MSK4_R[src]
Bit 31 - Alarm B date mask
pub fn wdsel(&self) -> WDSEL_R[src]
Bit 30 - Week day selection
pub fn dt(&self) -> DT_R[src]
Bits 28:29 - Date tens in BCD format
pub fn du(&self) -> DU_R[src]
Bits 24:27 - Date units or day in BCD format
pub fn msk3(&self) -> MSK3_R[src]
Bit 23 - Alarm B hours mask
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format
pub fn msk2(&self) -> MSK2_R[src]
Bit 15 - Alarm B minutes mask
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format
pub fn msk1(&self) -> MSK1_R[src]
Bit 7 - Alarm B seconds mask
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format
impl R<u32, Reg<u32, _SSR>>[src]
impl R<u32, Reg<u32, _TSTR>>[src]
pub fn pm(&self) -> PM_R[src]
Bit 22 - AM/PM notation
pub fn ht(&self) -> HT_R[src]
Bits 20:21 - Hour tens in BCD format.
pub fn hu(&self) -> HU_R[src]
Bits 16:19 - Hour units in BCD format.
pub fn mnt(&self) -> MNT_R[src]
Bits 12:14 - Minute tens in BCD format.
pub fn mnu(&self) -> MNU_R[src]
Bits 8:11 - Minute units in BCD format.
pub fn st(&self) -> ST_R[src]
Bits 4:6 - Second tens in BCD format.
pub fn su(&self) -> SU_R[src]
Bits 0:3 - Second units in BCD format.
impl R<u32, Reg<u32, _TSDR>>[src]
pub fn wdu(&self) -> WDU_R[src]
Bits 13:15 - Week day units
pub fn mt(&self) -> MT_R[src]
Bit 12 - Month tens in BCD format
pub fn mu(&self) -> MU_R[src]
Bits 8:11 - Month units in BCD format
pub fn dt(&self) -> DT_R[src]
Bits 4:5 - Date tens in BCD format
pub fn du(&self) -> DU_R[src]
Bits 0:3 - Date units in BCD format
impl R<u32, Reg<u32, _TSSSR>>[src]
impl R<u32, Reg<u32, _CALR>>[src]
pub fn calp(&self) -> CALP_R[src]
Bit 15 - Use an 8-second calibration cycle period
pub fn calw8(&self) -> CALW8_R[src]
Bit 14 - Use a 16-second calibration cycle period
pub fn calw16(&self) -> CALW16_R[src]
Bit 13 - CALW16
pub fn calm(&self) -> CALM_R[src]
Bits 0:8 - Calibration minus
impl R<u32, Reg<u32, _TAFCR>>[src]
pub fn alarmouttype(&self) -> ALARMOUTTYPE_R[src]
Bit 18 - AFO_ALARM output type
pub fn tamppudis(&self) -> TAMPPUDIS_R[src]
Bit 15 - TAMPER pull-up disable
pub fn tampprch(&self) -> TAMPPRCH_R[src]
Bits 13:14 - Tamper precharge duration
pub fn tampflt(&self) -> TAMPFLT_R[src]
Bits 11:12 - Tamper filter count
pub fn tampfreq(&self) -> TAMPFREQ_R[src]
Bits 8:10 - Tamper sampling frequency
pub fn tampts(&self) -> TAMPTS_R[src]
Bit 7 - Activate timestamp on tamper detection event
pub fn tamp3trg(&self) -> TAMP3TRG_R[src]
Bit 6 - TAMPER1 mapping
pub fn tamp3e(&self) -> TAMP3E_R[src]
Bit 5 - TIMESTAMP mapping
pub fn tamp2trg(&self) -> TAMP2TRG_R[src]
Bit 4 - Active level for tamper 2
pub fn tamp2e(&self) -> TAMP2E_R[src]
Bit 3 - Tamper 2 detection enable
pub fn tampie(&self) -> TAMPIE_R[src]
Bit 2 - Tamper interrupt enable
pub fn tamp1etrg(&self) -> TAMP1ETRG_R[src]
Bit 1 - Active level for tamper 1
pub fn tamp1e(&self) -> TAMP1E_R[src]
Bit 0 - Tamper 1 detection enable
impl R<u32, Reg<u32, _ALRMASSR>>[src]
pub fn maskss(&self) -> MASKSS_R[src]
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&self) -> SS_R[src]
Bits 0:14 - Sub seconds value
impl R<u32, Reg<u32, _ALRMBSSR>>[src]
pub fn maskss(&self) -> MASKSS_R[src]
Bits 24:27 - Mask the most-significant bits starting at this bit
pub fn ss(&self) -> SS_R[src]
Bits 0:14 - Sub seconds value
impl R<u32, Reg<u32, _BKPR>>[src]
impl R<u32, Reg<u32, _POWER>>[src]
impl R<u32, Reg<u32, _CLKCR>>[src]
pub fn hwfc_en(&self) -> HWFC_EN_R[src]
Bit 14 - HW Flow Control enable
pub fn negedge(&self) -> NEGEDGE_R[src]
Bit 13 - SDIO_CK dephasing selection bit
pub fn widbus(&self) -> WIDBUS_R[src]
Bits 11:12 - Wide bus mode enable bit
pub fn bypass(&self) -> BYPASS_R[src]
Bit 10 - Clock divider bypass enable bit
pub fn pwrsav(&self) -> PWRSAV_R[src]
Bit 9 - Power saving configuration bit
pub fn clken(&self) -> CLKEN_R[src]
Bit 8 - Clock enable bit
pub fn clkdiv(&self) -> CLKDIV_R[src]
Bits 0:7 - Clock divide factor
impl R<u32, Reg<u32, _ARG>>[src]
impl R<u32, Reg<u32, _CMD>>[src]
pub fn ce_atacmd(&self) -> CE_ATACMD_R[src]
Bit 14 - CE-ATA command
pub fn n_ien(&self) -> NIEN_R[src]
Bit 13 - not Interrupt Enable
pub fn encmdcompl(&self) -> ENCMDCOMPL_R[src]
Bit 12 - Enable CMD completion
pub fn sdiosuspend(&self) -> SDIOSUSPEND_R[src]
Bit 11 - SD I/O suspend command
pub fn cpsmen(&self) -> CPSMEN_R[src]
Bit 10 - Command path state machine (CPSM) Enable bit
pub fn waitpend(&self) -> WAITPEND_R[src]
Bit 9 - CPSM Waits for ends of data transfer (CmdPend internal signal).
pub fn waitint(&self) -> WAITINT_R[src]
Bit 8 - CPSM waits for interrupt request
pub fn waitresp(&self) -> WAITRESP_R[src]
Bits 6:7 - Wait for response bits
pub fn cmdindex(&self) -> CMDINDEX_R[src]
Bits 0:5 - Command index
impl R<u32, Reg<u32, _RESPCMD>>[src]
impl R<u32, Reg<u32, _RESP1>>[src]
pub fn cardstatus1(&self) -> CARDSTATUS1_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _RESP2>>[src]
pub fn cardstatus2(&self) -> CARDSTATUS2_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _RESP3>>[src]
pub fn cardstatus3(&self) -> CARDSTATUS3_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _RESP4>>[src]
pub fn cardstatus4(&self) -> CARDSTATUS4_R[src]
Bits 0:31 - see Table 133.
impl R<u32, Reg<u32, _DTIMER>>[src]
pub fn datatime(&self) -> DATATIME_R[src]
Bits 0:31 - Data timeout period
impl R<u32, Reg<u32, _DLEN>>[src]
pub fn datalength(&self) -> DATALENGTH_R[src]
Bits 0:24 - Data length value
impl R<u32, Reg<u32, _DCTRL>>[src]
pub fn sdioen(&self) -> SDIOEN_R[src]
Bit 11 - SD I/O enable functions
pub fn rwmod(&self) -> RWMOD_R[src]
Bit 10 - Read wait mode
pub fn rwstop(&self) -> RWSTOP_R[src]
Bit 9 - Read wait stop
pub fn rwstart(&self) -> RWSTART_R[src]
Bit 8 - Read wait start
pub fn dblocksize(&self) -> DBLOCKSIZE_R[src]
Bits 4:7 - Data block size
pub fn dmaen(&self) -> DMAEN_R[src]
Bit 3 - DMA enable bit
pub fn dtmode(&self) -> DTMODE_R[src]
Bit 2 - Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
pub fn dtdir(&self) -> DTDIR_R[src]
Bit 1 - Data transfer direction selection
pub fn dten(&self) -> DTEN_R[src]
Bit 0 - Data transfer enabled bit
impl R<u32, Reg<u32, _DCOUNT>>[src]
pub fn datacount(&self) -> DATACOUNT_R[src]
Bits 0:24 - Data count value
impl R<u32, Reg<u32, _STA>>[src]
pub fn ceataend(&self) -> CEATAEND_R[src]
Bit 23 - CE-ATA command completion signal received for CMD61
pub fn sdioit(&self) -> SDIOIT_R[src]
Bit 22 - SDIO interrupt received
pub fn rxdavl(&self) -> RXDAVL_R[src]
Bit 21 - Data available in receive FIFO
pub fn txdavl(&self) -> TXDAVL_R[src]
Bit 20 - Data available in transmit FIFO
pub fn rxfifoe(&self) -> RXFIFOE_R[src]
Bit 19 - Receive FIFO empty
pub fn txfifoe(&self) -> TXFIFOE_R[src]
Bit 18 - Transmit FIFO empty
pub fn rxfifof(&self) -> RXFIFOF_R[src]
Bit 17 - Receive FIFO full
pub fn txfifof(&self) -> TXFIFOF_R[src]
Bit 16 - Transmit FIFO full
pub fn rxfifohf(&self) -> RXFIFOHF_R[src]
Bit 15 - Receive FIFO half full: there are at least 8 words in the FIFO
pub fn txfifohe(&self) -> TXFIFOHE_R[src]
Bit 14 - Transmit FIFO half empty: at least 8 words can be written into the FIFO
pub fn rxact(&self) -> RXACT_R[src]
Bit 13 - Data receive in progress
pub fn txact(&self) -> TXACT_R[src]
Bit 12 - Data transmit in progress
pub fn cmdact(&self) -> CMDACT_R[src]
Bit 11 - Command transfer in progress
pub fn dbckend(&self) -> DBCKEND_R[src]
Bit 10 - Data block sent/received (CRC check passed)
pub fn stbiterr(&self) -> STBITERR_R[src]
Bit 9 - Start bit not detected on all data signals in wide bus mode
pub fn dataend(&self) -> DATAEND_R[src]
Bit 8 - Data end (data counter, SDIDCOUNT, is zero)
pub fn cmdsent(&self) -> CMDSENT_R[src]
Bit 7 - Command sent (no response required)
pub fn cmdrend(&self) -> CMDREND_R[src]
Bit 6 - Command response received (CRC check passed)
pub fn rxoverr(&self) -> RXOVERR_R[src]
Bit 5 - Received FIFO overrun error
pub fn txunderr(&self) -> TXUNDERR_R[src]
Bit 4 - Transmit FIFO underrun error
pub fn dtimeout(&self) -> DTIMEOUT_R[src]
Bit 3 - Data timeout
pub fn ctimeout(&self) -> CTIMEOUT_R[src]
Bit 2 - Command response timeout
pub fn dcrcfail(&self) -> DCRCFAIL_R[src]
Bit 1 - Data block sent/received (CRC check failed)
pub fn ccrcfail(&self) -> CCRCFAIL_R[src]
Bit 0 - Command response received (CRC check failed)
impl R<u32, Reg<u32, _ICR>>[src]
pub fn ceataendc(&self) -> CEATAENDC_R[src]
Bit 23 - CEATAEND flag clear bit
pub fn sdioitc(&self) -> SDIOITC_R[src]
Bit 22 - SDIOIT flag clear bit
pub fn dbckendc(&self) -> DBCKENDC_R[src]
Bit 10 - DBCKEND flag clear bit
pub fn stbiterrc(&self) -> STBITERRC_R[src]
Bit 9 - STBITERR flag clear bit
pub fn dataendc(&self) -> DATAENDC_R[src]
Bit 8 - DATAEND flag clear bit
pub fn cmdsentc(&self) -> CMDSENTC_R[src]
Bit 7 - CMDSENT flag clear bit
pub fn cmdrendc(&self) -> CMDRENDC_R[src]
Bit 6 - CMDREND flag clear bit
pub fn rxoverrc(&self) -> RXOVERRC_R[src]
Bit 5 - RXOVERR flag clear bit
pub fn txunderrc(&self) -> TXUNDERRC_R[src]
Bit 4 - TXUNDERR flag clear bit
pub fn dtimeoutc(&self) -> DTIMEOUTC_R[src]
Bit 3 - DTIMEOUT flag clear bit
pub fn ctimeoutc(&self) -> CTIMEOUTC_R[src]
Bit 2 - CTIMEOUT flag clear bit
pub fn dcrcfailc(&self) -> DCRCFAILC_R[src]
Bit 1 - DCRCFAIL flag clear bit
pub fn ccrcfailc(&self) -> CCRCFAILC_R[src]
Bit 0 - CCRCFAIL flag clear bit
impl R<u32, Reg<u32, _MASK>>[src]
pub fn ceataendie(&self) -> CEATAENDIE_R[src]
Bit 23 - CE-ATA command completion signal received interrupt enable
pub fn sdioitie(&self) -> SDIOITIE_R[src]
Bit 22 - SDIO mode interrupt received interrupt enable
pub fn rxdavlie(&self) -> RXDAVLIE_R[src]
Bit 21 - Data available in Rx FIFO interrupt enable
pub fn txdavlie(&self) -> TXDAVLIE_R[src]
Bit 20 - Data available in Tx FIFO interrupt enable
pub fn rxfifoeie(&self) -> RXFIFOEIE_R[src]
Bit 19 - Rx FIFO empty interrupt enable
pub fn txfifoeie(&self) -> TXFIFOEIE_R[src]
Bit 18 - Tx FIFO empty interrupt enable
pub fn rxfifofie(&self) -> RXFIFOFIE_R[src]
Bit 17 - Rx FIFO full interrupt enable
pub fn txfifofie(&self) -> TXFIFOFIE_R[src]
Bit 16 - Tx FIFO full interrupt enable
pub fn rxfifohfie(&self) -> RXFIFOHFIE_R[src]
Bit 15 - Rx FIFO half full interrupt enable
pub fn txfifoheie(&self) -> TXFIFOHEIE_R[src]
Bit 14 - Tx FIFO half empty interrupt enable
pub fn rxactie(&self) -> RXACTIE_R[src]
Bit 13 - Data receive acting interrupt enable
pub fn txactie(&self) -> TXACTIE_R[src]
Bit 12 - Data transmit acting interrupt enable
pub fn cmdactie(&self) -> CMDACTIE_R[src]
Bit 11 - Command acting interrupt enable
pub fn dbckendie(&self) -> DBCKENDIE_R[src]
Bit 10 - Data block end interrupt enable
pub fn stbiterrie(&self) -> STBITERRIE_R[src]
Bit 9 - Start bit error interrupt enable
pub fn dataendie(&self) -> DATAENDIE_R[src]
Bit 8 - Data end interrupt enable
pub fn cmdsentie(&self) -> CMDSENTIE_R[src]
Bit 7 - Command sent interrupt enable
pub fn cmdrendie(&self) -> CMDRENDIE_R[src]
Bit 6 - Command response received interrupt enable
pub fn rxoverrie(&self) -> RXOVERRIE_R[src]
Bit 5 - Rx FIFO overrun error interrupt enable
pub fn txunderrie(&self) -> TXUNDERRIE_R[src]
Bit 4 - Tx FIFO underrun error interrupt enable
pub fn dtimeoutie(&self) -> DTIMEOUTIE_R[src]
Bit 3 - Data timeout interrupt enable
pub fn ctimeoutie(&self) -> CTIMEOUTIE_R[src]
Bit 2 - Command timeout interrupt enable
pub fn dcrcfailie(&self) -> DCRCFAILIE_R[src]
Bit 1 - Data CRC fail interrupt enable
pub fn ccrcfailie(&self) -> CCRCFAILIE_R[src]
Bit 0 - Command CRC fail interrupt enable
impl R<u32, Reg<u32, _FIFOCNT>>[src]
pub fn fifocount(&self) -> FIFOCOUNT_R[src]
Bits 0:23 - Remaining number of words to be written to or read from the FIFO.
impl R<u32, Reg<u32, _FIFO>>[src]
pub fn fif0data(&self) -> FIF0DATA_R[src]
Bits 0:31 - FIF0Data
impl R<u32, Reg<u32, _CR1>>[src]
pub fn bidimode(&self) -> BIDIMODE_R[src]
Bit 15 - Bidirectional data mode enable
pub fn bidioe(&self) -> BIDIOE_R[src]
Bit 14 - Output enable in bidirectional mode
pub fn crcen(&self) -> CRCEN_R[src]
Bit 13 - Hardware CRC calculation enable
pub fn crcnext(&self) -> CRCNEXT_R[src]
Bit 12 - CRC transfer next
pub fn dff(&self) -> DFF_R[src]
Bit 11 - Data frame format
pub fn rxonly(&self) -> RXONLY_R[src]
Bit 10 - Receive only
pub fn ssm(&self) -> SSM_R[src]
Bit 9 - Software slave management
pub fn ssi(&self) -> SSI_R[src]
Bit 8 - Internal slave select
pub fn lsbfirst(&self) -> LSBFIRST_R[src]
Bit 7 - Frame format
pub fn spe(&self) -> SPE_R[src]
Bit 6 - SPI enable
pub fn br(&self) -> BR_R[src]
Bits 3:5 - Baud rate control
pub fn mstr(&self) -> MSTR_R[src]
Bit 2 - Master selection
pub fn cpol(&self) -> CPOL_R[src]
Bit 1 - Clock polarity
pub fn cpha(&self) -> CPHA_R[src]
Bit 0 - Clock phase
impl R<u32, Reg<u32, _CR2>>[src]
pub fn txeie(&self) -> TXEIE_R[src]
Bit 7 - Tx buffer empty interrupt enable
pub fn rxneie(&self) -> RXNEIE_R[src]
Bit 6 - RX buffer not empty interrupt enable
pub fn errie(&self) -> ERRIE_R[src]
Bit 5 - Error interrupt enable
pub fn frf(&self) -> FRF_R[src]
Bit 4 - Frame format
pub fn ssoe(&self) -> SSOE_R[src]
Bit 2 - SS output enable
pub fn txdmaen(&self) -> TXDMAEN_R[src]
Bit 1 - Tx buffer DMA enable
pub fn rxdmaen(&self) -> RXDMAEN_R[src]
Bit 0 - Rx buffer DMA enable
impl R<u32, Reg<u32, _SR>>[src]
pub fn tifrfe(&self) -> TIFRFE_R[src]
Bit 8 - TI frame format error
pub fn bsy(&self) -> BSY_R[src]
Bit 7 - Busy flag
pub fn ovr(&self) -> OVR_R[src]
Bit 6 - Overrun flag
pub fn modf(&self) -> MODF_R[src]
Bit 5 - Mode fault
pub fn crcerr(&self) -> CRCERR_R[src]
Bit 4 - CRC error flag
pub fn udr(&self) -> UDR_R[src]
Bit 3 - Underrun flag
pub fn chside(&self) -> CHSIDE_R[src]
Bit 2 - Channel side
pub fn txe(&self) -> TXE_R[src]
Bit 1 - Transmit buffer empty
pub fn rxne(&self) -> RXNE_R[src]
Bit 0 - Receive buffer not empty
impl R<u32, Reg<u32, _DR>>[src]
impl R<u32, Reg<u32, _CRCPR>>[src]
impl R<u32, Reg<u32, _RXCRCR>>[src]
impl R<u32, Reg<u32, _TXCRCR>>[src]
impl R<u32, Reg<u32, _I2SCFGR>>[src]
pub fn i2smod(&self) -> I2SMOD_R[src]
Bit 11 - I2S mode selection
pub fn i2se(&self) -> I2SE_R[src]
Bit 10 - I2S Enable
pub fn i2scfg(&self) -> I2SCFG_R[src]
Bits 8:9 - I2S configuration mode
pub fn pcmsync(&self) -> PCMSYNC_R[src]
Bit 7 - PCM frame synchronization
pub fn i2sstd(&self) -> I2SSTD_R[src]
Bits 4:5 - I2S standard selection
pub fn ckpol(&self) -> CKPOL_R[src]
Bit 3 - Steady state clock polarity
pub fn datlen(&self) -> DATLEN_R[src]
Bits 1:2 - Data length to be transferred
pub fn chlen(&self) -> CHLEN_R[src]
Bit 0 - Channel length (number of bits per audio channel)
impl R<u32, Reg<u32, _I2SPR>>[src]
pub fn mckoe(&self) -> MCKOE_R[src]
Bit 9 - Master clock output enable
pub fn odd(&self) -> ODD_R[src]
Bit 8 - Odd factor for the prescaler
pub fn i2sdiv(&self) -> I2SDIV_R[src]
Bits 0:7 - I2S Linear prescaler
impl R<u32, Reg<u32, _MEMRMP>>[src]
pub fn mem_mode(&self) -> MEM_MODE_R[src]
Bits 0:1 - MEM_MODE
pub fn boot_mode(&self) -> BOOT_MODE_R[src]
Bits 8:9 - BOOT_MODE
impl R<u32, Reg<u32, _PMC>>[src]
pub fn usb_pu(&self) -> USB_PU_R[src]
Bit 0 - USB pull-up
pub fn lcd_capa(&self) -> LCD_CAPA_R[src]
Bits 1:5 - decoupling capacitance connection
impl R<u32, Reg<u32, _EXTICR1>>[src]
pub fn exti3(&self) -> EXTI3_R[src]
Bits 12:15 - EXTI x configuration (x = 0 to 3)
pub fn exti2(&self) -> EXTI2_R[src]
Bits 8:11 - EXTI x configuration (x = 0 to 3)
pub fn exti1(&self) -> EXTI1_R[src]
Bits 4:7 - EXTI x configuration (x = 0 to 3)
pub fn exti0(&self) -> EXTI0_R[src]
Bits 0:3 - EXTI x configuration (x = 0 to 3)
impl R<u32, Reg<u32, _EXTICR2>>[src]
pub fn exti7(&self) -> EXTI7_R[src]
Bits 12:15 - EXTI x configuration (x = 4 to 7)
pub fn exti6(&self) -> EXTI6_R[src]
Bits 8:11 - EXTI x configuration (x = 4 to 7)
pub fn exti5(&self) -> EXTI5_R[src]
Bits 4:7 - EXTI x configuration (x = 4 to 7)
pub fn exti4(&self) -> EXTI4_R[src]
Bits 0:3 - EXTI x configuration (x = 4 to 7)
impl R<u32, Reg<u32, _EXTICR3>>[src]
pub fn exti11(&self) -> EXTI11_R[src]
Bits 12:15 - EXTI x configuration (x = 8 to 11)
pub fn exti10(&self) -> EXTI10_R[src]
Bits 8:11 - EXTI10
pub fn exti9(&self) -> EXTI9_R[src]
Bits 4:7 - EXTI x configuration (x = 8 to 11)
pub fn exti8(&self) -> EXTI8_R[src]
Bits 0:3 - EXTI x configuration (x = 8 to 11)
impl R<u32, Reg<u32, _EXTICR4>>[src]
pub fn exti15(&self) -> EXTI15_R[src]
Bits 12:15 - EXTI x configuration (x = 12 to 15)
pub fn exti14(&self) -> EXTI14_R[src]
Bits 8:11 - EXTI14
pub fn exti13(&self) -> EXTI13_R[src]
Bits 4:7 - EXTI13
pub fn exti12(&self) -> EXTI12_R[src]
Bits 0:3 - EXTI12
impl R<u8, CKD_A>[src]
pub fn variant(&self) -> Variant<u8, CKD_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ckd(&self) -> CKD_R[src]
Bits 8:9 - Clock division
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn cc1ie(&self) -> CC1IE_R[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
pub fn cc1of(&self) -> CC1OF_R[src]
Bit 9 - Capture/compare 1 overcapture flag
pub fn cc1if(&self) -> CC1IF_R[src]
Bit 1 - Capture/Compare 1 interrupt flag
pub fn uif(&self) -> UIF_R[src]
Bit 0 - Update interrupt flag
impl R<bool, UG_A>[src]
pub fn variant(&self) -> Variant<bool, UG_A>[src]
Get enumerated values variant
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
impl R<u32, Reg<u32, _EGR>>[src]
pub fn cc1g(&self) -> CC1G_R[src]
Bit 1 - Capture/Compare 1 generation
pub fn ug(&self) -> UG_R[src]
Bit 0 - Update generation
impl R<u32, Reg<u32, _CCMR1_OUTPUT>>[src]
pub fn oc1m(&self) -> OC1M_R[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&self) -> OC1PE_R[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&self) -> OC1FE_R[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u32, Reg<u32, _CCMR1_INPUT>>[src]
pub fn ic1f(&self) -> IC1F_R[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&self) -> IC1PSC_R[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u32, Reg<u32, _CCER>>[src]
pub fn cc1np(&self) -> CC1NP_R[src]
Bit 3 - Capture/Compare 1 complementary output Polarity
pub fn cc1p(&self) -> CC1P_R[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&self) -> CC1E_R[src]
Bit 0 - Capture/Compare 1 output enable
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u32, Reg<u32, _CCR>>[src]
impl R<u32, Reg<u32, _OR>>[src]
impl R<u8, CKD_A>[src]
pub fn variant(&self) -> Variant<u8, CKD_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CMS_A>[src]
pub fn variant(&self) -> CMS_A[src]
Get enumerated values variant
pub fn is_edge_aligned(&self) -> bool[src]
Checks if the value of the field is EDGEALIGNED
pub fn is_center_aligned1(&self) -> bool[src]
Checks if the value of the field is CENTERALIGNED1
pub fn is_center_aligned2(&self) -> bool[src]
Checks if the value of the field is CENTERALIGNED2
pub fn is_center_aligned3(&self) -> bool[src]
Checks if the value of the field is CENTERALIGNED3
impl R<bool, DIR_A>[src]
pub fn variant(&self) -> DIR_A[src]
Get enumerated values variant
pub fn is_up(&self) -> bool[src]
Checks if the value of the field is UP
pub fn is_down(&self) -> bool[src]
Checks if the value of the field is DOWN
impl R<bool, OPM_A>[src]
pub fn variant(&self) -> OPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ckd(&self) -> CKD_R[src]
Bits 8:9 - Clock division
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn cms(&self) -> CMS_R[src]
Bits 5:6 - Center-aligned mode selection
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Direction
pub fn opm(&self) -> OPM_R[src]
Bit 3 - One-pulse mode
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
impl R<bool, TI1S_A>[src]
pub fn variant(&self) -> TI1S_A[src]
Get enumerated values variant
pub fn is_normal(&self) -> bool[src]
Checks if the value of the field is NORMAL
pub fn is_xor(&self) -> bool[src]
Checks if the value of the field is XOR
impl R<u8, MMS_A>[src]
pub fn variant(&self) -> MMS_A[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
pub fn is_enable(&self) -> bool[src]
Checks if the value of the field is ENABLE
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
pub fn is_compare_pulse(&self) -> bool[src]
Checks if the value of the field is COMPAREPULSE
pub fn is_compare_oc1(&self) -> bool[src]
Checks if the value of the field is COMPAREOC1
pub fn is_compare_oc2(&self) -> bool[src]
Checks if the value of the field is COMPAREOC2
pub fn is_compare_oc3(&self) -> bool[src]
Checks if the value of the field is COMPAREOC3
pub fn is_compare_oc4(&self) -> bool[src]
Checks if the value of the field is COMPAREOC4
impl R<bool, CCDS_A>[src]
pub fn variant(&self) -> CCDS_A[src]
Get enumerated values variant
pub fn is_on_compare(&self) -> bool[src]
Checks if the value of the field is ONCOMPARE
pub fn is_on_update(&self) -> bool[src]
Checks if the value of the field is ONUPDATE
impl R<u32, Reg<u32, _CR2>>[src]
pub fn ti1s(&self) -> TI1S_R[src]
Bit 7 - TI1 selection
pub fn mms(&self) -> MMS_R[src]
Bits 4:6 - Master mode selection
pub fn ccds(&self) -> CCDS_R[src]
Bit 3 - Capture/compare DMA selection
impl R<bool, ETP_A>[src]
pub fn variant(&self) -> ETP_A[src]
Get enumerated values variant
pub fn is_not_inverted(&self) -> bool[src]
Checks if the value of the field is NOTINVERTED
pub fn is_inverted(&self) -> bool[src]
Checks if the value of the field is INVERTED
impl R<bool, ECE_A>[src]
pub fn variant(&self) -> ECE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, ETPS_A>[src]
pub fn variant(&self) -> ETPS_A[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
pub fn is_div8(&self) -> bool[src]
Checks if the value of the field is DIV8
impl R<u8, ETF_A>[src]
pub fn variant(&self) -> ETF_A[src]
Get enumerated values variant
pub fn is_no_filter(&self) -> bool[src]
Checks if the value of the field is NOFILTER
pub fn is_fck_int_n2(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N2
pub fn is_fck_int_n4(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N4
pub fn is_fck_int_n8(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N8
pub fn is_fdts_div2_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N6
pub fn is_fdts_div2_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N8
pub fn is_fdts_div4_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N6
pub fn is_fdts_div4_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N8
pub fn is_fdts_div8_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N6
pub fn is_fdts_div8_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N8
pub fn is_fdts_div16_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N5
pub fn is_fdts_div16_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N6
pub fn is_fdts_div16_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N8
pub fn is_fdts_div32_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N5
pub fn is_fdts_div32_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N6
pub fn is_fdts_div32_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N8
impl R<bool, MSM_A>[src]
pub fn variant(&self) -> MSM_A[src]
Get enumerated values variant
pub fn is_no_sync(&self) -> bool[src]
Checks if the value of the field is NOSYNC
pub fn is_sync(&self) -> bool[src]
Checks if the value of the field is SYNC
impl R<u8, TS_A>[src]
pub fn variant(&self) -> Variant<u8, TS_A>[src]
Get enumerated values variant
pub fn is_itr0(&self) -> bool[src]
Checks if the value of the field is ITR0
pub fn is_itr1(&self) -> bool[src]
Checks if the value of the field is ITR1
pub fn is_itr2(&self) -> bool[src]
Checks if the value of the field is ITR2
pub fn is_ti1f_ed(&self) -> bool[src]
Checks if the value of the field is TI1F_ED
pub fn is_ti1fp1(&self) -> bool[src]
Checks if the value of the field is TI1FP1
pub fn is_ti2fp2(&self) -> bool[src]
Checks if the value of the field is TI2FP2
pub fn is_etrf(&self) -> bool[src]
Checks if the value of the field is ETRF
impl R<u8, SMS_A>[src]
pub fn variant(&self) -> SMS_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_encoder_mode_1(&self) -> bool[src]
Checks if the value of the field is ENCODER_MODE_1
pub fn is_encoder_mode_2(&self) -> bool[src]
Checks if the value of the field is ENCODER_MODE_2
pub fn is_encoder_mode_3(&self) -> bool[src]
Checks if the value of the field is ENCODER_MODE_3
pub fn is_reset_mode(&self) -> bool[src]
Checks if the value of the field is RESET_MODE
pub fn is_gated_mode(&self) -> bool[src]
Checks if the value of the field is GATED_MODE
pub fn is_trigger_mode(&self) -> bool[src]
Checks if the value of the field is TRIGGER_MODE
pub fn is_ext_clock_mode(&self) -> bool[src]
Checks if the value of the field is EXT_CLOCK_MODE
impl R<u32, Reg<u32, _SMCR>>[src]
pub fn etp(&self) -> ETP_R[src]
Bit 15 - External trigger polarity
pub fn ece(&self) -> ECE_R[src]
Bit 14 - External clock enable
pub fn etps(&self) -> ETPS_R[src]
Bits 12:13 - External trigger prescaler
pub fn etf(&self) -> ETF_R[src]
Bits 8:11 - External trigger filter
pub fn msm(&self) -> MSM_R[src]
Bit 7 - Master/Slave mode
pub fn ts(&self) -> TS_R[src]
Bits 4:6 - Trigger selection
pub fn occs(&self) -> OCCS_R[src]
Bit 3 - OCREF clear selection
pub fn sms(&self) -> SMS_R[src]
Bits 0:2 - Slave mode selection
impl R<bool, TDE_A>[src]
pub fn variant(&self) -> TDE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC4DE_A>[src]
pub fn variant(&self) -> CC4DE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, UDE_A>[src]
pub fn variant(&self) -> UDE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, TIE_A>[src]
pub fn variant(&self) -> TIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC4IE_A>[src]
pub fn variant(&self) -> CC4IE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn tde(&self) -> TDE_R[src]
Bit 14 - Trigger DMA request enable
pub fn cc4de(&self) -> CC4DE_R[src]
Bit 12 - Capture/Compare 4 DMA request enable
pub fn cc3de(&self) -> CC3DE_R[src]
Bit 11 - Capture/Compare 3 DMA request enable
pub fn cc2de(&self) -> CC2DE_R[src]
Bit 10 - Capture/Compare 2 DMA request enable
pub fn cc1de(&self) -> CC1DE_R[src]
Bit 9 - Capture/Compare 1 DMA request enable
pub fn ude(&self) -> UDE_R[src]
Bit 8 - Update DMA request enable
pub fn tie(&self) -> TIE_R[src]
Bit 6 - Trigger interrupt enable
pub fn cc4ie(&self) -> CC4IE_R[src]
Bit 4 - Capture/Compare 4 interrupt enable
pub fn cc3ie(&self) -> CC3IE_R[src]
Bit 3 - Capture/Compare 3 interrupt enable
pub fn cc2ie(&self) -> CC2IE_R[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&self) -> CC1IE_R[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
impl R<bool, CC4OF_A>[src]
pub fn variant(&self) -> Variant<bool, CC4OF_A>[src]
Get enumerated values variant
pub fn is_overcapture(&self) -> bool[src]
Checks if the value of the field is OVERCAPTURE
impl R<bool, TIF_A>[src]
pub fn variant(&self) -> TIF_A[src]
Get enumerated values variant
pub fn is_no_trigger(&self) -> bool[src]
Checks if the value of the field is NOTRIGGER
pub fn is_trigger(&self) -> bool[src]
Checks if the value of the field is TRIGGER
impl R<bool, CC4IF_A>[src]
pub fn variant(&self) -> Variant<bool, CC4IF_A>[src]
Get enumerated values variant
pub fn is_match_(&self) -> bool[src]
Checks if the value of the field is MATCH
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
pub fn cc4of(&self) -> CC4OF_R[src]
Bit 12 - Capture/compare 1 overcapture flag
pub fn cc3of(&self) -> CC3OF_R[src]
Bit 11 - Capture/compare 3 overcapture flag
pub fn cc2of(&self) -> CC2OF_R[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&self) -> CC1OF_R[src]
Bit 9 - Capture/compare 1 overcapture flag
pub fn tif(&self) -> TIF_R[src]
Bit 6 - Trigger interrupt flag
pub fn cc4if(&self) -> CC4IF_R[src]
Bit 4 - Capture/Compare 4 interrupt flag
pub fn cc3if(&self) -> CC3IF_R[src]
Bit 3 - Capture/Compare 3 interrupt flag
pub fn cc2if(&self) -> CC2IF_R[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&self) -> CC1IF_R[src]
Bit 1 - Capture/Compare 1 interrupt flag
pub fn uif(&self) -> UIF_R[src]
Bit 0 - Update interrupt flag
impl R<bool, TG_A>[src]
pub fn variant(&self) -> Variant<bool, TG_A>[src]
Get enumerated values variant
pub fn is_trigger(&self) -> bool[src]
Checks if the value of the field is TRIGGER
impl R<bool, CC4G_A>[src]
pub fn variant(&self) -> Variant<bool, CC4G_A>[src]
Get enumerated values variant
pub fn is_trigger(&self) -> bool[src]
Checks if the value of the field is TRIGGER
impl R<bool, UG_A>[src]
pub fn variant(&self) -> Variant<bool, UG_A>[src]
Get enumerated values variant
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
impl R<u32, Reg<u32, _EGR>>[src]
pub fn tg(&self) -> TG_R[src]
Bit 6 - Trigger generation
pub fn cc4g(&self) -> CC4G_R[src]
Bit 4 - Capture/compare 4 generation
pub fn cc3g(&self) -> CC3G_R[src]
Bit 3 - Capture/compare 3 generation
pub fn cc2g(&self) -> CC2G_R[src]
Bit 2 - Capture/compare 2 generation
pub fn cc1g(&self) -> CC1G_R[src]
Bit 1 - Capture/compare 1 generation
pub fn ug(&self) -> UG_R[src]
Bit 0 - Update generation
impl R<u8, OC2M_A>[src]
pub fn variant(&self) -> OC2M_A[src]
Get enumerated values variant
pub fn is_frozen(&self) -> bool[src]
Checks if the value of the field is FROZEN
pub fn is_active_on_match(&self) -> bool[src]
Checks if the value of the field is ACTIVEONMATCH
pub fn is_inactive_on_match(&self) -> bool[src]
Checks if the value of the field is INACTIVEONMATCH
pub fn is_toggle(&self) -> bool[src]
Checks if the value of the field is TOGGLE
pub fn is_force_inactive(&self) -> bool[src]
Checks if the value of the field is FORCEINACTIVE
pub fn is_force_active(&self) -> bool[src]
Checks if the value of the field is FORCEACTIVE
pub fn is_pwm_mode1(&self) -> bool[src]
Checks if the value of the field is PWMMODE1
pub fn is_pwm_mode2(&self) -> bool[src]
Checks if the value of the field is PWMMODE2
impl R<bool, OC2PE_A>[src]
pub fn variant(&self) -> OC2PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC2S_A>[src]
pub fn variant(&self) -> Variant<bool, CC2S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<bool, OC1PE_A>[src]
pub fn variant(&self) -> OC1PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CC1S_A>[src]
pub fn variant(&self) -> Variant<u8, CC1S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<u32, Reg<u32, _CCMR1_OUTPUT>>[src]
pub fn oc2ce(&self) -> OC2CE_R[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&self) -> OC2M_R[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&self) -> OC2PE_R[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&self) -> OC2FE_R[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&self) -> CC2S_R[src]
Bit 8 - Capture/Compare 2 selection
pub fn oc1ce(&self) -> OC1CE_R[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&self) -> OC1M_R[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&self) -> OC1PE_R[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&self) -> OC1FE_R[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u8, CC2S_A>[src]
pub fn variant(&self) -> Variant<u8, CC2S_A>[src]
Get enumerated values variant
pub fn is_ti2(&self) -> bool[src]
Checks if the value of the field is TI2
pub fn is_ti1(&self) -> bool[src]
Checks if the value of the field is TI1
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u8, IC1F_A>[src]
pub fn variant(&self) -> IC1F_A[src]
Get enumerated values variant
pub fn is_no_filter(&self) -> bool[src]
Checks if the value of the field is NOFILTER
pub fn is_fck_int_n2(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N2
pub fn is_fck_int_n4(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N4
pub fn is_fck_int_n8(&self) -> bool[src]
Checks if the value of the field is FCK_INT_N8
pub fn is_fdts_div2_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N6
pub fn is_fdts_div2_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV2_N8
pub fn is_fdts_div4_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N6
pub fn is_fdts_div4_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV4_N8
pub fn is_fdts_div8_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N6
pub fn is_fdts_div8_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV8_N8
pub fn is_fdts_div16_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N5
pub fn is_fdts_div16_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N6
pub fn is_fdts_div16_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV16_N8
pub fn is_fdts_div32_n5(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N5
pub fn is_fdts_div32_n6(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N6
pub fn is_fdts_div32_n8(&self) -> bool[src]
Checks if the value of the field is FDTS_DIV32_N8
impl R<u8, CC1S_A>[src]
pub fn variant(&self) -> Variant<u8, CC1S_A>[src]
Get enumerated values variant
pub fn is_ti1(&self) -> bool[src]
Checks if the value of the field is TI1
pub fn is_ti2(&self) -> bool[src]
Checks if the value of the field is TI2
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u32, Reg<u32, _CCMR1_INPUT>>[src]
pub fn ic2f(&self) -> IC2F_R[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&self) -> IC2PSC_R[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&self) -> CC2S_R[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&self) -> IC1F_R[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&self) -> IC1PSC_R[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u8, OC4M_A>[src]
pub fn variant(&self) -> OC4M_A[src]
Get enumerated values variant
pub fn is_frozen(&self) -> bool[src]
Checks if the value of the field is FROZEN
pub fn is_active_on_match(&self) -> bool[src]
Checks if the value of the field is ACTIVEONMATCH
pub fn is_inactive_on_match(&self) -> bool[src]
Checks if the value of the field is INACTIVEONMATCH
pub fn is_toggle(&self) -> bool[src]
Checks if the value of the field is TOGGLE
pub fn is_force_inactive(&self) -> bool[src]
Checks if the value of the field is FORCEINACTIVE
pub fn is_force_active(&self) -> bool[src]
Checks if the value of the field is FORCEACTIVE
pub fn is_pwm_mode1(&self) -> bool[src]
Checks if the value of the field is PWMMODE1
pub fn is_pwm_mode2(&self) -> bool[src]
Checks if the value of the field is PWMMODE2
impl R<bool, OC4PE_A>[src]
pub fn variant(&self) -> OC4PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CC4S_A>[src]
pub fn variant(&self) -> Variant<bool, CC4S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<bool, OC3PE_A>[src]
pub fn variant(&self) -> OC3PE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u8, CC3S_A>[src]
pub fn variant(&self) -> Variant<u8, CC3S_A>[src]
Get enumerated values variant
pub fn is_output(&self) -> bool[src]
Checks if the value of the field is OUTPUT
impl R<u32, Reg<u32, _CCMR2_OUTPUT>>[src]
pub fn oc4ce(&self) -> OC4CE_R[src]
Bit 15 - Output compare 4 clear enable
pub fn oc4m(&self) -> OC4M_R[src]
Bits 12:14 - Output compare 4 mode
pub fn oc4pe(&self) -> OC4PE_R[src]
Bit 11 - Output compare 4 preload enable
pub fn oc4fe(&self) -> OC4FE_R[src]
Bit 10 - Output compare 4 fast enable
pub fn cc4s(&self) -> CC4S_R[src]
Bit 8 - Capture/Compare 4 selection
pub fn oc3ce(&self) -> OC3CE_R[src]
Bit 7 - Output compare 3 clear enable
pub fn oc3m(&self) -> OC3M_R[src]
Bits 4:6 - Output compare 3 mode
pub fn oc3pe(&self) -> OC3PE_R[src]
Bit 3 - Output compare 3 preload enable
pub fn oc3fe(&self) -> OC3FE_R[src]
Bit 2 - Output compare 3 fast enable
pub fn cc3s(&self) -> CC3S_R[src]
Bits 0:1 - Capture/Compare 3 selection
impl R<u8, CC4S_A>[src]
pub fn variant(&self) -> Variant<u8, CC4S_A>[src]
Get enumerated values variant
pub fn is_ti4(&self) -> bool[src]
Checks if the value of the field is TI4
pub fn is_ti3(&self) -> bool[src]
Checks if the value of the field is TI3
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u8, CC3S_A>[src]
pub fn variant(&self) -> Variant<u8, CC3S_A>[src]
Get enumerated values variant
pub fn is_ti3(&self) -> bool[src]
Checks if the value of the field is TI3
pub fn is_ti4(&self) -> bool[src]
Checks if the value of the field is TI4
pub fn is_trc(&self) -> bool[src]
Checks if the value of the field is TRC
impl R<u32, Reg<u32, _CCMR2_INPUT>>[src]
pub fn ic4f(&self) -> IC4F_R[src]
Bits 12:15 - Input capture 4 filter
pub fn ic4psc(&self) -> IC4PSC_R[src]
Bits 10:11 - Input capture 4 prescaler
pub fn cc4s(&self) -> CC4S_R[src]
Bits 8:9 - Capture/Compare 4 selection
pub fn ic3f(&self) -> IC3F_R[src]
Bits 4:7 - Input capture 3 filter
pub fn ic3psc(&self) -> IC3PSC_R[src]
Bits 2:3 - Input capture 3 prescaler
pub fn cc3s(&self) -> CC3S_R[src]
Bits 0:1 - Capture/compare 3 selection
impl R<u32, Reg<u32, _CCER>>[src]
pub fn cc4np(&self) -> CC4NP_R[src]
Bit 15 - Capture/Compare 4 output Polarity
pub fn cc4p(&self) -> CC4P_R[src]
Bit 13 - Capture/Compare 4 output Polarity
pub fn cc4e(&self) -> CC4E_R[src]
Bit 12 - Capture/Compare 4 output enable
pub fn cc3np(&self) -> CC3NP_R[src]
Bit 11 - Capture/Compare 3 output Polarity
pub fn cc3p(&self) -> CC3P_R[src]
Bit 9 - Capture/Compare 3 output Polarity
pub fn cc3e(&self) -> CC3E_R[src]
Bit 8 - Capture/Compare 3 output enable
pub fn cc2np(&self) -> CC2NP_R[src]
Bit 7 - Capture/Compare 2 output Polarity
pub fn cc2p(&self) -> CC2P_R[src]
Bit 5 - Capture/Compare 2 output Polarity
pub fn cc2e(&self) -> CC2E_R[src]
Bit 4 - Capture/Compare 2 output enable
pub fn cc1np(&self) -> CC1NP_R[src]
Bit 3 - Capture/Compare 1 complementary output Polarity
pub fn cc1p(&self) -> CC1P_R[src]
Bit 1 - Capture/Compare 1 output Polarity
pub fn cc1e(&self) -> CC1E_R[src]
Bit 0 - Capture/Compare 1 output enable
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u32, Reg<u32, _CCR>>[src]
impl R<u32, Reg<u32, _DCR>>[src]
pub fn dbl(&self) -> DBL_R[src]
Bits 8:12 - DMA burst length
pub fn dba(&self) -> DBA_R[src]
Bits 0:4 - DMA base address
impl R<u32, Reg<u32, _DMAR>>[src]
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, OPM_A>[src]
pub fn variant(&self) -> OPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&self) -> OPM_R[src]
Bit 3 - One-pulse mode
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
impl R<u8, MMS_A>[src]
pub fn variant(&self) -> Variant<u8, MMS_A>[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
pub fn is_enable(&self) -> bool[src]
Checks if the value of the field is ENABLE
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
impl R<u32, Reg<u32, _CR2>>[src]
impl R<bool, UDE_A>[src]
pub fn variant(&self) -> UDE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn ude(&self) -> UDE_R[src]
Bit 8 - Update DMA request enable
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
pub fn psc(&self) -> PSC_R[src]
Bits 0:15 - Prescaler valueThe counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u8, CKD_A>[src]
pub fn variant(&self) -> Variant<u8, CKD_A>[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
impl R<bool, ARPE_A>[src]
pub fn variant(&self) -> ARPE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, OPM_A>[src]
pub fn variant(&self) -> OPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, URS_A>[src]
pub fn variant(&self) -> URS_A[src]
Get enumerated values variant
pub fn is_any_event(&self) -> bool[src]
Checks if the value of the field is ANYEVENT
pub fn is_counter_only(&self) -> bool[src]
Checks if the value of the field is COUNTERONLY
impl R<bool, UDIS_A>[src]
pub fn variant(&self) -> UDIS_A[src]
Get enumerated values variant
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
impl R<bool, CEN_A>[src]
pub fn variant(&self) -> CEN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ckd(&self) -> CKD_R[src]
Bits 8:9 - Clock division
pub fn arpe(&self) -> ARPE_R[src]
Bit 7 - Auto-reload preload enable
pub fn opm(&self) -> OPM_R[src]
Bit 3 - One-pulse mode
pub fn urs(&self) -> URS_R[src]
Bit 2 - Update request source
pub fn udis(&self) -> UDIS_R[src]
Bit 1 - Update disable
pub fn cen(&self) -> CEN_R[src]
Bit 0 - Counter enable
impl R<u32, Reg<u32, _CR2>>[src]
impl R<u32, Reg<u32, _SMCR>>[src]
pub fn msm(&self) -> MSM_R[src]
Bit 7 - Master/Slave mode
pub fn ts(&self) -> TS_R[src]
Bits 4:6 - Trigger selection
pub fn sms(&self) -> SMS_R[src]
Bits 0:2 - Slave mode selection
impl R<bool, UIE_A>[src]
pub fn variant(&self) -> UIE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DIER>>[src]
pub fn tie(&self) -> TIE_R[src]
Bit 6 - Trigger interrupt enable
pub fn cc2ie(&self) -> CC2IE_R[src]
Bit 2 - Capture/Compare 2 interrupt enable
pub fn cc1ie(&self) -> CC1IE_R[src]
Bit 1 - Capture/Compare 1 interrupt enable
pub fn uie(&self) -> UIE_R[src]
Bit 0 - Update interrupt enable
impl R<bool, UIF_A>[src]
pub fn variant(&self) -> UIF_A[src]
Get enumerated values variant
pub fn is_clear(&self) -> bool[src]
Checks if the value of the field is CLEAR
pub fn is_update_pending(&self) -> bool[src]
Checks if the value of the field is UPDATEPENDING
impl R<u32, Reg<u32, _SR>>[src]
pub fn cc2of(&self) -> CC2OF_R[src]
Bit 10 - Capture/compare 2 overcapture flag
pub fn cc1of(&self) -> CC1OF_R[src]
Bit 9 - Capture/compare 1 overcapture flag
pub fn tif(&self) -> TIF_R[src]
Bit 6 - Trigger interrupt flag
pub fn cc2if(&self) -> CC2IF_R[src]
Bit 2 - Capture/Compare 2 interrupt flag
pub fn cc1if(&self) -> CC1IF_R[src]
Bit 1 - Capture/Compare 1 interrupt flag
pub fn uif(&self) -> UIF_R[src]
Bit 0 - Update interrupt flag
impl R<bool, UG_A>[src]
pub fn variant(&self) -> Variant<bool, UG_A>[src]
Get enumerated values variant
pub fn is_update(&self) -> bool[src]
Checks if the value of the field is UPDATE
impl R<u32, Reg<u32, _EGR>>[src]
pub fn tg(&self) -> TG_R[src]
Bit 6 - Trigger generation
pub fn cc2g(&self) -> CC2G_R[src]
Bit 2 - Capture/Compare 2 generation
pub fn cc1g(&self) -> CC1G_R[src]
Bit 1 - Capture/Compare 1 generation
pub fn ug(&self) -> UG_R[src]
Bit 0 - Update generation
impl R<u32, Reg<u32, _CCMR1_OUTPUT>>[src]
pub fn oc2ce(&self) -> OC2CE_R[src]
Bit 15 - Output compare 2 clear enable
pub fn oc2m(&self) -> OC2M_R[src]
Bits 12:14 - Output compare 2 mode
pub fn oc2pe(&self) -> OC2PE_R[src]
Bit 11 - Output compare 2 preload enable
pub fn oc2fe(&self) -> OC2FE_R[src]
Bit 10 - Output compare 2 fast enable
pub fn cc2s(&self) -> CC2S_R[src]
Bit 8 - Capture/Compare 2 selection
pub fn oc1ce(&self) -> OC1CE_R[src]
Bit 7 - Output compare 1 clear enable
pub fn oc1m(&self) -> OC1M_R[src]
Bits 4:6 - Output compare 1 mode
pub fn oc1pe(&self) -> OC1PE_R[src]
Bit 3 - Output compare 1 preload enable
pub fn oc1fe(&self) -> OC1FE_R[src]
Bit 2 - Output compare 1 fast enable
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u32, Reg<u32, _CCMR1_INPUT>>[src]
pub fn ic2f(&self) -> IC2F_R[src]
Bits 12:15 - Input capture 2 filter
pub fn ic2psc(&self) -> IC2PSC_R[src]
Bits 10:11 - Input capture 2 prescaler
pub fn cc2s(&self) -> CC2S_R[src]
Bits 8:9 - Capture/Compare 2 selection
pub fn ic1f(&self) -> IC1F_R[src]
Bits 4:7 - Input capture 1 filter
pub fn ic1psc(&self) -> IC1PSC_R[src]
Bits 2:3 - Input capture 1 prescaler
pub fn cc1s(&self) -> CC1S_R[src]
Bits 0:1 - Capture/Compare 1 selection
impl R<u32, Reg<u32, _CNT>>[src]
impl R<u32, Reg<u32, _PSC>>[src]
impl R<u32, Reg<u32, _ARR>>[src]
impl R<u32, Reg<u32, _CCR>>[src]
impl R<u32, Reg<u32, _OR>>[src]
impl R<u32, Reg<u32, _SR>>[src]
pub fn cts(&self) -> CTS_R[src]
Bit 9 - CTS flag
pub fn lbd(&self) -> LBD_R[src]
Bit 8 - LIN break detection flag
pub fn txe(&self) -> TXE_R[src]
Bit 7 - Transmit data register empty
pub fn tc(&self) -> TC_R[src]
Bit 6 - Transmission complete
pub fn rxne(&self) -> RXNE_R[src]
Bit 5 - Read data register not empty
pub fn idle(&self) -> IDLE_R[src]
Bit 4 - IDLE line detected
pub fn ore(&self) -> ORE_R[src]
Bit 3 - Overrun error
pub fn nf(&self) -> NF_R[src]
Bit 2 - Noise detected flag
pub fn fe(&self) -> FE_R[src]
Bit 1 - Framing error
pub fn pe(&self) -> PE_R[src]
Bit 0 - Parity error
impl R<u32, Reg<u32, _DR>>[src]
impl R<u32, Reg<u32, _BRR>>[src]
pub fn div_mantissa(&self) -> DIV_MANTISSA_R[src]
Bits 4:15 - mantissa of USARTDIV
pub fn div_fraction(&self) -> DIV_FRACTION_R[src]
Bits 0:3 - fraction of USARTDIV
impl R<u32, Reg<u32, _CR1>>[src]
pub fn over8(&self) -> OVER8_R[src]
Bit 15 - Oversampling mode
pub fn ue(&self) -> UE_R[src]
Bit 13 - USART enable
pub fn m(&self) -> M_R[src]
Bit 12 - Word length
pub fn wake(&self) -> WAKE_R[src]
Bit 11 - Wakeup method
pub fn pce(&self) -> PCE_R[src]
Bit 10 - Parity control enable
pub fn ps(&self) -> PS_R[src]
Bit 9 - Parity selection
pub fn peie(&self) -> PEIE_R[src]
Bit 8 - PE interrupt enable
pub fn txeie(&self) -> TXEIE_R[src]
Bit 7 - TXE interrupt enable
pub fn tcie(&self) -> TCIE_R[src]
Bit 6 - Transmission complete interrupt enable
pub fn rxneie(&self) -> RXNEIE_R[src]
Bit 5 - RXNE interrupt enable
pub fn idleie(&self) -> IDLEIE_R[src]
Bit 4 - IDLE interrupt enable
pub fn te(&self) -> TE_R[src]
Bit 3 - Transmitter enable
pub fn re(&self) -> RE_R[src]
Bit 2 - Receiver enable
pub fn rwu(&self) -> RWU_R[src]
Bit 1 - Receiver wakeup
pub fn sbk(&self) -> SBK_R[src]
Bit 0 - Send break
impl R<u32, Reg<u32, _CR2>>[src]
pub fn linen(&self) -> LINEN_R[src]
Bit 14 - LIN mode enable
pub fn stop(&self) -> STOP_R[src]
Bits 12:13 - STOP bits
pub fn clken(&self) -> CLKEN_R[src]
Bit 11 - Clock enable
pub fn cpol(&self) -> CPOL_R[src]
Bit 10 - Clock polarity
pub fn cpha(&self) -> CPHA_R[src]
Bit 9 - Clock phase
pub fn lbcl(&self) -> LBCL_R[src]
Bit 8 - Last bit clock pulse
pub fn lbdie(&self) -> LBDIE_R[src]
Bit 6 - LIN break detection interrupt enable
pub fn lbdl(&self) -> LBDL_R[src]
Bit 5 - lin break detection length
pub fn add(&self) -> ADD_R[src]
Bits 0:3 - Address of the USART node
impl R<u32, Reg<u32, _CR3>>[src]
pub fn onebit(&self) -> ONEBIT_R[src]
Bit 11 - One sample bit method enable
pub fn ctsie(&self) -> CTSIE_R[src]
Bit 10 - CTS interrupt enable
pub fn ctse(&self) -> CTSE_R[src]
Bit 9 - CTS enable
pub fn rtse(&self) -> RTSE_R[src]
Bit 8 - RTS enable
pub fn dmat(&self) -> DMAT_R[src]
Bit 7 - DMA enable transmitter
pub fn dmar(&self) -> DMAR_R[src]
Bit 6 - DMA enable receiver
pub fn scen(&self) -> SCEN_R[src]
Bit 5 - Smartcard mode enable
pub fn nack(&self) -> NACK_R[src]
Bit 4 - Smartcard NACK enable
pub fn hdsel(&self) -> HDSEL_R[src]
Bit 3 - Half-duplex selection
pub fn irlp(&self) -> IRLP_R[src]
Bit 2 - IrDA low-power
pub fn iren(&self) -> IREN_R[src]
Bit 1 - IrDA mode enable
pub fn eie(&self) -> EIE_R[src]
Bit 0 - Error interrupt enable
impl R<u32, Reg<u32, _GTPR>>[src]
pub fn gt(&self) -> GT_R[src]
Bits 8:15 - Guard time value
pub fn psc(&self) -> PSC_R[src]
Bits 0:7 - Prescaler value
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP0R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP1R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP2R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP3R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP4R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP5R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP6R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<u8, STAT_TX_A>[src]
pub fn variant(&self) -> STAT_TX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u8, EP_TYPE_A>[src]
pub fn variant(&self) -> EP_TYPE_A[src]
Get enumerated values variant
pub fn is_bulk(&self) -> bool[src]
Checks if the value of the field is BULK
pub fn is_control(&self) -> bool[src]
Checks if the value of the field is CONTROL
pub fn is_iso(&self) -> bool[src]
Checks if the value of the field is ISO
pub fn is_interrupt(&self) -> bool[src]
Checks if the value of the field is INTERRUPT
impl R<u8, STAT_RX_A>[src]
pub fn variant(&self) -> STAT_RX_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_stall(&self) -> bool[src]
Checks if the value of the field is STALL
pub fn is_nak(&self) -> bool[src]
Checks if the value of the field is NAK
pub fn is_valid(&self) -> bool[src]
Checks if the value of the field is VALID
impl R<u32, Reg<u32, _EP7R>>[src]
pub fn ea(&self) -> EA_R[src]
Bits 0:3 - Endpoint address
pub fn stat_tx(&self) -> STAT_TX_R[src]
Bits 4:5 - Status bits, for transmission transfers
pub fn dtog_tx(&self) -> DTOG_TX_R[src]
Bit 6 - Data Toggle, for transmission transfers
pub fn ctr_tx(&self) -> CTR_TX_R[src]
Bit 7 - Correct Transfer for transmission
pub fn ep_kind(&self) -> EP_KIND_R[src]
Bit 8 - Endpoint kind
pub fn ep_type(&self) -> EP_TYPE_R[src]
Bits 9:10 - Endpoint type
pub fn setup(&self) -> SETUP_R[src]
Bit 11 - Setup transaction completed
pub fn stat_rx(&self) -> STAT_RX_R[src]
Bits 12:13 - Status bits, for reception transfers
pub fn dtog_rx(&self) -> DTOG_RX_R[src]
Bit 14 - Data Toggle, for reception transfers
pub fn ctr_rx(&self) -> CTR_RX_R[src]
Bit 15 - Correct transfer for reception
impl R<bool, FRES_A>[src]
pub fn variant(&self) -> FRES_A[src]
Get enumerated values variant
pub fn is_no_reset(&self) -> bool[src]
Checks if the value of the field is NORESET
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<bool, PDWN_A>[src]
pub fn variant(&self) -> PDWN_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, LPMODE_A>[src]
pub fn variant(&self) -> LPMODE_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, FSUSP_A>[src]
pub fn variant(&self) -> FSUSP_A[src]
Get enumerated values variant
pub fn is_no_effect(&self) -> bool[src]
Checks if the value of the field is NOEFFECT
pub fn is_suspend(&self) -> bool[src]
Checks if the value of the field is SUSPEND
impl R<bool, RESUME_A>[src]
pub fn variant(&self) -> Variant<bool, RESUME_A>[src]
Get enumerated values variant
pub fn is_requested(&self) -> bool[src]
Checks if the value of the field is REQUESTED
impl R<bool, ESOFM_A>[src]
pub fn variant(&self) -> ESOFM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, SOFM_A>[src]
pub fn variant(&self) -> SOFM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, RESETM_A>[src]
pub fn variant(&self) -> RESETM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, SUSPM_A>[src]
pub fn variant(&self) -> SUSPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, WKUPM_A>[src]
pub fn variant(&self) -> WKUPM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, ERRM_A>[src]
pub fn variant(&self) -> ERRM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, PMAOVRM_A>[src]
pub fn variant(&self) -> PMAOVRM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<bool, CTRM_A>[src]
pub fn variant(&self) -> CTRM_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _CNTR>>[src]
pub fn fres(&self) -> FRES_R[src]
Bit 0 - Force USB Reset
pub fn pdwn(&self) -> PDWN_R[src]
Bit 1 - Power down
pub fn lpmode(&self) -> LPMODE_R[src]
Bit 2 - Low-power mode
pub fn fsusp(&self) -> FSUSP_R[src]
Bit 3 - Force suspend
pub fn resume(&self) -> RESUME_R[src]
Bit 4 - Resume request
pub fn esofm(&self) -> ESOFM_R[src]
Bit 8 - Expected start of frame interrupt mask
pub fn sofm(&self) -> SOFM_R[src]
Bit 9 - Start of frame interrupt mask
pub fn resetm(&self) -> RESETM_R[src]
Bit 10 - USB reset interrupt mask
pub fn suspm(&self) -> SUSPM_R[src]
Bit 11 - Suspend mode interrupt mask
pub fn wkupm(&self) -> WKUPM_R[src]
Bit 12 - Wakeup interrupt mask
pub fn errm(&self) -> ERRM_R[src]
Bit 13 - Error interrupt mask
pub fn pmaovrm(&self) -> PMAOVRM_R[src]
Bit 14 - Packet memory area over / underrun interrupt mask
pub fn ctrm(&self) -> CTRM_R[src]
Bit 15 - Correct transfer interrupt mask
impl R<bool, DIR_A>[src]
pub fn variant(&self) -> DIR_A[src]
Get enumerated values variant
pub fn is_to(&self) -> bool[src]
Checks if the value of the field is TO
pub fn is_from(&self) -> bool[src]
Checks if the value of the field is FROM
impl R<bool, ESOF_A>[src]
pub fn variant(&self) -> Variant<bool, ESOF_A>[src]
Get enumerated values variant
pub fn is_expected_start_of_frame(&self) -> bool[src]
Checks if the value of the field is EXPECTEDSTARTOFFRAME
impl R<bool, SOF_A>[src]
pub fn variant(&self) -> Variant<bool, SOF_A>[src]
Get enumerated values variant
pub fn is_start_of_frame(&self) -> bool[src]
Checks if the value of the field is STARTOFFRAME
impl R<bool, RESET_A>[src]
pub fn variant(&self) -> Variant<bool, RESET_A>[src]
Get enumerated values variant
pub fn is_reset(&self) -> bool[src]
Checks if the value of the field is RESET
impl R<bool, SUSP_A>[src]
pub fn variant(&self) -> Variant<bool, SUSP_A>[src]
Get enumerated values variant
pub fn is_suspend(&self) -> bool[src]
Checks if the value of the field is SUSPEND
impl R<bool, WKUP_A>[src]
pub fn variant(&self) -> Variant<bool, WKUP_A>[src]
Get enumerated values variant
pub fn is_wakeup(&self) -> bool[src]
Checks if the value of the field is WAKEUP
impl R<bool, ERR_A>[src]
pub fn variant(&self) -> Variant<bool, ERR_A>[src]
Get enumerated values variant
pub fn is_error(&self) -> bool[src]
Checks if the value of the field is ERROR
impl R<bool, PMAOVR_A>[src]
pub fn variant(&self) -> Variant<bool, PMAOVR_A>[src]
Get enumerated values variant
pub fn is_overrun(&self) -> bool[src]
Checks if the value of the field is OVERRUN
impl R<bool, CTR_A>[src]
pub fn variant(&self) -> Variant<bool, CTR_A>[src]
Get enumerated values variant
pub fn is_completed(&self) -> bool[src]
Checks if the value of the field is COMPLETED
impl R<u32, Reg<u32, _ISTR>>[src]
pub fn ep_id(&self) -> EP_ID_R[src]
Bits 0:3 - Endpoint Identifier
pub fn dir(&self) -> DIR_R[src]
Bit 4 - Direction of transaction
pub fn esof(&self) -> ESOF_R[src]
Bit 8 - Expected start frame
pub fn sof(&self) -> SOF_R[src]
Bit 9 - start of frame
pub fn reset(&self) -> RESET_R[src]
Bit 10 - reset request
pub fn susp(&self) -> SUSP_R[src]
Bit 11 - Suspend mode request
pub fn wkup(&self) -> WKUP_R[src]
Bit 12 - Wakeup
pub fn err(&self) -> ERR_R[src]
Bit 13 - Error
pub fn pmaovr(&self) -> PMAOVR_R[src]
Bit 14 - Packet memory area over / underrun
pub fn ctr(&self) -> CTR_R[src]
Bit 15 - Correct transfer
impl R<bool, LCK_A>[src]
pub fn variant(&self) -> Variant<bool, LCK_A>[src]
Get enumerated values variant
pub fn is_locked(&self) -> bool[src]
Checks if the value of the field is LOCKED
impl R<bool, RXDM_A>[src]
pub fn variant(&self) -> Variant<bool, RXDM_A>[src]
Get enumerated values variant
pub fn is_received(&self) -> bool[src]
Checks if the value of the field is RECEIVED
impl R<bool, RXDP_A>[src]
pub fn variant(&self) -> Variant<bool, RXDP_A>[src]
Get enumerated values variant
pub fn is_received(&self) -> bool[src]
Checks if the value of the field is RECEIVED
impl R<u32, Reg<u32, _FNR>>[src]
pub fn fn_(&self) -> FN_R[src]
Bits 0:10 - Frame number
pub fn lsof(&self) -> LSOF_R[src]
Bits 11:12 - Lost SOF
pub fn lck(&self) -> LCK_R[src]
Bit 13 - Locked
pub fn rxdm(&self) -> RXDM_R[src]
Bit 14 - Receive data - line status
pub fn rxdp(&self) -> RXDP_R[src]
Bit 15 - Receive data + line status
impl R<bool, EF_A>[src]
pub fn variant(&self) -> EF_A[src]
Get enumerated values variant
pub fn is_disabled(&self) -> bool[src]
Checks if the value of the field is DISABLED
pub fn is_enabled(&self) -> bool[src]
Checks if the value of the field is ENABLED
impl R<u32, Reg<u32, _DADDR>>[src]
pub fn add(&self) -> ADD_R[src]
Bits 0:6 - Device address
pub fn ef(&self) -> EF_R[src]
Bit 7 - Enable function
impl R<u32, Reg<u32, _BTABLE>>[src]
impl R<u32, Reg<u32, _CR>>[src]
impl R<u8, WDGTB_A>[src]
pub fn variant(&self) -> WDGTB_A[src]
Get enumerated values variant
pub fn is_div1(&self) -> bool[src]
Checks if the value of the field is DIV1
pub fn is_div2(&self) -> bool[src]
Checks if the value of the field is DIV2
pub fn is_div4(&self) -> bool[src]
Checks if the value of the field is DIV4
pub fn is_div8(&self) -> bool[src]
Checks if the value of the field is DIV8
impl R<u32, Reg<u32, _CFR>>[src]
pub fn w(&self) -> W_R[src]
Bits 0:6 - 7-bit window value
pub fn wdgtb(&self) -> WDGTB_R[src]
Bits 7:8 - Timer base
impl R<bool, EWIF_A>[src]
pub fn variant(&self) -> EWIF_A[src]
Get enumerated values variant
pub fn is_pending(&self) -> bool[src]
Checks if the value of the field is PENDING
pub fn is_finished(&self) -> bool[src]
Checks if the value of the field is FINISHED
impl R<u32, Reg<u32, _SR>>[src]
impl R<u32, Reg<u32, _SR>>[src]
pub fn jcnr(&self) -> JCNR_R[src]
Bit 9 - Injected channel not ready
pub fn rcnr(&self) -> RCNR_R[src]
Bit 8 - Regular channel not ready
pub fn adons(&self) -> ADONS_R[src]
Bit 6 - ADC ON status
pub fn ovr(&self) -> OVR_R[src]
Bit 5 - Overrun
pub fn strt(&self) -> STRT_R[src]
Bit 4 - Regular channel start flag
pub fn jstrt(&self) -> JSTRT_R[src]
Bit 3 - Injected channel start flag
pub fn jeoc(&self) -> JEOC_R[src]
Bit 2 - Injected channel end of conversion
pub fn eoc(&self) -> EOC_R[src]
Bit 1 - Regular channel end of conversion
pub fn awd(&self) -> AWD_R[src]
Bit 0 - Analog watchdog flag
impl R<u32, Reg<u32, _CR1>>[src]
pub fn ovrie(&self) -> OVRIE_R[src]
Bit 26 - Overrun interrupt enable
pub fn res(&self) -> RES_R[src]
Bits 24:25 - Resolution
pub fn awden(&self) -> AWDEN_R[src]
Bit 23 - Analog watchdog enable on regular channels
pub fn jawden(&self) -> JAWDEN_R[src]
Bit 22 - Analog watchdog enable on injected channels
pub fn pdi(&self) -> PDI_R[src]
Bit 17 - Power down during the idle phase
pub fn pdd(&self) -> PDD_R[src]
Bit 16 - Power down during the delay phase
pub fn discnum(&self) -> DISCNUM_R[src]
Bits 13:15 - Discontinuous mode channel count
pub fn jdiscen(&self) -> JDISCEN_R[src]
Bit 12 - Discontinuous mode on injected channels
pub fn discen(&self) -> DISCEN_R[src]
Bit 11 - Discontinuous mode on regular channels
pub fn jauto(&self) -> JAUTO_R[src]
Bit 10 - Automatic injected group conversion
pub fn awdsgl(&self) -> AWDSGL_R[src]
Bit 9 - Enable the watchdog on a single channel in scan mode
pub fn scan(&self) -> SCAN_R[src]
Bit 8 - Scan mode
pub fn jeocie(&self) -> JEOCIE_R[src]
Bit 7 - Interrupt enable for injected channels
pub fn awdie(&self) -> AWDIE_R[src]
Bit 6 - Analog watchdog interrupt enable
pub fn eocie(&self) -> EOCIE_R[src]
Bit 5 - Interrupt enable for EOC
pub fn awdch(&self) -> AWDCH_R[src]
Bits 0:4 - Analog watchdog channel select bits
impl R<u32, Reg<u32, _CR2>>[src]
pub fn swstart(&self) -> SWSTART_R[src]
Bit 30 - Start conversion of regular channels
pub fn exten(&self) -> EXTEN_R[src]
Bits 28:29 - External trigger enable for regular channels
pub fn extsel(&self) -> EXTSEL_R[src]
Bits 24:27 - External event select for regular group
pub fn jswstart(&self) -> JSWSTART_R[src]
Bit 22 - Start conversion of injected channels
pub fn jexten(&self) -> JEXTEN_R[src]
Bits 20:21 - External trigger enable for injected channels
pub fn jextsel(&self) -> JEXTSEL_R[src]
Bits 16:19 - External event select for injected group
pub fn align(&self) -> ALIGN_R[src]
Bit 11 - Data alignment
pub fn eocs(&self) -> EOCS_R[src]
Bit 10 - End of conversion selection
pub fn dds(&self) -> DDS_R[src]
Bit 9 - DMA disable selection
pub fn dma(&self) -> DMA_R[src]
Bit 8 - Direct memory access mode
pub fn dels(&self) -> DELS_R[src]
Bits 4:6 - Delay selection
pub fn adc_cfg(&self) -> ADC_CFG_R[src]
Bit 2 - ADC configuration
pub fn cont(&self) -> CONT_R[src]
Bit 1 - Continuous conversion
pub fn adon(&self) -> ADON_R[src]
Bit 0 - A/D Converter ON / OFF
impl R<u32, Reg<u32, _SMPR1>>[src]
impl R<u32, Reg<u32, _SMPR2>>[src]
impl R<u32, Reg<u32, _SMPR3>>[src]
impl R<u32, Reg<u32, _JOFR1>>[src]
pub fn joffset1(&self) -> JOFFSET1_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _JOFR2>>[src]
pub fn joffset2(&self) -> JOFFSET2_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _JOFR3>>[src]
pub fn joffset3(&self) -> JOFFSET3_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _JOFR4>>[src]
pub fn joffset4(&self) -> JOFFSET4_R[src]
Bits 0:11 - Data offset for injected channel x
impl R<u32, Reg<u32, _HTR>>[src]
impl R<u32, Reg<u32, _LTR>>[src]
impl R<u32, Reg<u32, _SQR1>>[src]
pub fn l(&self) -> L_R[src]
Bits 20:23 - Regular channel sequence length
pub fn sq28(&self) -> SQ28_R[src]
Bits 15:19 - 28th conversion in regular sequence
pub fn sq27(&self) -> SQ27_R[src]
Bits 10:14 - 27th conversion in regular sequence
pub fn sq26(&self) -> SQ26_R[src]
Bits 5:9 - 26th conversion in regular sequence
pub fn sq25(&self) -> SQ25_R[src]
Bits 0:4 - 25th conversion in regular sequence
impl R<u32, Reg<u32, _SQR2>>[src]
pub fn sq24(&self) -> SQ24_R[src]
Bits 25:29 - 24th conversion in regular sequence
pub fn sq23(&self) -> SQ23_R[src]
Bits 20:24 - 23rd conversion in regular sequence
pub fn sq22(&self) -> SQ22_R[src]
Bits 15:19 - 22nd conversion in regular sequence
pub fn sq21(&self) -> SQ21_R[src]
Bits 10:14 - 21st conversion in regular sequence
pub fn sq20(&self) -> SQ20_R[src]
Bits 5:9 - 20th conversion in regular sequence
pub fn sq19(&self) -> SQ19_R[src]
Bits 0:4 - 19th conversion in regular sequence
impl R<u32, Reg<u32, _SQR3>>[src]
pub fn sq18(&self) -> SQ18_R[src]
Bits 25:29 - 18th conversion in regular sequence
pub fn sq17(&self) -> SQ17_R[src]
Bits 20:24 - 17th conversion in regular sequence
pub fn sq16(&self) -> SQ16_R[src]
Bits 15:19 - 16th conversion in regular sequence
pub fn sq15(&self) -> SQ15_R[src]
Bits 10:14 - 15th conversion in regular sequence
pub fn sq14(&self) -> SQ14_R[src]
Bits 5:9 - 14th conversion in regular sequence
pub fn sq13(&self) -> SQ13_R[src]
Bits 0:4 - 13th conversion in regular sequence
impl R<u32, Reg<u32, _SQR4>>[src]
pub fn sq12(&self) -> SQ12_R[src]
Bits 25:29 - 12th conversion in regular sequence
pub fn sq11(&self) -> SQ11_R[src]
Bits 20:24 - 11th conversion in regular sequence
pub fn sq10(&self) -> SQ10_R[src]
Bits 15:19 - 10th conversion in regular sequence
pub fn sq9(&self) -> SQ9_R[src]
Bits 10:14 - 9th conversion in regular sequence
pub fn sq8(&self) -> SQ8_R[src]
Bits 5:9 - 8th conversion in regular sequence
pub fn sq7(&self) -> SQ7_R[src]
Bits 0:4 - 7th conversion in regular sequence
impl R<u32, Reg<u32, _SQR5>>[src]
pub fn sq6(&self) -> SQ6_R[src]
Bits 25:29 - 6th conversion in regular sequence
pub fn sq5(&self) -> SQ5_R[src]
Bits 20:24 - 5th conversion in regular sequence
pub fn sq4(&self) -> SQ4_R[src]
Bits 15:19 - 4th conversion in regular sequence
pub fn sq3(&self) -> SQ3_R[src]
Bits 10:14 - 3rd conversion in regular sequence
pub fn sq2(&self) -> SQ2_R[src]
Bits 5:9 - 2nd conversion in regular sequence
pub fn sq1(&self) -> SQ1_R[src]
Bits 0:4 - 1st conversion in regular sequence
impl R<u32, Reg<u32, _JSQR>>[src]
pub fn jl(&self) -> JL_R[src]
Bits 20:21 - Injected sequence length
pub fn jsq4(&self) -> JSQ4_R[src]
Bits 15:19 - 4th conversion in injected sequence
pub fn jsq3(&self) -> JSQ3_R[src]
Bits 10:14 - 3rd conversion in injected sequence
pub fn jsq2(&self) -> JSQ2_R[src]
Bits 5:9 - 2nd conversion in injected sequence
pub fn jsq1(&self) -> JSQ1_R[src]
Bits 0:4 - 1st conversion in injected sequence
impl R<u32, Reg<u32, _JDR1>>[src]
impl R<u32, Reg<u32, _JDR2>>[src]
impl R<u32, Reg<u32, _JDR3>>[src]
impl R<u32, Reg<u32, _JDR4>>[src]
impl R<u32, Reg<u32, _DR>>[src]
pub fn regular_data(&self) -> REGULARDATA_R[src]
Bits 0:15 - Regular data
impl R<u32, Reg<u32, _SMPR0>>[src]
impl R<u32, Reg<u32, _CSR>>[src]
pub fn awd1(&self) -> AWD1_R[src]
Bit 0 - Analog watchdog flag of the ADC
pub fn eoc1(&self) -> EOC1_R[src]
Bit 1 - End of conversion of the ADC
pub fn jeoc1(&self) -> JEOC1_R[src]
Bit 2 - Injected channel end of conversion of the ADC
pub fn jstrt1(&self) -> JSTRT1_R[src]
Bit 3 - Injected channel Start flag of the ADC
pub fn strt1(&self) -> STRT1_R[src]
Bit 4 - Regular channel Start flag of the ADC
pub fn ovr1(&self) -> OVR1_R[src]
Bit 5 - Overrun flag of the ADC
pub fn adons1(&self) -> ADONS1_R[src]
Bit 6 - ADON Status of ADC1
impl R<u32, Reg<u32, _CCR>>[src]
pub fn adcpre(&self) -> ADCPRE_R[src]
Bits 16:17 - ADC prescaler
pub fn tsvrefe(&self) -> TSVREFE_R[src]
Bit 23 - Temperature sensor and VREFINT enable
impl R<u32, Reg<u32, _IDCODE>>[src]
pub fn dev_id(&self) -> DEV_ID_R[src]
Bits 0:11 - Device identifier
pub fn rev_id(&self) -> REV_ID_R[src]
Bits 16:31 - Revision identifie
impl R<u32, Reg<u32, _CR>>[src]
pub fn dbg_sleep(&self) -> DBG_SLEEP_R[src]
Bit 0 - Debug Sleep mode
pub fn dbg_stop(&self) -> DBG_STOP_R[src]
Bit 1 - Debug Stop mode
pub fn dbg_standby(&self) -> DBG_STANDBY_R[src]
Bit 2 - Debug Standby mode
pub fn trace_ioen(&self) -> TRACE_IOEN_R[src]
Bit 5 - Trace pin assignment control
pub fn trace_mode(&self) -> TRACE_MODE_R[src]
Bits 6:7 - Trace pin assignment control
impl R<u32, Reg<u32, _APB1_FZ>>[src]
pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R[src]
Bit 0 - TIM2 counter stopped when core is halted
pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R[src]
Bit 1 - TIM3 counter stopped when core is halted
pub fn dbg_tim4_stop(&self) -> DBG_TIM4_STOP_R[src]
Bit 2 - TIM4 counter stopped when core is halted
pub fn dbg_tim5_stop(&self) -> DBG_TIM5_STOP_R[src]
Bit 3 - TIM5 counter stopped when core is halted
pub fn dbg_tim6_stop(&self) -> DBG_TIM6_STOP_R[src]
Bit 4 - TIM6 counter stopped when core is halted
pub fn dbg_tim7_stop(&self) -> DBG_TIM7_STOP_R[src]
Bit 5 - TIM7 counter stopped when core is halted
pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R[src]
Bit 10 - Debug RTC stopped when core is halted
pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R[src]
Bit 11 - Debug window watchdog stopped when core is halted
pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R[src]
Bit 12 - Debug independent watchdog stopped when core is halted
pub fn dbg_i2c1_smbus_timeout(&self) -> DBG_I2C1_SMBUS_TIMEOUT_R[src]
Bit 21 - SMBUS timeout mode stopped when core is halted
pub fn dbg_i2c2_smbus_timeout(&self) -> DBG_I2C2_SMBUS_TIMEOUT_R[src]
Bit 22 - SMBUS timeout mode stopped when core is halted
impl R<u32, Reg<u32, _APB2_FZ>>[src]
pub fn dbg_tim9_stop(&self) -> DBG_TIM9_STOP_R[src]
Bit 2 - TIM counter stopped when core is halted
pub fn dbg_tim10_stop(&self) -> DBG_TIM10_STOP_R[src]
Bit 3 - TIM counter stopped when core is halted
pub fn dbg_tim11_stop(&self) -> DBG_TIM11_STOP_R[src]
Bit 4 - TIM counter stopped when core is halted
impl R<u32, Reg<u32, _ACTRL>>[src]
pub fn disfold(&self) -> DISFOLD_R[src]
Bit 2 - DISFOLD
pub fn fpexcodis(&self) -> FPEXCODIS_R[src]
Bit 10 - FPEXCODIS
pub fn disramode(&self) -> DISRAMODE_R[src]
Bit 11 - DISRAMODE
pub fn disitmatbflush(&self) -> DISITMATBFLUSH_R[src]
Bit 12 - DISITMATBFLUSH
impl R<u32, Reg<u32, _STIR>>[src]
impl R<u32, Reg<u32, _CTRL>>[src]
pub fn enable(&self) -> ENABLE_R[src]
Bit 0 - Counter enable
pub fn tickint(&self) -> TICKINT_R[src]
Bit 1 - SysTick exception request enable
pub fn clksource(&self) -> CLKSOURCE_R[src]
Bit 2 - Clock source selection
pub fn countflag(&self) -> COUNTFLAG_R[src]
Bit 16 - COUNTFLAG
impl R<u32, Reg<u32, _LOAD_>>[src]
impl R<u32, Reg<u32, _VAL>>[src]
impl R<u32, Reg<u32, _CALIB>>[src]
Trait Implementations
Auto Trait Implementations
impl<U, T> Send for R<U, T> where
T: Send,
U: Send,
T: Send,
U: Send,
impl<U, T> Sync for R<U, T> where
T: Sync,
U: Sync,
T: Sync,
U: Sync,
impl<U, T> Unpin for R<U, T> where
T: Unpin,
U: Unpin,
T: Unpin,
U: Unpin,
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized, [src]
T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized, [src]
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized, [src]
T: ?Sized,
fn borrow_mut(&mut self) -> &mut T[src]
impl<T> From<T> for T[src]
impl<T, U> Into<U> for T where
U: From<T>, [src]
U: From<T>,
impl<T> Same<T> for T
type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>, [src]
U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>[src]
impl<T, U> TryInto<U> for T where
U: TryFrom<T>, [src]
U: TryFrom<T>,