Struct stm32l0x1_hal::power::Power

pub struct Power<VDD, VCORE, RTC> { /* private fields */ }

The constrained Power peripheral

Implementations

impl<VDD, RTC> Power<VDD, VCoreRange2, RTC>

pub fn into_vdd_range<NEWVDD>(self) -> Power<VDD, VCoreRange2, RTC>

Change the VDD range (logically - not physically)

impl<VDD, RTC> Power<VDD, VCoreRange3, RTC>

pub fn into_vdd_range<NEWVDD>(self) -> Power<VDD, VCoreRange3, RTC>

Change the VDD range (logically - not physically)

impl<VCORE, RTC> Power<VddHigh, VCORE, RTC>

pub fn into_vcore_range<NEWRANGE>(self) -> Power<VddHigh, NEWRANGE, RTC>where
    NEWRANGE: Vos,

Change the power peripheral’s VCoreRange type state.

This does not take effect until enact() is called

impl<RTC> Power<VddLow, VCoreRange2, RTC>

pub fn into_vcore_range(self) -> Power<VddLow, VCoreRange3, RTC>

Change the power peripheral’s VCoreRange type state.

This does not take effect until enact() is called

impl<RTC> Power<VddLow, VCoreRange3, RTC>

pub fn into_vcore_range(self) -> Power<VddLow, VCoreRange2, RTC>

Change the power peripheral’s VCoreRange type state.

This does not take effect until enact() is called

impl<VDD, VCORE, RTC> Power<VDD, VCORE, RTC>where
    VCORE: Vos,

pub fn dbp_context<F>(&mut self, op: F)where
    F: FnMut(),

Provide a context for changing LSE and RTC settings.

7.3.20: Note: The LSEON, LSEBYP, RTCSEL, LSEDRV and RTCEN bits in the RCC control and status register (RCC_CSR) are in the RTC domain. As these bits are write protected after reset, the DBP bit in the Power control register (PWR_CR) has to be set to be able to modify them. Refer to Section 6.1.2: RTC and RTC backup registers for further information.

pub unsafe fn enact(&mut self, apb1: &mut APB1)

Enact the current Power type states

This function is unsafe because it does not validate the requested setting against the currently configured clock. Rcc::freeze takes care of this for you.

pub fn read_vcore_range(&self) -> VCoreRange

Read the current VCoreRange value from the register

impl<VDD, VCORE> Power<VDD, VCORE, RtcEn>where
    VCORE: Vos,

pub fn disable_rtc(self, apb1: &mut APB1) -> Power<VDD, VCORE, RtcDis>

Disable the RTC, changing the type state of self

impl<VDD, VCORE> Power<VDD, VCORE, RtcDis>where
    VCORE: Vos,

pub fn enable_rtc(self, cr: &mut CR, apb1: &mut APB1) -> Power<VDD, VCORE, RtcEn>

Enable the RTC, changing the type state of self

Trait Implementations

impl Constrain<Power<VddHigh, VCoreRange2, RtcDis>> for PWR

fn constrain(self) -> Power<VddHigh, VCoreRange2, RtcDis>

Constrains the peripheral to play nicely with the other abstractions

impl Constrain<Power<VddLow, VCoreRange2, RtcDis>> for PWR

fn constrain(self) -> Power<VddLow, VCoreRange2, RtcDis>

Constrains the peripheral to play nicely with the other abstractions