Module stm32h7xx_hal::stm32::bdma::isr [−][src]
DMA interrupt status register
Enums
GIF1_A | Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
HTIF1_A | Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TCIF1_A | Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TEIF1_A | Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
Type Definitions
GIF1_R | Reader of field |
GIF2_A | Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
GIF2_R | Reader of field |
GIF3_A | Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
GIF3_R | Reader of field |
GIF4_A | Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
GIF4_R | Reader of field |
GIF5_A | Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
GIF5_R | Reader of field |
GIF6_A | Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
GIF6_R | Reader of field |
GIF7_A | Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
GIF7_R | Reader of field |
GIF8_A | Channel x global interrupt flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
GIF8_R | Reader of field |
HTIF1_R | Reader of field |
HTIF2_A | Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
HTIF2_R | Reader of field |
HTIF3_A | Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
HTIF3_R | Reader of field |
HTIF4_A | Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
HTIF4_R | Reader of field |
HTIF5_A | Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
HTIF5_R | Reader of field |
HTIF6_A | Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
HTIF6_R | Reader of field |
HTIF7_A | Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
HTIF7_R | Reader of field |
HTIF8_A | Channel x half transfer flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
HTIF8_R | Reader of field |
R | Reader of register ISR |
TCIF1_R | Reader of field |
TCIF2_A | Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TCIF2_R | Reader of field |
TCIF3_A | Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TCIF3_R | Reader of field |
TCIF4_A | Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TCIF4_R | Reader of field |
TCIF5_A | Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TCIF5_R | Reader of field |
TCIF6_A | Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TCIF6_R | Reader of field |
TCIF7_A | Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TCIF7_R | Reader of field |
TCIF8_A | Channel x transfer complete flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TCIF8_R | Reader of field |
TEIF1_R | Reader of field |
TEIF2_A | Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TEIF2_R | Reader of field |
TEIF3_A | Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TEIF3_R | Reader of field |
TEIF4_A | Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TEIF4_R | Reader of field |
TEIF5_A | Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TEIF5_R | Reader of field |
TEIF6_A | Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TEIF6_R | Reader of field |
TEIF7_A | Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TEIF7_R | Reader of field |
TEIF8_A | Channel x transfer error flag (x = 1..8) This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. |
TEIF8_R | Reader of field |