Struct stm32h7x3::mdma::mdma_c9cr::W
[−]
[src]
pub struct W { /* fields omitted */ }
Value to write to the register
Methods
impl W
[src]
fn reset_value() -> W
[src]
Reset value of the register
unsafe fn bits(&mut self, bits: u32) -> &mut Self
[src]
Writes raw bits to the register
fn en(&mut self) -> _ENW
[src]
Bit 0 - channel enable
fn teie(&mut self) -> _TEIEW
[src]
Bit 1 - Transfer error interrupt enable This bit is set and cleared by software.
fn ctcie(&mut self) -> _CTCIEW
[src]
Bit 2 - Channel Transfer Complete interrupt enable This bit is set and cleared by software.
fn brtie(&mut self) -> _BRTIEW
[src]
Bit 3 - Block Repeat transfer interrupt enable This bit is set and cleared by software.
fn btie(&mut self) -> _BTIEW
[src]
Bit 4 - Block Transfer interrupt enable This bit is set and cleared by software.
fn tcie(&mut self) -> _TCIEW
[src]
Bit 5 - buffer Transfer Complete interrupt enable This bit is set and cleared by software.
fn pl(&mut self) -> _PLW
[src]
Bits 6:7 - Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0.
fn bex(&mut self) -> _BEXW
[src]
Bit 12 - byte Endianness exchange
fn hex(&mut self) -> _HEXW
[src]
Bit 13 - Half word Endianes exchange
fn wex(&mut self) -> _WEXW
[src]
Bit 14 - Word Endianness exchange
fn swrq(&mut self) -> _SWRQW
[src]
Bit 16 - SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access).