Struct stm32h7x3::mdma::mdma_c3isr::R
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pub struct R { /* fields omitted */ }
Value read from the register
Methods
impl R
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fn bits(&self) -> u32
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Value of the register as raw bits
fn teif3(&self) -> TEIF3R
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Bit 0 - Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
fn ctcif3(&self) -> CTCIF3R
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Bit 1 - Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
fn brtif3(&self) -> BRTIF3R
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Bit 2 - Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
fn btif3(&self) -> BTIF3R
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Bit 3 - Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
fn tcif3(&self) -> TCIF3R
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Bit 4 - channel x buffer transfer complete
fn crqa3(&self) -> CRQA3R
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Bit 16 - channel x request active flag