Struct stm32h7::stm32h743::sdmmc1::cmdr::W

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pub struct W(_);

Expand description

Register CMDR writer

Implementations

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impl W

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pub fn cmdindex(&mut self) -> CMDINDEX_W<'_, 0>

Bits 0:5 - Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message.

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pub fn cmdtrans(&mut self) -> CMDTRANS_W<'_, 6>

Bit 6 - The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent.

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pub fn cmdstop(&mut self) -> CMDSTOP_W<'_, 7>

Bit 7 - The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent.

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pub fn waitresp(&mut self) -> WAITRESP_W<'_, 8>

Bits 8:9 - Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response.

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pub fn waitint(&mut self) -> WAITINT_W<'_, 10>

Bit 10 - CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode.

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pub fn waitpend(&mut self) -> WAITPEND_W<'_, 11>

Bit 11 - CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card.

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pub fn cpsmen(&mut self) -> CPSMEN_W<'_, 12>

Bit 12 - Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0.

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pub fn dthold(&mut self) -> DTHOLD_W<'_, 13>

Bit 13 - Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state.

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pub fn bootmode(&mut self) -> BOOTMODE_W<'_, 14>

Bit 14 - Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)

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pub fn booten(&mut self) -> BOOTEN_W<'_, 15>

Bit 15 - Enable boot mode procedure.

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pub fn cmdsuspend(&mut self) -> CMDSUSPEND_W<'_, 16>

Bit 16 - The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1.

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