pub struct W(_);
Expand description
Register SR
writer
Implementations
sourceimpl W
impl W
sourcepub fn ceis(&mut self) -> CEIS_W<'_, 5>
pub fn ceis(&mut self) -> CEIS_W<'_, 5>
Bit 5 - Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1.
sourcepub fn seis(&mut self) -> SEIS_W<'_, 6>
pub fn seis(&mut self) -> SEIS_W<'_, 6>
Bit 6 - Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101…01) An interrupt is pending if IE = 1 in the RNG_CR register.
Methods from Deref<Target = W<SR_SPEC>>
Trait Implementations
Auto Trait Implementations
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more