Struct stm32h7::stm32h743::quadspi::ccr::W

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pub struct W(_);

Expand description

Register CCR writer

Implementations

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impl W

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pub fn instruction(&mut self) -> INSTRUCTION_W<'_, 0>

Bits 0:7 - Instruction Instruction to be send to the external SPI device. This field can be written only when BUSY = 0.

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pub fn imode(&mut self) -> IMODE_W<'_, 8>

Bits 8:9 - Instruction mode This field defines the instruction phase mode of operation: This field can be written only when BUSY = 0.

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pub fn admode(&mut self) -> ADMODE_W<'_, 10>

Bits 10:11 - Address mode This field defines the address phase mode of operation: This field can be written only when BUSY = 0.

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pub fn adsize(&mut self) -> ADSIZE_W<'_, 12>

Bits 12:13 - Address size This bit defines address size: This field can be written only when BUSY = 0.

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pub fn abmode(&mut self) -> ABMODE_W<'_, 14>

Bits 14:15 - Alternate bytes mode This field defines the alternate-bytes phase mode of operation: This field can be written only when BUSY = 0.

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pub fn absize(&mut self) -> ABSIZE_W<'_, 16>

Bits 16:17 - Alternate bytes size This bit defines alternate bytes size: This field can be written only when BUSY = 0.

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pub fn dcyc(&mut self) -> DCYC_W<'_, 18>

Bits 18:22 - Number of dummy cycles This field defines the duration of the dummy phase. In both SDR and DDR modes, it specifies a number of CLK cycles (0-31). This field can be written only when BUSY = 0.

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pub fn dmode(&mut self) -> DMODE_W<'_, 24>

Bits 24:25 - Data mode This field defines the data phases mode of operation: This field also determines the dummy phase mode of operation. This field can be written only when BUSY = 0.

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pub fn fmode(&mut self) -> FMODE_W<'_, 26>

Bits 26:27 - Functional mode This field defines the QUADSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE value. This field can be written only when BUSY = 0.

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pub fn sioo(&mut self) -> SIOO_W<'_, 28>

Bit 28 - Send instruction only once mode See Section15.3.11: Sending the instruction only once on page13. This bit has no effect when IMODE = 00. This field can be written only when BUSY = 0.

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pub fn dhhc(&mut self) -> DHHC_W<'_, 30>

Bit 30 - DDR hold Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode: This feature is only active in DDR mode. This field can be written only when BUSY = 0.

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pub fn ddrm(&mut self) -> DDRM_W<'_, 31>

Bit 31 - Double data rate mode This bit sets the DDR mode for the address, alternate byte and data phase: This field can be written only when BUSY = 0.

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