[−][src]Struct stm32h7::stm32h743v::i2c1::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub cr1: CR1,
    pub cr2: CR2,
    pub oar1: OAR1,
    pub oar2: OAR2,
    pub timingr: TIMINGR,
    pub timeoutr: TIMEOUTR,
    pub isr: ISR,
    pub icr: ICR,
    pub pecr: PECR,
    pub rxdr: RXDR,
    pub txdr: TXDR,
}

Register block

Fields

cr1: CR1

0x00 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

cr2: CR2

0x04 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

oar1: OAR1

0x08 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

oar2: OAR2

0x0c - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

timingr: TIMINGR

0x10 - Access: No wait states

timeoutr: TIMEOUTR

0x14 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

isr: ISR

0x18 - Access: No wait states

icr: ICR

0x1c - Access: No wait states

pecr: PECR

0x20 - Access: No wait states

rxdr: RXDR

0x24 - Access: No wait states

txdr: TXDR

0x28 - Access: No wait states

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