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#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
    pub cr1: CR1,
    #[doc = "0x04 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
    pub cr2: CR2,
    #[doc = "0x08 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
    pub oar1: OAR1,
    #[doc = "0x0c - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
    pub oar2: OAR2,
    #[doc = "0x10 - Access: No wait states"]
    pub timingr: TIMINGR,
    #[doc = "0x14 - Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
    pub timeoutr: TIMEOUTR,
    #[doc = "0x18 - Access: No wait states"]
    pub isr: ISR,
    #[doc = "0x1c - Access: No wait states"]
    pub icr: ICR,
    #[doc = "0x20 - Access: No wait states"]
    pub pecr: PECR,
    #[doc = "0x24 - Access: No wait states"]
    pub rxdr: RXDR,
    #[doc = "0x28 - Access: No wait states"]
    pub txdr: TXDR,
}
#[doc = "Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
pub struct CR1 {
    register: vcell::VolatileCell<u32>,
}
#[doc = "Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
pub mod cr1;
#[doc = "Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
pub struct CR2 {
    register: vcell::VolatileCell<u32>,
}
#[doc = "Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
pub mod cr2;
#[doc = "Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
pub struct OAR1 {
    register: vcell::VolatileCell<u32>,
}
#[doc = "Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
pub mod oar1;
#[doc = "Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
pub struct OAR2 {
    register: vcell::VolatileCell<u32>,
}
#[doc = "Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
pub mod oar2;
#[doc = "Access: No wait states"]
pub struct TIMINGR {
    register: vcell::VolatileCell<u32>,
}
#[doc = "Access: No wait states"]
pub mod timingr;
#[doc = "Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
pub struct TIMEOUTR {
    register: vcell::VolatileCell<u32>,
}
#[doc = "Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK."]
pub mod timeoutr;
#[doc = "Access: No wait states"]
pub struct ISR {
    register: vcell::VolatileCell<u32>,
}
#[doc = "Access: No wait states"]
pub mod isr;
#[doc = "Access: No wait states"]
pub struct ICR {
    register: vcell::VolatileCell<u32>,
}
#[doc = "Access: No wait states"]
pub mod icr;
#[doc = "Access: No wait states"]
pub struct PECR {
    register: vcell::VolatileCell<u32>,
}
#[doc = "Access: No wait states"]
pub mod pecr;
#[doc = "Access: No wait states"]
pub struct RXDR {
    register: vcell::VolatileCell<u32>,
}
#[doc = "Access: No wait states"]
pub mod rxdr;
#[doc = "Access: No wait states"]
pub struct TXDR {
    register: vcell::VolatileCell<u32>,
}
#[doc = "Access: No wait states"]
pub mod txdr;