Type Alias R

pub type R = R<CFG2rs>;

Register CFG2 reader

Aliased Type

pub struct R { /* private fields */ }

Implementations

impl R

pub fn mssi(&self) -> MSSI_R

Bits 0:3 - Master SS Idleness Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted additionally between active edge of SS opening a session and the beginning of the first data frame of the session in Master mode when SSOE is enabled. … Note: This feature is not supported in TI mode. To include the delay, the SPI must be disabled and re-enabled between sessions.

pub fn midi(&self) -> MIDI_R

Bits 4:7 - master Inter-Data Idleness Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between two consecutive data frames in Master mode. … Note: This feature is not supported in TI mode.

pub fn rdiom(&self) -> RDIOM_R

Bit 13 - RDY signal input/output management Note: When DSIZE at the SPI_CFG1 register is configured shorter than 8-bit, the RDIOM bit has to be kept at zero.

pub fn rdiop(&self) -> RDIOP_R

Bit 14 - RDY signal input/output polarity

pub fn ioswp(&self) -> IOSWP_R

Bit 15 - swap functionality of MISO and MOSI pins When this bit is set, the function of MISO and MOSI pins alternate functions are inverted. Original MISO pin becomes MOSI and original MOSI pin becomes MISO. Note: This bit can be also used in PCM and I2S modes to swap SDO and SDI pins.

pub fn comm(&self) -> COMM_R

Bits 17:18 - SPI Communication Mode

pub fn sp(&self) -> SP_R

Bits 19:21 - serial protocol others: reserved, must not be used

pub fn master(&self) -> MASTER_R

Bit 22 - SPI Master

pub fn lsbfrst(&self) -> LSBFRST_R

Bit 23 - data frame format Note: This bit can be also used in PCM and I2S modes.

pub fn cpha(&self) -> CPHA_R

Bit 24 - clock phase

pub fn cpol(&self) -> CPOL_R

Bit 25 - clock polarity

pub fn ssm(&self) -> SSM_R

Bit 26 - software management of SS signal input When master uses hardware SS output (SSM=0 and SSOE=1) the SS signal input is forced to not active state internally to prevent master mode fault error.

pub fn ssiop(&self) -> SSIOP_R

Bit 28 - SS input/output polarity

pub fn ssoe(&self) -> SSOE_R

Bit 29 - SS output enable This bit is taken into account in Master mode only

pub fn ssom(&self) -> SSOM_R

Bit 30 - SS output management in Master mode This bit is taken into account in Master mode when SSOE is enabled. It allows the SS output to be configured between two consecutive data transfers.

pub fn afcntr(&self) -> AFCNTR_R

Bit 31 - alternate function GPIOs control This bit is taken into account when SPE=0 only When SPI has to be disabled temporary for a specific configuration reason (e.g. CRC reset, CPHA or HDDIR change) setting this bit prevents any glitches on the associated outputs configured at alternate function mode by keeping them forced at state corresponding the current SPI configuration. Note: This bit can be also used in PCM and I2S modes. Note: The bit AFCNTR must not be set to 1, when the block is in slave mode.

Trait Implementations

impl Debug for R

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.