Type Alias R

pub type R = R<CR1rs>;

Register CR1 reader

Aliased Type

pub struct R { /* private fields */ }

Implementations

impl R

pub fn cen(&self) -> CEN_R

Bit 0 - Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.

pub fn udis(&self) -> UDIS_R

Bit 1 - Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.

pub fn urs(&self) -> URS_R

Bit 2 - Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller

pub fn opm(&self) -> OPM_R

Bit 3 - One-pulse mode

pub fn arpe(&self) -> ARPE_R

Bit 7 - Auto-reload preload enable

pub fn ckd(&self) -> CKD_R

Bits 8:9 - Clock division This bit-field indicates the division ratio between the timer clock (tim_ker_ck) frequency and sampling clock used by the digital filters (tim_etr_in, tim_tix),

pub fn uifremap(&self) -> UIFREMAP_R

Bit 11 - UIF status bit remapping

pub fn dithen(&self) -> DITHEN_R

Bit 12 - Dithering Enable Note: The DITHEN bit can only be modified when CEN bit is reset.

Trait Implementations

impl Debug for R

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.