stm32h5::stm32h563::tim1

Struct RegisterBlock

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#[repr(C)]
pub struct RegisterBlock { /* private fields */ }
Expand description

Register block

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impl RegisterBlock

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pub const fn cr1(&self) -> &CR1

0x00 - TIM1 control register 1

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pub const fn cr2(&self) -> &CR2

0x04 - TIM1 control register 2

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pub const fn smcr(&self) -> &SMCR

0x08 - TIM1 slave mode control register

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pub const fn dier(&self) -> &DIER

0x0c - TIM1 DMA/interrupt enable register

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pub const fn sr(&self) -> &SR

0x10 - TIM1 status register

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pub const fn egr(&self) -> &EGR

0x14 - TIM1 event generation register

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pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT

0x18 - TIM1 capture/compare mode register 1 [alternate]

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pub const fn ccmr1_input(&self) -> &CCMR1_INPUT

0x18 - TIM1 capture/compare mode register 1 [alternate]

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pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT

0x1c - TIM1 capture/compare mode register 2 [alternate]

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pub const fn ccmr2_input(&self) -> &CCMR2_INPUT

0x1c - TIM1 capture/compare mode register 2 [alternate]

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pub const fn ccer(&self) -> &CCER

0x20 - TIM1 capture/compare enable register

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pub const fn cnt(&self) -> &CNT

0x24 - TIM1 counter

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pub const fn psc(&self) -> &PSC

0x28 - TIM1 prescaler

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pub const fn arr(&self) -> &ARR

0x2c - TIM1 auto-reload register

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pub const fn rcr(&self) -> &RCR

0x30 - TIM1 repetition counter register

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pub const fn ccr1(&self) -> &CCR1

0x34 - TIM1 capture/compare register 1

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pub const fn ccr2(&self) -> &CCR2

0x38 - TIM1 capture/compare register 2

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pub const fn ccr3(&self) -> &CCR3

0x3c - TIM1 capture/compare register 3

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pub const fn ccr4(&self) -> &CCR4

0x40 - TIM1 capture/compare register 4

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pub const fn bdtr(&self) -> &BDTR

0x44 - TIM1 break and dead-time register

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pub const fn ccr5(&self) -> &CCR5

0x48 - TIM1 capture/compare register 5

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pub const fn ccr6(&self) -> &CCR6

0x4c - TIM1 capture/compare register 6

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pub const fn ccmr3(&self) -> &CCMR3

0x50 - TIM1 capture/compare mode register 3

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pub const fn dtr2(&self) -> &DTR2

0x54 - TIM1 timer deadtime register 2

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pub const fn ecr(&self) -> &ECR

0x58 - TIM1 timer encoder control register

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pub const fn tisel(&self) -> &TISEL

0x5c - TIM1 timer input selection register

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pub const fn af1(&self) -> &AF1

0x60 - TIM1 alternate function option register 1

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pub const fn af2(&self) -> &AF2

0x64 - TIM1 alternate function register 2

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pub const fn dcr(&self) -> &DCR

0x3dc - TIM1 DMA control register

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pub const fn dmar(&self) -> &DMAR

0x3e0 - TIM1 DMA address for full transfer

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