Struct SEC_FMC 

pub struct SEC_FMC { /* private fields */ }

Flexible memory controller

Implementations

impl SEC_FMC

pub const PTR: *const RegisterBlock = {0x57000400 as *const stm32h573::fmc::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn bcr1(&self) -> &BCR1

0x00 - SRAM/NOR-Flash chip-select control register for bank 1

pub fn btr1(&self) -> &BTR1

0x04 - SRAM/NOR-Flash chip-select timing register for bank 1

pub fn bcr2(&self) -> &BCR2

0x08 - SRAM/NOR-Flash chip-select control register for bank 2

pub fn btr2(&self) -> &BTR2

0x0c - SRAM/NOR-Flash chip-select timing register for bank 2

pub fn bcr3(&self) -> &BCR3

0x10 - SRAM/NOR-Flash chip-select control register for bank 3

pub fn btr3(&self) -> &BTR3

0x14 - SRAM/NOR-Flash chip-select timing register for bank 3

pub fn bcr4(&self) -> &BCR4

0x18 - SRAM/NOR-Flash chip-select control register for bank 4

pub fn btr4(&self) -> &BTR4

0x1c - SRAM/NOR-Flash chip-select timing register for bank 4

pub fn pcscntr(&self) -> &PCSCNTR

0x20 - PSRAM chip select counter register

pub fn pcr(&self) -> &PCR

0x80 - NAND Flash control registers

pub fn sr(&self) -> &SR

0x84 - FIFO status and interrupt register

pub fn pmem(&self) -> &PMEM

0x88 - Common memory space timing register

pub fn patt(&self) -> &PATT

0x8c - Attribute memory space timing register

pub fn eccr(&self) -> &ECCR

0x94 - ECC result registers

pub fn bwtr1(&self) -> &BWTR1

0x104 - SRAM/NOR-Flash write timing registers 1

pub fn bwtr2(&self) -> &BWTR2

0x10c - SRAM/NOR-Flash write timing registers 2

pub fn bwtr3(&self) -> &BWTR3

0x114 - SRAM/NOR-Flash write timing registers 3

pub fn bwtr4(&self) -> &BWTR4

0x11c - SRAM/NOR-Flash write timing registers 4

pub fn sdcr1(&self) -> &SDCR1

0x140 - SDRAM control registers 1

pub fn sdcr2(&self) -> &SDCR2

0x144 - SDRAM control registers 2

pub fn sdtr1(&self) -> &SDTR1

0x148 - SDRAM timing registers 1

pub fn sdtr2(&self) -> &SDTR2

0x14c - SDRAM timing registers 2

pub fn sdcmr(&self) -> &SDCMR

0x150 - SDRAM Command Mode register

pub fn sdrtr(&self) -> &SDRTR

0x154 - SDRAM refresh timer register

pub fn sdsr(&self) -> &SDSR

0x158 - SDRAM status register

Trait Implementations

impl Debug for SEC_FMC

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for SEC_FMC

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for SEC_FMC