pub enum TXISR {
NotEmpty = 0,
Empty = 1,
}Expand description
Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to ‘1’ by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0.
Value on reset: 0
Variants§
NotEmpty = 0
0: The TXDR register is not empty
Empty = 1
1: The TXDR register is empty and the data to be transmitted must be written in the TXDR register
Trait Implementations§
impl Copy for TXISR
impl Eq for TXISR
impl StructuralPartialEq for TXISR
Auto Trait Implementations§
impl Freeze for TXISR
impl RefUnwindSafe for TXISR
impl Send for TXISR
impl Sync for TXISR
impl Unpin for TXISR
impl UnwindSafe for TXISR
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more