pub enum LCKK {
NotActive = 0,
Active = 1,
}Expand description
Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0]
- LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the LOCK. After the first LOCK sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset.
Value on reset: 0
Variants§
NotActive = 0
0: Port configuration lock key not active
Active = 1
1: Port configuration lock key active
Trait Implementations§
impl Copy for LCKK
impl Eq for LCKK
impl StructuralPartialEq for LCKK
Auto Trait Implementations§
impl Freeze for LCKK
impl RefUnwindSafe for LCKK
impl Send for LCKK
impl Sync for LCKK
impl Unpin for LCKK
impl UnwindSafe for LCKK
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more