pub enum IM32 {
Masked = 0,
Unmasked = 1,
}Expand description
CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded.
Value on reset: 1
Variants§
Trait Implementations§
impl Copy for IM32
impl Eq for IM32
impl StructuralPartialEq for IM32
Auto Trait Implementations§
impl Freeze for IM32
impl RefUnwindSafe for IM32
impl Send for IM32
impl Sync for IM32
impl Unpin for IM32
impl UnwindSafe for IM32
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more