pub enum IM0 {
Masked = 0,
Unmasked = 1,
}Expand description
CPU wakeup with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded.
Value on reset: 0
Variants§
Trait Implementations§
impl Copy for IM0
impl Eq for IM0
impl StructuralPartialEq for IM0
Auto Trait Implementations§
impl Freeze for IM0
impl RefUnwindSafe for IM0
impl Send for IM0
impl Sync for IM0
impl Unpin for IM0
impl UnwindSafe for IM0
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more