pub enum EM0 {
Masked = 0,
Unmasked = 1,
}Expand description
CPU wakeup with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded.
Value on reset: 0
Variants§
Trait Implementations§
impl Copy for EM0
impl Eq for EM0
impl StructuralPartialEq for EM0
Auto Trait Implementations§
impl Freeze for EM0
impl RefUnwindSafe for EM0
impl Send for EM0
impl Sync for EM0
impl Unpin for EM0
impl UnwindSafe for EM0
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more