Struct stm32g4::stm32g474::fdcan::RegisterBlock [−][src]
Register block
Fields
crel: CREL
0x00 - FDCAN Core Release Register
endn: ENDN
0x04 - FDCAN Core Release Register
dbtp: DBTP
0x0c - This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
test: TEST
0x10 - Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
rwd: RWD
0x14 - The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.
cccr: CCCR
0x18 - For details about setting and resetting of single bits see Software initialization.
nbtp: NBTP
0x1c - FDCAN_NBTP
tscc: TSCC
0x20 - FDCAN Timestamp Counter Configuration Register
tscv: TSCV
0x24 - FDCAN Timestamp Counter Value Register
tocc: TOCC
0x28 - FDCAN Timeout Counter Configuration Register
tocv: TOCV
0x2c - FDCAN Timeout Counter Value Register
ecr: ECR
0x40 - FDCAN Error Counter Register
psr: PSR
0x44 - FDCAN Protocol Status Register
tdcr: TDCR
0x48 - FDCAN Transmitter Delay Compensation Register
ir: IR
0x50 - The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.
ie: IE
0x54 - The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line.
ils: ILS
0x58 - The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].
ile: ILE
0x5c - Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.
rxgfc: RXGFC
0x80 - Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.
xidam: XIDAM
0x84 - FDCAN Extended ID and Mask Register
hpms: HPMS
0x88 - This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.
rxf0s: RXF0S
0x90 - FDCAN Rx FIFO 0 Status Register
rxf0a: RXF0A
0x94 - CAN Rx FIFO 0 Acknowledge Register
rxf1s: RXF1S
0x98 - FDCAN Rx FIFO 1 Status Register
rxf1a: RXF1A
0x9c - FDCAN Rx FIFO 1 Acknowledge Register
txbc: TXBC
0xc0 - FDCAN Tx Buffer Configuration Register
txfqs: TXFQS
0xc4 - The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).
txbrp: TXBRP
0xc8 - FDCAN Tx Buffer Request Pending Register
txbar: TXBAR
0xcc - FDCAN Tx Buffer Add Request Register
txbcr: TXBCR
0xd0 - FDCAN Tx Buffer Cancellation Request Register
txbto: TXBTO
0xd4 - FDCAN Tx Buffer Transmission Occurred Register
txbcf: TXBCF
0xd8 - FDCAN Tx Buffer Cancellation Finished Register
txbtie: TXBTIE
0xdc - FDCAN Tx Buffer Transmission Interrupt Enable Register
txbcie: TXBCIE
0xe0 - FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
txefs: TXEFS
0xe4 - FDCAN Tx Event FIFO Status Register
txefa: TXEFA
0xe8 - FDCAN Tx Event FIFO Acknowledge Register
ckdiv: CKDIV
0x100 - FDCAN CFG clock divider register
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