Type Definition stm32g4::stm32g441::rcc::pllcfgr::R

type R = R<u32, PLLCFGR>;

Reader of register PLLCFGR

Implementations

impl R

pub fn pllpdiv(&self) -> PLLPDIV_R

Bits 27:31 - Main PLL division factor for PLLSAI2CLK

pub fn pllr(&self) -> PLLR_R

Bits 25:26 - Main PLL division factor for PLLCLK (system clock)

pub fn pllren(&self) -> PLLREN_R

Bit 24 - Main PLL PLLCLK output enable

pub fn pllq(&self) -> PLLQ_R

Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)

pub fn pllqen(&self) -> PLLQEN_R

Bit 20 - Main PLL PLLUSB1CLK output enable

pub fn pllp(&self) -> PLLP_R

Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)

pub fn pllpen(&self) -> PLLPEN_R

Bit 16 - Main PLL PLLSAI3CLK output enable

pub fn plln(&self) -> PLLN_R

Bits 8:14 - Main PLL multiplication factor for VCO

pub fn pllm(&self) -> PLLM_R

Bits 4:7 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock

pub fn pllsrc(&self) -> PLLSRC_R

Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source