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#[doc = "Reader of register PLLCFGR"] pub type R = crate::R<u32, super::PLLCFGR>; #[doc = "Writer for register PLLCFGR"] pub type W = crate::W<u32, super::PLLCFGR>; #[doc = "Register PLLCFGR `reset()`'s with value 0x1000"] impl crate::ResetValue for super::PLLCFGR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0x1000 } } #[doc = "Reader of field `PLLPDIV`"] pub type PLLPDIV_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PLLPDIV`"] pub struct PLLPDIV_W<'a> { w: &'a mut W, } impl<'a> PLLPDIV_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x1f << 27)) | (((value as u32) & 0x1f) << 27); self.w } } #[doc = "Reader of field `PLLR`"] pub type PLLR_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PLLR`"] pub struct PLLR_W<'a> { w: &'a mut W, } impl<'a> PLLR_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 25)) | (((value as u32) & 0x03) << 25); self.w } } #[doc = "Reader of field `PLLREN`"] pub type PLLREN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PLLREN`"] pub struct PLLREN_W<'a> { w: &'a mut W, } impl<'a> PLLREN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); self.w } } #[doc = "Reader of field `PLLQ`"] pub type PLLQ_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PLLQ`"] pub struct PLLQ_W<'a> { w: &'a mut W, } impl<'a> PLLQ_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 21)) | (((value as u32) & 0x03) << 21); self.w } } #[doc = "Reader of field `PLLQEN`"] pub type PLLQEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PLLQEN`"] pub struct PLLQEN_W<'a> { w: &'a mut W, } impl<'a> PLLQEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20); self.w } } #[doc = "Reader of field `PLLP`"] pub type PLLP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PLLP`"] pub struct PLLP_W<'a> { w: &'a mut W, } impl<'a> PLLP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); self.w } } #[doc = "Reader of field `PLLPEN`"] pub type PLLPEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PLLPEN`"] pub struct PLLPEN_W<'a> { w: &'a mut W, } impl<'a> PLLPEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); self.w } } #[doc = "Reader of field `PLLN`"] pub type PLLN_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PLLN`"] pub struct PLLN_W<'a> { w: &'a mut W, } impl<'a> PLLN_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8); self.w } } #[doc = "Reader of field `PLLM`"] pub type PLLM_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PLLM`"] pub struct PLLM_W<'a> { w: &'a mut W, } impl<'a> PLLM_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 4)) | (((value as u32) & 0x0f) << 4); self.w } } #[doc = "Reader of field `PLLSRC`"] pub type PLLSRC_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PLLSRC`"] pub struct PLLSRC_W<'a> { w: &'a mut W, } impl<'a> PLLSRC_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03); self.w } } impl R { #[doc = "Bits 27:31 - Main PLL division factor for PLLSAI2CLK"] #[inline(always)] pub fn pllpdiv(&self) -> PLLPDIV_R { PLLPDIV_R::new(((self.bits >> 27) & 0x1f) as u8) } #[doc = "Bits 25:26 - Main PLL division factor for PLLCLK (system clock)"] #[inline(always)] pub fn pllr(&self) -> PLLR_R { PLLR_R::new(((self.bits >> 25) & 0x03) as u8) } #[doc = "Bit 24 - Main PLL PLLCLK output enable"] #[inline(always)] pub fn pllren(&self) -> PLLREN_R { PLLREN_R::new(((self.bits >> 24) & 0x01) != 0) } #[doc = "Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)"] #[inline(always)] pub fn pllq(&self) -> PLLQ_R { PLLQ_R::new(((self.bits >> 21) & 0x03) as u8) } #[doc = "Bit 20 - Main PLL PLLUSB1CLK output enable"] #[inline(always)] pub fn pllqen(&self) -> PLLQEN_R { PLLQEN_R::new(((self.bits >> 20) & 0x01) != 0) } #[doc = "Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)"] #[inline(always)] pub fn pllp(&self) -> PLLP_R { PLLP_R::new(((self.bits >> 17) & 0x01) != 0) } #[doc = "Bit 16 - Main PLL PLLSAI3CLK output enable"] #[inline(always)] pub fn pllpen(&self) -> PLLPEN_R { PLLPEN_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bits 8:14 - Main PLL multiplication factor for VCO"] #[inline(always)] pub fn plln(&self) -> PLLN_R { PLLN_R::new(((self.bits >> 8) & 0x7f) as u8) } #[doc = "Bits 4:7 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock"] #[inline(always)] pub fn pllm(&self) -> PLLM_R { PLLM_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source"] #[inline(always)] pub fn pllsrc(&self) -> PLLSRC_R { PLLSRC_R::new((self.bits & 0x03) as u8) } } impl W { #[doc = "Bits 27:31 - Main PLL division factor for PLLSAI2CLK"] #[inline(always)] pub fn pllpdiv(&mut self) -> PLLPDIV_W { PLLPDIV_W { w: self } } #[doc = "Bits 25:26 - Main PLL division factor for PLLCLK (system clock)"] #[inline(always)] pub fn pllr(&mut self) -> PLLR_W { PLLR_W { w: self } } #[doc = "Bit 24 - Main PLL PLLCLK output enable"] #[inline(always)] pub fn pllren(&mut self) -> PLLREN_W { PLLREN_W { w: self } } #[doc = "Bits 21:22 - Main PLL division factor for PLLUSB1CLK(48 MHz clock)"] #[inline(always)] pub fn pllq(&mut self) -> PLLQ_W { PLLQ_W { w: self } } #[doc = "Bit 20 - Main PLL PLLUSB1CLK output enable"] #[inline(always)] pub fn pllqen(&mut self) -> PLLQEN_W { PLLQEN_W { w: self } } #[doc = "Bit 17 - Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)"] #[inline(always)] pub fn pllp(&mut self) -> PLLP_W { PLLP_W { w: self } } #[doc = "Bit 16 - Main PLL PLLSAI3CLK output enable"] #[inline(always)] pub fn pllpen(&mut self) -> PLLPEN_W { PLLPEN_W { w: self } } #[doc = "Bits 8:14 - Main PLL multiplication factor for VCO"] #[inline(always)] pub fn plln(&mut self) -> PLLN_W { PLLN_W { w: self } } #[doc = "Bits 4:7 - Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock"] #[inline(always)] pub fn pllm(&mut self) -> PLLM_W { PLLM_W { w: self } } #[doc = "Bits 0:1 - Main PLL, PLLSAI1 and PLLSAI2 entry clock source"] #[inline(always)] pub fn pllsrc(&mut self) -> PLLSRC_W { PLLSRC_W { w: self } } }