Type Definition stm32g4::stm32g441::crs::cr::W

type W = W<u32, CR>;

Writer for register CR

Implementations

impl W

pub fn syncokie(&mut self) -> SYNCOKIE_W<'_>

Bit 0 - SYNC event OK interrupt enable

pub fn syncwarnie(&mut self) -> SYNCWARNIE_W<'_>

Bit 1 - SYNC warning interrupt enable

pub fn errie(&mut self) -> ERRIE_W<'_>

Bit 2 - Synchronization or trimming error interrupt enable

pub fn esyncie(&mut self) -> ESYNCIE_W<'_>

Bit 3 - Expected SYNC interrupt enable

pub fn cen(&mut self) -> CEN_W<'_>

Bit 5 - Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified.

pub fn autotrimen(&mut self) -> AUTOTRIMEN_W<'_>

Bit 6 - Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details.

pub fn swsync(&mut self) -> SWSYNC_W<'_>

Bit 7 - Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware.

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 8:14 - HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only.