Type Definition stm32g4::stm32g431::adc1::cfgr::W [−][src]
type W = W<u32, CFGR>;
Writer for register CFGR
Implementations
impl W
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pub fn jqdis(&mut self) -> JQDIS_W<'_>
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Bit 31 - Injected Queue disable
pub fn awd1ch(&mut self) -> AWD1CH_W<'_>
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Bits 26:30 - Analog watchdog 1 channel selection
pub fn jauto(&mut self) -> JAUTO_W<'_>
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Bit 25 - Automatic injected group conversion
pub fn jawd1en(&mut self) -> JAWD1EN_W<'_>
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Bit 24 - Analog watchdog 1 enable on injected channels
pub fn awd1en(&mut self) -> AWD1EN_W<'_>
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Bit 23 - Analog watchdog 1 enable on regular channels
pub fn awd1sgl(&mut self) -> AWD1SGL_W<'_>
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Bit 22 - Enable the watchdog 1 on a single channel or on all channels
pub fn jqm(&mut self) -> JQM_W<'_>
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Bit 21 - JSQR queue mode
pub fn jdiscen(&mut self) -> JDISCEN_W<'_>
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Bit 20 - Discontinuous mode on injected channels
pub fn discnum(&mut self) -> DISCNUM_W<'_>
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Bits 17:19 - Discontinuous mode channel count
pub fn discen(&mut self) -> DISCEN_W<'_>
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Bit 16 - Discontinuous mode for regular channels
pub fn align(&mut self) -> ALIGN_W<'_>
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Bit 15 - Data alignment
pub fn autdly(&mut self) -> AUTDLY_W<'_>
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Bit 14 - Delayed conversion mode
pub fn cont(&mut self) -> CONT_W<'_>
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Bit 13 - Single / continuous conversion mode for regular conversions
pub fn ovrmod(&mut self) -> OVRMOD_W<'_>
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Bit 12 - Overrun mode
pub fn exten(&mut self) -> EXTEN_W<'_>
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Bits 10:11 - External trigger enable and polarity selection for regular channels
pub fn extsel(&mut self) -> EXTSEL_W<'_>
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Bits 5:9 - External trigger selection for regular group
pub fn res(&mut self) -> RES_W<'_>
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Bits 3:4 - Data resolution
pub fn dmacfg(&mut self) -> DMACFG_W<'_>
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Bit 1 - Direct memory access configuration
pub fn dmaen(&mut self) -> DMAEN_W<'_>
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Bit 0 - Direct memory access enable