Type Alias MMS_W

pub type MMS_W<'a, REG> = FieldWriter<'a, REG, 3, MMS>;

Field MMS writer - Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Aliased Type

struct MMS_W<'a, REG> { /* private fields */ }

Implementations

impl<'a, REG> MMS_W<'a, REG>

where REG: Writable + RegisterSpec, REG::Ux: From<u8>,

pub fn reset(self) -> &'a mut W<REG>

Use UG bit from TIMx_EGR register

pub fn enable(self) -> &'a mut W<REG>

Use CNT bit from TIMx_CEN register

pub fn update(self) -> &'a mut W<REG>

Use the update event