Struct stm32g0::stm32g0x1::rcc::pllsyscfgr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn pllsrc(&self) -> PLLSRCR

Bits 0:1 - PLL input clock source

pub fn pllm(&self) -> PLLMR

Bits 4:6 - Division factor M of the PLL input clock divider

pub fn plln(&self) -> PLLNR

Bits 8:14 - PLL frequency multiplication factor N

pub fn pllpen(&self) -> PLLPENR

Bit 16 - PLLPCLK clock output enable

pub fn pllp(&self) -> PLLPR

Bits 17:21 - PLL VCO division factor P for PLLPCLK clock output

pub fn pllqen(&self) -> PLLQENR

Bit 24 - PLLQCLK clock output enable

pub fn pllq(&self) -> PLLQR

Bits 25:27 - PLL VCO division factor Q for PLLQCLK clock output

pub fn pllren(&self) -> PLLRENR

Bit 28 - PLLRCLK clock output enable

pub fn pllr(&self) -> PLLRR

Bits 29:31 - PLL VCO division factor R for PLLRCLK clock output