pub struct W(_);
Expand description
Register CCER
writer
Implementations
sourceimpl W
impl W
sourcepub fn cc1e(&mut self) -> CC1E_W<'_, 0>
pub fn cc1e(&mut self) -> CC1E_W<'_, 0>
Bit 0 - Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details.
sourcepub fn cc1p(&mut self) -> CC1P_W<'_, 1>
pub fn cc1p(&mut self) -> CC1P_W<'_, 1>
Bit 1 - Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.
sourcepub fn cc1ne(&mut self) -> CC1NE_W<'_, 2>
pub fn cc1ne(&mut self) -> CC1NE_W<'_, 2>
Bit 2 - Capture/Compare 1 complementary output enable
sourcepub fn cc1np(&mut self) -> CC1NP_W<'_, 3>
pub fn cc1np(&mut self) -> CC1NP_W<'_, 3>
Bit 3 - Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.
sourcepub fn cc2e(&mut self) -> CC2E_W<'_, 4>
pub fn cc2e(&mut self) -> CC2E_W<'_, 4>
Bit 4 - Capture/Compare 2 output enable Refer to CC1E description
sourcepub fn cc2p(&mut self) -> CC2P_W<'_, 5>
pub fn cc2p(&mut self) -> CC2P_W<'_, 5>
Bit 5 - Capture/Compare 2 output polarity Refer to CC1P description
Methods from Deref<Target = W<CCER_SPEC>>
Trait Implementations
Auto Trait Implementations
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more