pub struct W(_);
Expand description
Register BDTR
writer
Implementations
sourceimpl W
impl W
sourcepub fn dtg(&mut self) -> DTG_W<'_, 0>
pub fn dtg(&mut self) -> DTG_W<'_, 0>
Bits 0:7 - Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
sourcepub fn lock(&mut self) -> LOCK_W<'_, 8>
pub fn lock(&mut self) -> LOCK_W<'_, 8>
Bits 8:9 - Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
sourcepub fn ossi(&mut self) -> OSSI_W<'_, 10>
pub fn ossi(&mut self) -> OSSI_W<'_, 10>
Bit 10 - Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
sourcepub fn ossr(&mut self) -> OSSR_W<'_, 11>
pub fn ossr(&mut self) -> OSSR_W<'_, 11>
Bit 11 - Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
sourcepub fn bke(&mut self) -> BKE_W<'_, 12>
pub fn bke(&mut self) -> BKE_W<'_, 12>
Bit 12 - Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
sourcepub fn bkp(&mut self) -> BKP_W<'_, 13>
pub fn bkp(&mut self) -> BKP_W<'_, 13>
Bit 13 - Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
sourcepub fn aoe(&mut self) -> AOE_W<'_, 14>
pub fn aoe(&mut self) -> AOE_W<'_, 14>
Bit 14 - Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
sourcepub fn moe(&mut self) -> MOE_W<'_, 15>
pub fn moe(&mut self) -> MOE_W<'_, 15>
Bit 15 - Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818).
sourcepub fn bkf(&mut self) -> BKF_W<'_, 16>
pub fn bkf(&mut self) -> BKF_W<'_, 16>
Bits 16:19 - Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
sourcepub fn bkdsrm(&mut self) -> BKDSRM_W<'_, 26>
pub fn bkdsrm(&mut self) -> BKDSRM_W<'_, 26>
Bit 26 - Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
sourcepub fn bkbid(&mut self) -> BKBID_W<'_, 28>
pub fn bkbid(&mut self) -> BKBID_W<'_, 28>
Bit 28 - Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Methods from Deref<Target = W<BDTR_SPEC>>
Trait Implementations
Auto Trait Implementations
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sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
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