pub type OC1M_R = FieldReader<u8, OC1M_A>;
Expand description
Field OC1M
reader - Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. The OC1M[3]
bit is not contiguous, located in bit 16.
Implementations
sourceimpl OC1M_R
impl OC1M_R
sourcepub fn is_active_on_match(&self) -> bool
pub fn is_active_on_match(&self) -> bool
Checks if the value of the field is ActiveOnMatch
sourcepub fn is_inactive_on_match(&self) -> bool
pub fn is_inactive_on_match(&self) -> bool
Checks if the value of the field is InactiveOnMatch
sourcepub fn is_force_inactive(&self) -> bool
pub fn is_force_inactive(&self) -> bool
Checks if the value of the field is ForceInactive
sourcepub fn is_force_active(&self) -> bool
pub fn is_force_active(&self) -> bool
Checks if the value of the field is ForceActive
sourcepub fn is_pwm_mode1(&self) -> bool
pub fn is_pwm_mode1(&self) -> bool
Checks if the value of the field is PwmMode1
sourcepub fn is_pwm_mode2(&self) -> bool
pub fn is_pwm_mode2(&self) -> bool
Checks if the value of the field is PwmMode2