Struct stm32g0::stm32g0c1::dac::cr::R

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pub struct R(_);

Expand description

Register CR reader

Implementations

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impl R

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pub fn en1(&self) -> EN1_R

Bit 0 - DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.

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pub fn ten1(&self) -> TEN1_R

Bit 1 - DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle.

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pub fn tsel1(&self) -> TSEL1_R

Bits 2:5 - DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 … Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

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pub fn wave1(&self) -> WAVE1_R

Bits 6:7 - DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 1x: Triangle wave generation enabled Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

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pub fn mamp1(&self) -> MAMP1_R

Bits 8:11 - DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

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pub fn dmaen1(&self) -> DMAEN1_R

Bit 12 - DAC channel1 DMA enable This bit is set and cleared by software.

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pub fn dmaudrie1(&self) -> DMAUDRIE1_R

Bit 13 - DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.

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pub fn cen1(&self) -> CEN1_R

Bit 14 - DAC channel1 calibration enable This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

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pub fn en2(&self) -> EN2_R

Bit 16 - DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. Note: These bits are available only on dual-channel DACs. Refer to implementation.

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pub fn ten2(&self) -> TEN2_R

Bit 17 - DAC channel2 trigger enable This bit is set and cleared by software to enable/disable DAC channel2 trigger Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the DAC_DOR2 register takes only one dac_pclk clock cycle. These bits are available only on dual-channel DACs. Refer to implementation.

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pub fn tsel2(&self) -> TSEL2_R

Bits 18:21 - DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 … Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). These bits are available only on dual-channel DACs. Refer to implementation.

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pub fn wave2(&self) -> WAVE2_R

Bits 22:23 - DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) These bits are available only on dual-channel DACs. Refer to implementation.

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pub fn mamp2(&self) -> MAMP2_R

Bits 24:27 - DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Note: These bits are available only on dual-channel DACs. Refer to implementation.

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pub fn dmaen2(&self) -> DMAEN2_R

Bit 28 - DAC channel2 DMA enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation.

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pub fn dmaudrie2(&self) -> DMAUDRIE2_R

Bit 29 - DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation.

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pub fn cen2(&self) -> CEN2_R

Bit 30 - DAC channel2 calibration enable This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. Note: This bit is available only on dual-channel DACs. Refer to implementation.