Struct stm32g0::stm32g0c1::wwdg::wwdg_cr::R [−][src]
pub struct R(_);
Expand description
Register WWDG_CR
reader
Implementations
Bits 0:6 - 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared).
Methods from Deref<Target = R<WWDG_CR_SPEC>>
Trait Implementations
Performs the conversion.