Struct stm32g0::stm32g0c1::tim2::ccmr1_output::R [−][src]
pub struct R(_);
Expand description
Register CCMR1_Output
reader
Implementations
Bits 8:9 - Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 4:6 - Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.
Bit 3 - Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
Methods from Deref<Target = R<CCMR1_OUTPUT_SPEC>>
Trait Implementations
Performs the conversion.