Struct stm32g0::stm32g0b0::usart1::cr3::W

pub struct W(_);

Register CR3 writer

Implementations

impl W

pub fn eie(&mut self) -> EIE_W<'_>

Bit 0 - Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register).

pub fn iren(&mut self) -> IREN_W<'_>

Bit 1 - IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .

pub fn irlp(&mut self) -> IRLP_W<'_>

Bit 2 - IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to .

pub fn hdsel(&mut self) -> HDSEL_W<'_>

Bit 3 - Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UEÂ =Â 0).

pub fn nack(&mut self) -> NACK_W<'_>

Bit 4 - Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .

pub fn scen(&mut self) -> SCEN_W<'_>

Bit 5 - Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .

pub fn dmar(&mut self) -> DMAR_W<'_>

Bit 6 - DMA enable receiver This bit is set/reset by software

pub fn dmat(&mut self) -> DMAT_W<'_>

Bit 7 - DMA enable transmitter This bit is set/reset by software

pub fn rtse(&mut self) -> RTSE_W<'_>

Bit 8 - RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .

pub fn ctse(&mut self) -> CTSE_W<'_>

Bit 9 - CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .

pub fn ctsie(&mut self) -> CTSIE_W<'_>

Bit 10 - CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to .

pub fn onebit(&mut self) -> ONEBIT_W<'_>

Bit 11 - One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0).

pub fn ovrdis(&mut self) -> OVRDIS_W<'_>

Bit 12 - Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data

pub fn ddre(&mut self) -> DDRE_W<'_>

Bit 13 - DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.

pub fn dem(&mut self) -> DEM_W<'_>

Bit 14 - Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. .

pub fn dep(&mut self) -> DEP_W<'_>

Bit 15 - Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to .

pub fn scarcnt(&mut self) -> SCARCNT_W<'_>

Bits 17:19 - Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to .

pub fn wus(&mut self) -> WUS_W<'_>

Bits 20:21 - Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.

pub fn wufie(&mut self) -> WUFIE_W<'_>

Bit 22 - Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835.

pub fn txftie(&mut self) -> TXFTIE_W<'_>

Bit 23 - TXFIFO threshold interrupt enable This bit is set and cleared by software.

pub fn tcbgtie(&mut self) -> TCBGTIE_W<'_>

Bit 24 - Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to .

pub fn rxftcfg(&mut self) -> RXFTCFG_W<'_>

Bits 25:27 - Receive FIFO threshold configuration Remaining combinations: Reserved

pub fn rxftie(&mut self) -> RXFTIE_W<'_>

Bit 28 - RXFIFO threshold interrupt enable This bit is set and cleared by software.

pub fn txftcfg(&mut self) -> TXFTCFG_W<'_>

Bits 29:31 - TXFIFO threshold configuration Remaining combinations: Reserved

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CR3_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<CR3_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CR3_SPEC>> for W

fn from(writer: W<CR3_SPEC>) -> Self

Performs the conversion.