Struct stm32g0::stm32g0b0::tim1::cr2::R

pub struct R(_);

Register CR2 reader

Implementations

impl R

pub fn ccpc(&self) -> CCPC_R

Bit 0 - Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.

pub fn ccus(&self) -> CCUS_R

Bit 2 - Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.

pub fn ccds(&self) -> CCDS_R

Bit 3 - Capture/compare DMA selection

pub fn mms(&self) -> MMS_R

Bits 4:6 - Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

pub fn ti1s(&self) -> TI1S_R

Bit 7 - TI1 selection

pub fn ois1(&self) -> OIS1_R

Bit 8 - Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

pub fn ois1n(&self) -> OIS1N_R

Bit 9 - Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

pub fn ois2(&self) -> OIS2_R

Bit 10 - Output Idle state 2 (OC2 output) Refer to OIS1 bit

pub fn ois2n(&self) -> OIS2N_R

Bit 11 - Output Idle state 2 (OC2N output) Refer to OIS1N bit

pub fn ois3(&self) -> OIS3_R

Bit 12 - Output Idle state 3 (OC3 output) Refer to OIS1 bit

pub fn ois3n(&self) -> OIS3N_R

Bit 13 - Output Idle state 3 (OC3N output) Refer to OIS1N bit

pub fn ois4(&self) -> OIS4_R

Bit 14 - Output Idle state 4 (OC4 output) Refer to OIS1 bit

pub fn ois5(&self) -> OIS5_R

Bit 16 - Output Idle state 5 (OC5 output) Refer to OIS1 bit

pub fn ois6(&self) -> OIS6_R

Bit 18 - Output Idle state 6 (OC6 output) Refer to OIS1 bit

pub fn mms2(&self) -> MMS2_R

Bits 20:23 - Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Methods from Deref<Target = R<CR2_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CR2_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CR2_SPEC>> for R

fn from(reader: R<CR2_SPEC>) -> Self

Performs the conversion.