Struct stm32g0::stm32g0b0::tim1::bdtr::LOCK_W

pub struct LOCK_W<'a> { /* fields omitted */ }

Field LOCK writer - Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.

Implementations

impl<'a> LOCK_W<'a>

pub fn variant(self, variant: LOCK_A) -> &'a mut W

Writes variant to the field

pub fn b_0x0(self) -> &'a mut W

LOCK OFF - No bit is write protected.

pub fn b_0x1(self) -> &'a mut W

LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written.

pub fn b_0x2(self) -> &'a mut W

LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.

pub fn b_0x3(self) -> &'a mut W

LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.

pub fn bits(self, value: u8) -> &'a mut W

Writes raw bits to the field