Struct stm32g0::stm32g081::adc::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 24 fields
pub isr: Reg<ISR_SPEC>,
pub ier: Reg<IER_SPEC>,
pub cr: Reg<CR_SPEC>,
pub cfgr1: Reg<CFGR1_SPEC>,
pub cfgr2: Reg<CFGR2_SPEC>,
pub smpr: Reg<SMPR_SPEC>,
pub awd1tr: Reg<AWD1TR_SPEC>,
pub awd2tr: Reg<AWD2TR_SPEC>,
pub awd3tr: Reg<AWD3TR_SPEC>,
pub dr: Reg<DR_SPEC>,
pub awd2cr: Reg<AWD2CR_SPEC>,
pub awd3cr: Reg<AWD3CR_SPEC>,
pub calfact: Reg<CALFACT_SPEC>,
pub ccr: Reg<CCR_SPEC>,
pub hwcfgr6: Reg<HWCFGR6_SPEC>,
pub hwcfgr5: Reg<HWCFGR5_SPEC>,
pub hwcfgr4: Reg<HWCFGR4_SPEC>,
pub hwcfgr3: Reg<HWCFGR3_SPEC>,
pub hwcfgr2: Reg<HWCFGR2_SPEC>,
pub hwcfgr1: Reg<HWCFGR1_SPEC>,
pub hwcfgr0: Reg<HWCFGR0_SPEC>,
pub verr: Reg<VERR_SPEC>,
pub ipidr: Reg<IPIDR_SPEC>,
pub sidr: Reg<SIDR_SPEC>,
// some fields omitted
}
Expand description
Register block
Fields
isr: Reg<ISR_SPEC>
0x00 - ADC interrupt and status register
ier: Reg<IER_SPEC>
0x04 - ADC interrupt enable register
cr: Reg<CR_SPEC>
0x08 - ADC control register
cfgr1: Reg<CFGR1_SPEC>
0x0c - ADC configuration register 1
cfgr2: Reg<CFGR2_SPEC>
0x10 - ADC configuration register 2
smpr: Reg<SMPR_SPEC>
0x14 - ADC sampling time register
awd1tr: Reg<AWD1TR_SPEC>
0x20 - watchdog threshold register
awd2tr: Reg<AWD2TR_SPEC>
0x24 - watchdog threshold register
awd3tr: Reg<AWD3TR_SPEC>
0x2c - watchdog threshold register
dr: Reg<DR_SPEC>
0x40 - ADC group regular conversion data register
awd2cr: Reg<AWD2CR_SPEC>
0xa0 - ADC analog watchdog 2 configuration register
awd3cr: Reg<AWD3CR_SPEC>
0xa4 - ADC analog watchdog 3 configuration register
calfact: Reg<CALFACT_SPEC>
0xb4 - ADC calibration factors register
ccr: Reg<CCR_SPEC>
0x308 - ADC common control register
hwcfgr6: Reg<HWCFGR6_SPEC>
0x3d8 - Hardware Configuration Register
hwcfgr5: Reg<HWCFGR5_SPEC>
0x3dc - Hardware Configuration Register
hwcfgr4: Reg<HWCFGR4_SPEC>
0x3e0 - Hardware Configuration Register
hwcfgr3: Reg<HWCFGR3_SPEC>
0x3e4 - Hardware Configuration Register
hwcfgr2: Reg<HWCFGR2_SPEC>
0x3e8 - Hardware Configuration Register
hwcfgr1: Reg<HWCFGR1_SPEC>
0x3ec - Hardware Configuration Register
hwcfgr0: Reg<HWCFGR0_SPEC>
0x3f0 - Hardware Configuration Register
verr: Reg<VERR_SPEC>
0x3f4 - EXTI IP Version register
ipidr: Reg<IPIDR_SPEC>
0x3f8 - EXTI Identification register
sidr: Reg<SIDR_SPEC>
0x3fc - EXTI Size ID register
Implementations
0x28 - channel selection register CHSELRMOD = 1 in ADC_CFGR1
0x28 - channel selection register