Struct stm32g0::stm32g070::tim15::cr2::R [−][src]
pub struct R(_);
Expand description
Register CR2
reader
Implementations
Bit 0 - Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
Bit 2 - Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
Bits 4:6 - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
Bit 8 - Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
Bit 9 - Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).