Module stm32g0::stm32g070::tim15::cr2 [−][src]
Expand description
control register 2
Structs
Field CCDS reader - Capture/compare DMA selection
Field CCDS writer - Capture/compare DMA selection
Field CCPC reader - Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
Field CCPC writer - Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
Field CCUS reader - Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
Field CCUS writer - Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
control register 2
Field MMS reader - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
Field MMS writer - Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
Field OIS1N reader - Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
Field OIS1N writer - Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
Field OIS1 reader - Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
Field OIS1 writer - Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
Field OIS2 reader - Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register).
Field OIS2 writer - Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register).
Register CR2 reader
Field TI1S reader - TI1 selection
Field TI1S writer - TI1 selection
Register CR2 writer
Enums
Capture/compare DMA selection
Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output.
Capture/compare control update selection Note: This bit acts only on channels that have a complementary output.
Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
Output Idle state 1 (OC1N output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
Output idle state 2 (OC2 output) Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register).
TI1 selection