Struct stm32g0::stm32g041::syscfg::cfgr2::R [−][src]
pub struct R(_);
Expand description
Register CFGR2
reader
Implementations
Bit 0 - Cortex-M0+ LOCKUP bit enable bit
Bit 1 - SRAM parity lock bit
Bit 2 - PVD lock enable bit
Bit 3 - ECC error lock bit
Bit 8 - SRAM parity error flag
Bit 16 - PA1_CDEN
Bit 17 - PA3_CDEN
Bit 18 - PA5_CDEN
Bit 19 - PA6_CDEN
Bit 20 - PA13_CDEN
Bit 21 - PB0_CDEN
Bit 22 - PB1_CDEN
Bit 23 - PB2_CDEN
Methods from Deref<Target = R<CFGR2_SPEC>>
Trait Implementations
Performs the conversion.