Struct stm32g0::stm32g081::dac::RegisterBlock[−][src]

#[repr(C)]pub struct RegisterBlock {
    pub dac_cr: DAC_CR,
    pub dac_swtrgr: DAC_SWTRGR,
    pub dac_dhr12r1: DAC_DHR12R1,
    pub dac_dhr12l1: DAC_DHR12L1,
    pub dac_dhr8r1: DAC_DHR8R1,
    pub dac_dhr12r2: DAC_DHR12R2,
    pub dac_dhr12l2: DAC_DHR12L2,
    pub dac_dhr8r2: DAC_DHR8R2,
    pub dac_dhr12rd: DAC_DHR12RD,
    pub dac_dhr12ld: DAC_DHR12LD,
    pub dac_dhr8rd: DAC_DHR8RD,
    pub dac_dor1: DAC_DOR1,
    pub dac_dor2: DAC_DOR2,
    pub dac_sr: DAC_SR,
    pub dac_ccr: DAC_CCR,
    pub dac_mcr: DAC_MCR,
    pub dac_shsr1: DAC_SHSR1,
    pub dac_shsr2: DAC_SHSR2,
    pub dac_shhr: DAC_SHHR,
    pub dac_shrr: DAC_SHRR,
    pub ip_hwcfgr0: IP_HWCFGR0,
    pub verr: VERR,
    pub ipidr: IPIDR,
    pub sidr: SIDR,
    // some fields omitted
}

Register block

Fields

dac_cr: DAC_CR

0x00 - DAC control register

dac_swtrgr: DAC_SWTRGR

0x04 - DAC software trigger register

dac_dhr12r1: DAC_DHR12R1

0x08 - DAC channel1 12-bit right-aligned data holding register

dac_dhr12l1: DAC_DHR12L1

0x0c - DAC channel1 12-bit left aligned data holding register

dac_dhr8r1: DAC_DHR8R1

0x10 - DAC channel1 8-bit right aligned data holding register

dac_dhr12r2: DAC_DHR12R2

0x14 - DAC channel2 12-bit right aligned data holding register

dac_dhr12l2: DAC_DHR12L2

0x18 - DAC channel2 12-bit left aligned data holding register

dac_dhr8r2: DAC_DHR8R2

0x1c - DAC channel2 8-bit right-aligned data holding register

dac_dhr12rd: DAC_DHR12RD

0x20 - Dual DAC 12-bit right-aligned data holding register

dac_dhr12ld: DAC_DHR12LD

0x24 - DUAL DAC 12-bit left aligned data holding register

dac_dhr8rd: DAC_DHR8RD

0x28 - DUAL DAC 8-bit right aligned data holding register

dac_dor1: DAC_DOR1

0x2c - DAC channel1 data output register

dac_dor2: DAC_DOR2

0x30 - DAC channel2 data output register

dac_sr: DAC_SR

0x34 - DAC status register

dac_ccr: DAC_CCR

0x38 - DAC calibration control register

dac_mcr: DAC_MCR

0x3c - DAC mode control register

dac_shsr1: DAC_SHSR1

0x40 - DAC Sample and Hold sample time register 1

dac_shsr2: DAC_SHSR2

0x44 - DAC Sample and Hold sample time register 2

dac_shhr: DAC_SHHR

0x48 - DAC Sample and Hold hold time register

dac_shrr: DAC_SHRR

0x4c - DAC Sample and Hold refresh time register

ip_hwcfgr0: IP_HWCFGR0

0x3f0 - DAC IP Hardware Configuration Register

verr: VERR

0x3f4 - EXTI IP Version register

ipidr: IPIDR

0x3f8 - EXTI Identification register

sidr: SIDR

0x3fc - EXTI Size ID register

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