[−][src]Type Definition stm32g0::stm32g030::adc::cfgr1::W
type W = W<u32, CFGR1>;
Writer for register CFGR1
Methods
impl W[src]
pub fn awdch1ch(&mut self) -> AWDCH1CH_W[src]
Bits 26:30 - ADC analog watchdog 1 monitored channel selection
pub fn awd1en(&mut self) -> AWD1EN_W[src]
Bit 23 - ADC analog watchdog 1 enable on scope ADC group regular
pub fn awd1sgl(&mut self) -> AWD1SGL_W[src]
Bit 22 - ADC analog watchdog 1 monitoring a single channel or all channels
pub fn chselrmod(&mut self) -> CHSELRMOD_W[src]
Bit 21 - Mode selection of the ADC_CHSELR register
pub fn discen(&mut self) -> DISCEN_W[src]
Bit 16 - ADC group regular sequencer discontinuous mode
pub fn autoff(&mut self) -> AUTOFF_W[src]
Bit 15 - Auto-off mode
pub fn wait(&mut self) -> WAIT_W[src]
Bit 14 - Wait conversion mode
pub fn cont(&mut self) -> CONT_W[src]
Bit 13 - ADC group regular continuous conversion mode
pub fn ovrmod(&mut self) -> OVRMOD_W[src]
Bit 12 - ADC group regular overrun configuration
pub fn exten(&mut self) -> EXTEN_W[src]
Bits 10:11 - ADC group regular external trigger polarity
pub fn extsel(&mut self) -> EXTSEL_W[src]
Bits 6:8 - ADC group regular external trigger source
pub fn align(&mut self) -> ALIGN_W[src]
Bit 5 - ADC data alignement
pub fn res(&mut self) -> RES_W[src]
Bits 3:4 - ADC data resolution
pub fn scandir(&mut self) -> SCANDIR_W[src]
Bit 2 - Scan sequence direction
pub fn dmacfg(&mut self) -> DMACFG_W[src]
Bit 1 - ADC DMA transfer configuration
pub fn dmaen(&mut self) -> DMAEN_W[src]
Bit 0 - ADC DMA transfer enable