Module rcc

Source
Expand description

Reset and clock control

Modules§

ahbenr
AHB peripheral clock enable register
ahbrstr
AHB peripheral reset register
ahbsmenr
AHB peripheral clock enable in Sleep mode register
apbenr1
APB peripheral clock enable register 1
apbenr2
APB peripheral clock enable register 2
apbrstr1
APB peripheral reset register 1
apbrstr2
APB peripheral reset register 2
apbsmenr1
APB peripheral clock enable in Sleep mode register 1
apbsmenr2
APB peripheral clock enable in Sleep mode register 2
bdcr
RTC domain control register
ccipr
Peripherals independent clock configuration register
ccipr2
Peripherals independent clock configuration register 2
cfgr
Clock configuration register
cicr
Clock interrupt clear register
cier
Clock interrupt enable register
cifr
Clock interrupt flag register
cr
Clock control register
csr
Control/status register
icscr
Internal clock sources calibration register
iopenr
GPIO clock enable register
ioprstr
I/O port reset register
iopsmenr
GPIO in Sleep mode clock enable register
pllcfgr
PLL configuration register

Structs§

RegisterBlock
Register block

Type Aliases§

AHBENR
AHBENR (rw) register accessor: AHB peripheral clock enable register
AHBRSTR
AHBRSTR (rw) register accessor: AHB peripheral reset register
AHBSMENR
AHBSMENR (rw) register accessor: AHB peripheral clock enable in Sleep mode register
APBENR1
APBENR1 (rw) register accessor: APB peripheral clock enable register 1
APBENR2
APBENR2 (rw) register accessor: APB peripheral clock enable register 2
APBRSTR1
APBRSTR1 (rw) register accessor: APB peripheral reset register 1
APBRSTR2
APBRSTR2 (rw) register accessor: APB peripheral reset register 2
APBSMENR1
APBSMENR1 (rw) register accessor: APB peripheral clock enable in Sleep mode register 1
APBSMENR2
APBSMENR2 (rw) register accessor: APB peripheral clock enable in Sleep mode register 2
BDCR
BDCR (rw) register accessor: RTC domain control register
CCIPR
CCIPR (rw) register accessor: Peripherals independent clock configuration register
CCIPR2
CCIPR2 (rw) register accessor: Peripherals independent clock configuration register 2
CFGR
CFGR (rw) register accessor: Clock configuration register
CICR
CICR (w) register accessor: Clock interrupt clear register
CIER
CIER (rw) register accessor: Clock interrupt enable register
CIFR
CIFR (r) register accessor: Clock interrupt flag register
CR
CR (rw) register accessor: Clock control register
CSR
CSR (rw) register accessor: Control/status register
ICSCR
ICSCR (rw) register accessor: Internal clock sources calibration register
IOPENR
IOPENR (rw) register accessor: GPIO clock enable register
IOPRSTR
IOPRSTR (rw) register accessor: I/O port reset register
IOPSMENR
IOPSMENR (rw) register accessor: GPIO in Sleep mode clock enable register
PLLCFGR
PLLCFGR (rw) register accessor: PLL configuration register