stm32g0_staging/stm32g0b0/
rcc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    icscr: ICSCR,
7    cfgr: CFGR,
8    pllcfgr: PLLCFGR,
9    _reserved4: [u8; 0x08],
10    cier: CIER,
11    cifr: CIFR,
12    cicr: CICR,
13    ioprstr: IOPRSTR,
14    ahbrstr: AHBRSTR,
15    apbrstr1: APBRSTR1,
16    apbrstr2: APBRSTR2,
17    iopenr: IOPENR,
18    ahbenr: AHBENR,
19    apbenr1: APBENR1,
20    apbenr2: APBENR2,
21    iopsmenr: IOPSMENR,
22    ahbsmenr: AHBSMENR,
23    apbsmenr1: APBSMENR1,
24    apbsmenr2: APBSMENR2,
25    ccipr: CCIPR,
26    ccipr2: CCIPR2,
27    bdcr: BDCR,
28    csr: CSR,
29}
30impl RegisterBlock {
31    ///0x00 - Clock control register
32    #[inline(always)]
33    pub const fn cr(&self) -> &CR {
34        &self.cr
35    }
36    ///0x04 - Internal clock sources calibration register
37    #[inline(always)]
38    pub const fn icscr(&self) -> &ICSCR {
39        &self.icscr
40    }
41    ///0x08 - Clock configuration register
42    #[inline(always)]
43    pub const fn cfgr(&self) -> &CFGR {
44        &self.cfgr
45    }
46    ///0x0c - PLL configuration register
47    #[inline(always)]
48    pub const fn pllcfgr(&self) -> &PLLCFGR {
49        &self.pllcfgr
50    }
51    ///0x18 - Clock interrupt enable register
52    #[inline(always)]
53    pub const fn cier(&self) -> &CIER {
54        &self.cier
55    }
56    ///0x1c - Clock interrupt flag register
57    #[inline(always)]
58    pub const fn cifr(&self) -> &CIFR {
59        &self.cifr
60    }
61    ///0x20 - Clock interrupt clear register
62    #[inline(always)]
63    pub const fn cicr(&self) -> &CICR {
64        &self.cicr
65    }
66    ///0x24 - I/O port reset register
67    #[inline(always)]
68    pub const fn ioprstr(&self) -> &IOPRSTR {
69        &self.ioprstr
70    }
71    ///0x28 - AHB peripheral reset register
72    #[inline(always)]
73    pub const fn ahbrstr(&self) -> &AHBRSTR {
74        &self.ahbrstr
75    }
76    ///0x2c - APB peripheral reset register 1
77    #[inline(always)]
78    pub const fn apbrstr1(&self) -> &APBRSTR1 {
79        &self.apbrstr1
80    }
81    ///0x30 - APB peripheral reset register 2
82    #[inline(always)]
83    pub const fn apbrstr2(&self) -> &APBRSTR2 {
84        &self.apbrstr2
85    }
86    ///0x34 - GPIO clock enable register
87    #[inline(always)]
88    pub const fn iopenr(&self) -> &IOPENR {
89        &self.iopenr
90    }
91    ///0x38 - AHB peripheral clock enable register
92    #[inline(always)]
93    pub const fn ahbenr(&self) -> &AHBENR {
94        &self.ahbenr
95    }
96    ///0x3c - APB peripheral clock enable register 1
97    #[inline(always)]
98    pub const fn apbenr1(&self) -> &APBENR1 {
99        &self.apbenr1
100    }
101    ///0x40 - APB peripheral clock enable register 2
102    #[inline(always)]
103    pub const fn apbenr2(&self) -> &APBENR2 {
104        &self.apbenr2
105    }
106    ///0x44 - GPIO in Sleep mode clock enable register
107    #[inline(always)]
108    pub const fn iopsmenr(&self) -> &IOPSMENR {
109        &self.iopsmenr
110    }
111    ///0x48 - AHB peripheral clock enable in Sleep mode register
112    #[inline(always)]
113    pub const fn ahbsmenr(&self) -> &AHBSMENR {
114        &self.ahbsmenr
115    }
116    ///0x4c - APB peripheral clock enable in Sleep mode register 1
117    #[inline(always)]
118    pub const fn apbsmenr1(&self) -> &APBSMENR1 {
119        &self.apbsmenr1
120    }
121    ///0x50 - APB peripheral clock enable in Sleep mode register 2
122    #[inline(always)]
123    pub const fn apbsmenr2(&self) -> &APBSMENR2 {
124        &self.apbsmenr2
125    }
126    ///0x54 - Peripherals independent clock configuration register
127    #[inline(always)]
128    pub const fn ccipr(&self) -> &CCIPR {
129        &self.ccipr
130    }
131    ///0x58 - Peripherals independent clock configuration register 2
132    #[inline(always)]
133    pub const fn ccipr2(&self) -> &CCIPR2 {
134        &self.ccipr2
135    }
136    ///0x5c - RTC domain control register
137    #[inline(always)]
138    pub const fn bdcr(&self) -> &BDCR {
139        &self.bdcr
140    }
141    ///0x60 - Control/status register
142    #[inline(always)]
143    pub const fn csr(&self) -> &CSR {
144        &self.csr
145    }
146}
147/**CR (rw) register accessor: Clock control register
148
149You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
150
151See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:CR)
152
153For information about available fields see [`mod@cr`]
154module*/
155pub type CR = crate::Reg<cr::CRrs>;
156///Clock control register
157pub mod cr;
158/**ICSCR (rw) register accessor: Internal clock sources calibration register
159
160You can [`read`](crate::Reg::read) this register and get [`icscr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icscr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
161
162See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:ICSCR)
163
164For information about available fields see [`mod@icscr`]
165module*/
166pub type ICSCR = crate::Reg<icscr::ICSCRrs>;
167///Internal clock sources calibration register
168pub mod icscr;
169/**CFGR (rw) register accessor: Clock configuration register
170
171You can [`read`](crate::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
172
173See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:CFGR)
174
175For information about available fields see [`mod@cfgr`]
176module*/
177pub type CFGR = crate::Reg<cfgr::CFGRrs>;
178///Clock configuration register
179pub mod cfgr;
180/**PLLCFGR (rw) register accessor: PLL configuration register
181
182You can [`read`](crate::Reg::read) this register and get [`pllcfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pllcfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
183
184See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:PLLCFGR)
185
186For information about available fields see [`mod@pllcfgr`]
187module*/
188pub type PLLCFGR = crate::Reg<pllcfgr::PLLCFGRrs>;
189///PLL configuration register
190pub mod pllcfgr;
191/**CIER (rw) register accessor: Clock interrupt enable register
192
193You can [`read`](crate::Reg::read) this register and get [`cier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
194
195See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:CIER)
196
197For information about available fields see [`mod@cier`]
198module*/
199pub type CIER = crate::Reg<cier::CIERrs>;
200///Clock interrupt enable register
201pub mod cier;
202/**CIFR (r) register accessor: Clock interrupt flag register
203
204You can [`read`](crate::Reg::read) this register and get [`cifr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
205
206See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:CIFR)
207
208For information about available fields see [`mod@cifr`]
209module*/
210pub type CIFR = crate::Reg<cifr::CIFRrs>;
211///Clock interrupt flag register
212pub mod cifr;
213/**CICR (w) register accessor: Clock interrupt clear register
214
215You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cicr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
216
217See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:CICR)
218
219For information about available fields see [`mod@cicr`]
220module*/
221pub type CICR = crate::Reg<cicr::CICRrs>;
222///Clock interrupt clear register
223pub mod cicr;
224/**IOPRSTR (rw) register accessor: I/O port reset register
225
226You can [`read`](crate::Reg::read) this register and get [`ioprstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioprstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
227
228See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:IOPRSTR)
229
230For information about available fields see [`mod@ioprstr`]
231module*/
232pub type IOPRSTR = crate::Reg<ioprstr::IOPRSTRrs>;
233///I/O port reset register
234pub mod ioprstr;
235/**AHBRSTR (rw) register accessor: AHB peripheral reset register
236
237You can [`read`](crate::Reg::read) this register and get [`ahbrstr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbrstr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
238
239See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:AHBRSTR)
240
241For information about available fields see [`mod@ahbrstr`]
242module*/
243pub type AHBRSTR = crate::Reg<ahbrstr::AHBRSTRrs>;
244///AHB peripheral reset register
245pub mod ahbrstr;
246/**APBRSTR1 (rw) register accessor: APB peripheral reset register 1
247
248You can [`read`](crate::Reg::read) this register and get [`apbrstr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbrstr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
249
250See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:APBRSTR1)
251
252For information about available fields see [`mod@apbrstr1`]
253module*/
254pub type APBRSTR1 = crate::Reg<apbrstr1::APBRSTR1rs>;
255///APB peripheral reset register 1
256pub mod apbrstr1;
257/**APBRSTR2 (rw) register accessor: APB peripheral reset register 2
258
259You can [`read`](crate::Reg::read) this register and get [`apbrstr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbrstr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
260
261See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:APBRSTR2)
262
263For information about available fields see [`mod@apbrstr2`]
264module*/
265pub type APBRSTR2 = crate::Reg<apbrstr2::APBRSTR2rs>;
266///APB peripheral reset register 2
267pub mod apbrstr2;
268/**IOPENR (rw) register accessor: GPIO clock enable register
269
270You can [`read`](crate::Reg::read) this register and get [`iopenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iopenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
271
272See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:IOPENR)
273
274For information about available fields see [`mod@iopenr`]
275module*/
276pub type IOPENR = crate::Reg<iopenr::IOPENRrs>;
277///GPIO clock enable register
278pub mod iopenr;
279/**AHBENR (rw) register accessor: AHB peripheral clock enable register
280
281You can [`read`](crate::Reg::read) this register and get [`ahbenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
282
283See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:AHBENR)
284
285For information about available fields see [`mod@ahbenr`]
286module*/
287pub type AHBENR = crate::Reg<ahbenr::AHBENRrs>;
288///AHB peripheral clock enable register
289pub mod ahbenr;
290/**APBENR1 (rw) register accessor: APB peripheral clock enable register 1
291
292You can [`read`](crate::Reg::read) this register and get [`apbenr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbenr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
293
294See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:APBENR1)
295
296For information about available fields see [`mod@apbenr1`]
297module*/
298pub type APBENR1 = crate::Reg<apbenr1::APBENR1rs>;
299///APB peripheral clock enable register 1
300pub mod apbenr1;
301/**APBENR2 (rw) register accessor: APB peripheral clock enable register 2
302
303You can [`read`](crate::Reg::read) this register and get [`apbenr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbenr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
304
305See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:APBENR2)
306
307For information about available fields see [`mod@apbenr2`]
308module*/
309pub type APBENR2 = crate::Reg<apbenr2::APBENR2rs>;
310///APB peripheral clock enable register 2
311pub mod apbenr2;
312/**IOPSMENR (rw) register accessor: GPIO in Sleep mode clock enable register
313
314You can [`read`](crate::Reg::read) this register and get [`iopsmenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`iopsmenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
315
316See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:IOPSMENR)
317
318For information about available fields see [`mod@iopsmenr`]
319module*/
320pub type IOPSMENR = crate::Reg<iopsmenr::IOPSMENRrs>;
321///GPIO in Sleep mode clock enable register
322pub mod iopsmenr;
323/**AHBSMENR (rw) register accessor: AHB peripheral clock enable in Sleep mode register
324
325You can [`read`](crate::Reg::read) this register and get [`ahbsmenr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbsmenr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
326
327See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:AHBSMENR)
328
329For information about available fields see [`mod@ahbsmenr`]
330module*/
331pub type AHBSMENR = crate::Reg<ahbsmenr::AHBSMENRrs>;
332///AHB peripheral clock enable in Sleep mode register
333pub mod ahbsmenr;
334/**APBSMENR1 (rw) register accessor: APB peripheral clock enable in Sleep mode register 1
335
336You can [`read`](crate::Reg::read) this register and get [`apbsmenr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbsmenr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
337
338See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:APBSMENR1)
339
340For information about available fields see [`mod@apbsmenr1`]
341module*/
342pub type APBSMENR1 = crate::Reg<apbsmenr1::APBSMENR1rs>;
343///APB peripheral clock enable in Sleep mode register 1
344pub mod apbsmenr1;
345/**APBSMENR2 (rw) register accessor: APB peripheral clock enable in Sleep mode register 2
346
347You can [`read`](crate::Reg::read) this register and get [`apbsmenr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apbsmenr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
348
349See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:APBSMENR2)
350
351For information about available fields see [`mod@apbsmenr2`]
352module*/
353pub type APBSMENR2 = crate::Reg<apbsmenr2::APBSMENR2rs>;
354///APB peripheral clock enable in Sleep mode register 2
355pub mod apbsmenr2;
356/**CCIPR (rw) register accessor: Peripherals independent clock configuration register
357
358You can [`read`](crate::Reg::read) this register and get [`ccipr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccipr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
359
360See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:CCIPR)
361
362For information about available fields see [`mod@ccipr`]
363module*/
364pub type CCIPR = crate::Reg<ccipr::CCIPRrs>;
365///Peripherals independent clock configuration register
366pub mod ccipr;
367/**CCIPR2 (rw) register accessor: Peripherals independent clock configuration register 2
368
369You can [`read`](crate::Reg::read) this register and get [`ccipr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccipr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
370
371See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:CCIPR2)
372
373For information about available fields see [`mod@ccipr2`]
374module*/
375pub type CCIPR2 = crate::Reg<ccipr2::CCIPR2rs>;
376///Peripherals independent clock configuration register 2
377pub mod ccipr2;
378/**BDCR (rw) register accessor: RTC domain control register
379
380You can [`read`](crate::Reg::read) this register and get [`bdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
381
382See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:BDCR)
383
384For information about available fields see [`mod@bdcr`]
385module*/
386pub type BDCR = crate::Reg<bdcr::BDCRrs>;
387///RTC domain control register
388pub mod bdcr;
389/**CSR (rw) register accessor: Control/status register
390
391You can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
392
393See register [structure](https://stm32-rs.github.io/stm32-rs/STM32G0B0.html#RCC:CSR)
394
395For information about available fields see [`mod@csr`]
396module*/
397pub type CSR = crate::Reg<csr::CSRrs>;
398///Control/status register
399pub mod csr;
stm32g0_staging/stm32g0b0/rcc.rs

stm32g0_staging/stm32g0b0/
rcc.rs
