pub enum CHSELRMOD {
BitPerInput = 0,
Sequence = 1,
}
Expand description
Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored.
Value on reset: 0
Variants§
BitPerInput = 0
0: Each bit of the ADC_CHSELR register enables an input
Sequence = 1
1: ADC_CHSELR register is able to sequence up to 8 channels
Trait Implementations§
impl Copy for CHSELRMOD
impl Eq for CHSELRMOD
impl StructuralPartialEq for CHSELRMOD
Auto Trait Implementations§
impl Freeze for CHSELRMOD
impl RefUnwindSafe for CHSELRMOD
impl Send for CHSELRMOD
impl Sync for CHSELRMOD
impl Unpin for CHSELRMOD
impl UnwindSafe for CHSELRMOD
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more