Struct stm32f7xx_hal::pac::tim1::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 21 fields
pub cr1: Reg<u32, _CR1>,
pub cr2: Reg<u32, _CR2>,
pub smcr: Reg<u32, _SMCR>,
pub dier: Reg<u32, _DIER>,
pub sr: Reg<u32, _SR>,
pub egr: Reg<u32, _EGR>,
pub ccer: Reg<u32, _CCER>,
pub cnt: Reg<u32, _CNT>,
pub psc: Reg<u32, _PSC>,
pub arr: Reg<u32, _ARR>,
pub rcr: Reg<u32, _RCR>,
pub ccr1: Reg<u32, _CCR>,
pub ccr2: Reg<u32, _CCR>,
pub ccr3: Reg<u32, _CCR>,
pub ccr4: Reg<u32, _CCR>,
pub bdtr: Reg<u32, _BDTR>,
pub dcr: Reg<u32, _DCR>,
pub dmar: Reg<u32, _DMAR>,
pub ccmr3_output: Reg<u32, _CCMR3_OUTPUT>,
pub ccr5: Reg<u32, _CCR5>,
pub crr6: Reg<u32, _CRR6>,
// some fields omitted
}
Expand description
Register block
Fields
cr1: Reg<u32, _CR1>
0x00 - control register 1
cr2: Reg<u32, _CR2>
0x04 - control register 2
smcr: Reg<u32, _SMCR>
0x08 - slave mode control register
dier: Reg<u32, _DIER>
0x0c - DMA/Interrupt enable register
sr: Reg<u32, _SR>
0x10 - status register
egr: Reg<u32, _EGR>
0x14 - event generation register
ccer: Reg<u32, _CCER>
0x20 - capture/compare enable register
cnt: Reg<u32, _CNT>
0x24 - counter
psc: Reg<u32, _PSC>
0x28 - prescaler
arr: Reg<u32, _ARR>
0x2c - auto-reload register
rcr: Reg<u32, _RCR>
0x30 - repetition counter register
ccr1: Reg<u32, _CCR>
0x34 - capture/compare register 1
ccr2: Reg<u32, _CCR>
0x38 - capture/compare register 1
ccr3: Reg<u32, _CCR>
0x3c - capture/compare register 1
ccr4: Reg<u32, _CCR>
0x40 - capture/compare register 1
bdtr: Reg<u32, _BDTR>
0x44 - break and dead-time register
dcr: Reg<u32, _DCR>
0x48 - DMA control register
dmar: Reg<u32, _DMAR>
0x4c - DMA address for full transfer
ccmr3_output: Reg<u32, _CCMR3_OUTPUT>
0x54 - capture/compare mode register 3 (output mode)
ccr5: Reg<u32, _CCR5>
0x58 - capture/compare register 5
crr6: Reg<u32, _CRR6>
0x5c - capture/compare register 6
Implementations
0x18 - capture/compare mode register 1 (input mode)
0x18 - capture/compare mode register 1 (input mode)
0x18 - capture/compare mode register 1 (output mode)
0x18 - capture/compare mode register 1 (output mode)
0x1c - capture/compare mode register 2 (input mode)
0x1c - capture/compare mode register 2 (input mode)
0x1c - capture/compare mode register 2 (output mode)
0x1c - capture/compare mode register 2 (output mode)