Struct stm32f7x6::rcc::pllcfgr::R
[−]
[src]
pub struct R { /* fields omitted */ }Value read from the register
Methods
impl R[src]
pub fn bits(&self) -> u32[src]
Value of the register as raw bits
pub fn pllq3(&self) -> PLLQ3R[src]
Bit 27 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
pub fn pllq2(&self) -> PLLQ2R[src]
Bit 26 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
pub fn pllq1(&self) -> PLLQ1R[src]
Bit 25 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
pub fn pllq0(&self) -> PLLQ0R[src]
Bit 24 - Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
pub fn pllsrc(&self) -> PLLSRCR[src]
Bit 22 - Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
pub fn pllp1(&self) -> PLLP1R[src]
Bit 17 - Main PLL (PLL) division factor for main system clock
pub fn pllp0(&self) -> PLLP0R[src]
Bit 16 - Main PLL (PLL) division factor for main system clock
pub fn plln8(&self) -> PLLN8R[src]
Bit 14 - Main PLL (PLL) multiplication factor for VCO
pub fn plln7(&self) -> PLLN7R[src]
Bit 13 - Main PLL (PLL) multiplication factor for VCO
pub fn plln6(&self) -> PLLN6R[src]
Bit 12 - Main PLL (PLL) multiplication factor for VCO
pub fn plln5(&self) -> PLLN5R[src]
Bit 11 - Main PLL (PLL) multiplication factor for VCO
pub fn plln4(&self) -> PLLN4R[src]
Bit 10 - Main PLL (PLL) multiplication factor for VCO
pub fn plln3(&self) -> PLLN3R[src]
Bit 9 - Main PLL (PLL) multiplication factor for VCO
pub fn plln2(&self) -> PLLN2R[src]
Bit 8 - Main PLL (PLL) multiplication factor for VCO
pub fn plln1(&self) -> PLLN1R[src]
Bit 7 - Main PLL (PLL) multiplication factor for VCO
pub fn plln0(&self) -> PLLN0R[src]
Bit 6 - Main PLL (PLL) multiplication factor for VCO
pub fn pllm5(&self) -> PLLM5R[src]
Bit 5 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
pub fn pllm4(&self) -> PLLM4R[src]
Bit 4 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
pub fn pllm3(&self) -> PLLM3R[src]
Bit 3 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
pub fn pllm2(&self) -> PLLM2R[src]
Bit 2 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
pub fn pllm1(&self) -> PLLM1R[src]
Bit 1 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
pub fn pllm0(&self) -> PLLM0R[src]
Bit 0 - Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock