Module stm32f4xx_hal::rcc

Clock configuration.

This module provides functionality to configure the RCC to generate the requested clocks.

Example

let dp = pac::Peripherals::take().unwrap();
let rcc = dp.RCC.constrain();
let clocks = rcc
    .cfgr
    .use_hse(8.MHz())
    .sysclk(168.MHz())
    .pclk1(24.MHz())
    .i2s_clk(86.MHz())
    .require_pll48clk()
    .freeze();
    // Test that the I2S clock is suitable for 48000kHz audio.
    assert!(clocks.i2s_clk().unwrap() == 48.MHz().into());

Limitations

Unlike the clock configuration tool provided by ST, the code does not extensively search all possible configurations. Instead, it often relies on an iterative approach to reduce computational complexity. On most MCUs the code will first generate a configuration for the 48 MHz clock and the system clock without taking other requested clocks into account, even if the accuracy of these clocks is affected. If you specific accuracy requirements, you should always check the resulting frequencies!

Whereas the hardware often supports flexible clock source selection and many clocks can be sourced from multiple PLLs, the code implements a fixed mapping between PLLs and clocks. The 48 MHz clock is always generated by the main PLL, the I2S clocks are always generated by the I2S PLL (unless a matching external clock input is provided), and similarly the SAI clocks are always generated by the SAI PLL. It is therefore not possible to, for example, specify two different I2S frequencies unless you also provide a matching I2S_CKIN signal for one of them.

Some MCUs have limited clock generation hardware and do not provide either I2S or SAI PLLs even though I2S or SAI are available. On the STM32F410, the I2S clock is generated by the main PLL, and on the STM32F413/423 SAI clocks are generated by the I2S PLL. On these MCUs, the actual frequencies may substantially deviate from the requested frequencies.

Structs

• AHB1
  Advanced High-performance Bus 1 (AHB1) registers
• AHB2
  Advanced High-performance Bus 2 (AHB2) registers
• AHB3
  AMBA High-performance Bus 3 (AHB3) registers
• APB1
  Advanced Peripheral Bus 1 (APB1) registers
• APB2
  Advanced Peripheral Bus 2 (APB2) registers
• CFGR
• Clocks
  Frozen clock frequencies
• Rcc
  Constrained RCC peripheral

Constants

• HSI
  Built-in high speed clock frequency
• PCLK1_MAX
  Maximum APB1 peripheral clock frequency
• PCLK2_MAX
  Maximum APB2 peripheral clock frequency
• SYSCLK_MAX
  Maximum system clock frequency
• SYSCLK_MIN
  Minimum system clock frequency

Traits

• BusClock
  Frequency on bus that peripheral is connected in
• BusTimerClock
  Frequency on bus that timer is connected in
• Enable
  Enable/disable peripheral
• LPEnable
  Low power enable/disable peripheral
• RccBus
  Bus associated to peripheral
• RccExt
  Extension trait that constrains the RCC peripheral
• Reset
  Reset peripheral